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[Qemu-commits] [qemu/qemu] 8cd0b4: target/mips: Add CP0 Config0 register
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] 8cd0b4: target/mips: Add CP0 Config0 register definitions ... |
Date: |
Fri, 15 Jan 2021 05:38:55 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 8cd0b410a24159891809ba5f41fa55abb5adf196
https://github.com/qemu/qemu/commit/8cd0b410a24159891809ba5f41fa55abb5adf196
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/cpu.h
Log Message:
-----------
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201201132817.2863301-2-f4bug@amsat.org>
Commit: b4cbbb47b0143bcf4e07a6bda5bb98b3f69c6c24
https://github.com/qemu/qemu/commit/b4cbbb47b0143bcf4e07a6bda5bb98b3f69c6c24
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Replace CP0_Config0 magic values by proper definitions
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201201132817.2863301-3-f4bug@amsat.org>
Commit: 07ae8ccd0fc4ab5a9766ebc1486ed81a1b4c5f41
https://github.com/qemu/qemu/commit/07ae8ccd0fc4ab5a9766ebc1486ed81a1b4c5f41
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/addr.c
M target/mips/cpu.h
Log Message:
-----------
target/mips/addr: Add translation helpers for KSEG1
It's useful for bootloader to do I/O operations.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Message-Id: <20201215064507.30148-3-jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 737cca57d3f3a2dd10ef397a33a97de619a5456a
https://github.com/qemu/qemu/commit/737cca57d3f3a2dd10ef397a33a97de619a5456a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
Remove a comment added 12 years ago but never used (commit
b6d96beda3a: "Use temporary registers for the MIPS FPU emulation").
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-2-f4bug@amsat.org>
Commit: bf5523773eac7a17cf6f6a062b3311a09063881f
https://github.com/qemu/qemu/commit/bf5523773eac7a17cf6f6a062b3311a09063881f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Reorder CPU_MIPS5 definition
Move CPU_MIPS5 after CPU_MIPS4 :)
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-3-f4bug@amsat.org>
Commit: 8b0ea9b638adadcf056f4a18fe53a7c6339beba8
https://github.com/qemu/qemu/commit/8b0ea9b638adadcf056f4a18fe53a7c6339beba8
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
Commit: b0586b38cb51dccb25a1957796e34ecd99c8fbf7
https://github.com/qemu/qemu/commit/b0586b38cb51dccb25a1957796e34ecd99c8fbf7
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/cpu.h
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
MIPS 64-bit ISA is introduced with MIPS3.
Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
and the cpu_type_is_64bit() method to check if a CPU supports
this ISA (thus is 64-bit).
Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-5-f4bug@amsat.org>
Commit: ce49581feb1006be21707713d86c05bb189e3f66
https://github.com/qemu/qemu/commit/ce49581feb1006be21707713d86c05bb189e3f66
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M hw/mips/boston.c
Log Message:
-----------
hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
Directly check if the CPU supports 64-bit with the recently
added cpu_type_is_64bit() helper (inlined).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-6-f4bug@amsat.org>
Commit: 08e2262fada2de06232e8099bddf6e03df015c5a
https://github.com/qemu/qemu/commit/08e2262fada2de06232e8099bddf6e03df015c5a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
Use the single ISA_MIPS32 definition to check if the Release 1
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R1 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-7-f4bug@amsat.org>
Commit: f395cef7656e794a5c6c007bdf661603410640d8
https://github.com/qemu/qemu/commit/f395cef7656e794a5c6c007bdf661603410640d8
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M linux-user/mips/cpu_loop.c
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
Use the single ISA_MIPS32R2 definition to check if the Release 2
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R2 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-8-f4bug@amsat.org>
Commit: 4d1524d2ce2f809ae514b23f8e9d502d051c6df4
https://github.com/qemu/qemu/commit/4d1524d2ce2f809ae514b23f8e9d502d051c6df4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
Use the single ISA_MIPS32R3 definition to check if the Release 3
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R3 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-9-f4bug@amsat.org>
Commit: d913c3992dfd9506a8201c2995d7c910a18db92f
https://github.com/qemu/qemu/commit/d913c3992dfd9506a8201c2995d7c910a18db92f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
Use the single ISA_MIPS32R5 definition to check if the Release 5
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R5 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-10-f4bug@amsat.org>
Commit: 13514fc93e6b2ead6e984bcd104975b6b4f375e8
https://github.com/qemu/qemu/commit/13514fc93e6b2ead6e984bcd104975b6b4f375e8
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M linux-user/mips/cpu_loop.c
M target/mips/helper.c
M target/mips/internal.h
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
Commit: bbd5e4a27f0e4e717f9bdf35fd9c1f42410dea04
https://github.com/qemu/qemu/commit/bbd5e4a27f0e4e717f9bdf35fd9c1f42410dea04
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/internal.h
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
The MIPS ISA release '1' is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-12-f4bug@amsat.org>
Commit: 7a47bae586865498ac55531141d9c3d4d9e3ff83
https://github.com/qemu/qemu/commit/7a47bae586865498ac55531141d9c3d4d9e3ff83
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M linux-user/mips/cpu_loop.c
M target/mips/cp0_timer.c
M target/mips/helper.c
M target/mips/internal.h
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
The MIPS ISA release 2 is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
Commit: bae4b15aa4fa56815e08cee395486a1c990caa99
https://github.com/qemu/qemu/commit/bae4b15aa4fa56815e08cee395486a1c990caa99
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
The MIPS ISA release 3 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-14-f4bug@amsat.org>
Commit: 5f89ce4fc2afdb81eaed90f337d7016207a2b176
https://github.com/qemu/qemu/commit/5f89ce4fc2afdb81eaed90f337d7016207a2b176
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
The MIPS ISA release 5 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-15-f4bug@amsat.org>
Commit: 2e211e0a12e6cde512b65d25799bb3ac25baa371
https://github.com/qemu/qemu/commit/2e211e0a12e6cde512b65d25799bb3ac25baa371
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M linux-user/mips/cpu_loop.c
M target/mips/cp0_helper.c
M target/mips/cpu.c
M target/mips/fpu_helper.c
M target/mips/helper.c
M target/mips/internal.h
M target/mips/mips-defs.h
M target/mips/translate.c
Log Message:
-----------
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
The MIPS ISA release 6 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
Commit: 9bcd41d41fb4fd9efbc2fd657a4a12c614e78412
https://github.com/qemu/qemu/commit/9bcd41d41fb4fd9efbc2fd657a4a12c614e78412
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/cpu.c
Log Message:
-----------
target/mips: Inline cpu_state_reset() in mips_cpu_reset()
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-2-f4bug@amsat.org>
Commit: 81ddae7c3095065466d235f782aa2af620db78d0
https://github.com/qemu/qemu/commit/81ddae7c3095065466d235f782aa2af620db78d0
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M linux-user/mips/cpu_loop.c
M target/mips/fpu_helper.c
A target/mips/fpu_helper.h
M target/mips/gdbstub.c
M target/mips/internal.h
M target/mips/kvm.c
M target/mips/machine.c
M target/mips/msa_helper.c
M target/mips/op_helper.c
M target/mips/translate.c
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Extract FPU helpers to 'fpu_helper.h'
Extract FPU specific helpers from "internal.h" to "fpu_helper.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201120210844.2625602-2-f4bug@amsat.org>
Commit: f9bd3d79f4f636ea9c9ce6dd2b6ad71b776458d6
https://github.com/qemu/qemu/commit/f9bd3d79f4f636ea9c9ce6dd2b6ad71b776458d6
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/helper.c
Log Message:
-----------
target/mips: Add !CONFIG_USER_ONLY comment after #endif
To help understand ifdef'ry, add comment after #endif.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-4-f4bug@amsat.org>
Commit: 2be565f9c2f8c2a1eb40efb86175e9f0c76761a4
https://github.com/qemu/qemu/commit/2be565f9c2f8c2a1eb40efb86175e9f0c76761a4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/helper.c
Log Message:
-----------
target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-5-f4bug@amsat.org>
Commit: e9927723ba928230222d68ece45d232ed602e78a
https://github.com/qemu/qemu/commit/e9927723ba928230222d68ece45d232ed602e78a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/helper.c
M target/mips/internal.h
Log Message:
-----------
target/mips: Move common helpers from helper.c to cpu.c
The rest of helper.c is TLB related. Extract the non TLB
specific functions to cpu.c, so we can rename helper.c as
tlb_helper.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-6-f4bug@amsat.org>
Commit: 4cb213dc90dfc53e447b057fe45d44ddfafc9933
https://github.com/qemu/qemu/commit/4cb213dc90dfc53e447b057fe45d44ddfafc9933
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
R target/mips/helper.c
M target/mips/meson.build
A target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Rename helper.c as tlb_helper.c
This file contains functions related to TLB management,
rename it as 'tlb_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-13-f4bug@amsat.org>
Commit: ca2690e36a96ca17c50f2be8aaa63d782e2126c3
https://github.com/qemu/qemu/commit/ca2690e36a96ca17c50f2be8aaa63d782e2126c3
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Fix code style for checkpatch.pl
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-14-f4bug@amsat.org>
Commit: f2c5b39ecdcc3d99f53517c18acfb950bfeecfd3
https://github.com/qemu/qemu/commit/f2c5b39ecdcc3d99f53517c18acfb950bfeecfd3
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/internal.h
M target/mips/tlb_helper.c
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Move mmu_init() functions to tlb_helper.c
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-15-f4bug@amsat.org>
Commit: 0dc351ca6bf5ffbdb63bbecf718d4917491b2c28
https://github.com/qemu/qemu/commit/0dc351ca6bf5ffbdb63bbecf718d4917491b2c28
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
A target/mips/cpu-defs.c.inc
M target/mips/cpu.c
R target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Rename translate_init.c as cpu-defs.c
This file is not TCG specific, contains CPU definitions
and is consumed by cpu.c. Rename it as such.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-10-f4bug@amsat.org>
Commit: e31309365e50a44ebaa6490445d877d8c4acb4f0
https://github.com/qemu/qemu/commit/e31309365e50a44ebaa6490445d877d8c4acb4f0
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
A target/mips/translate.h
Log Message:
-----------
target/mips/translate: Extract DisasContext structure
Extract DisasContext to a new 'translate.h' header so
different translation files (ISA, ASE, extensions)
can use it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207235539.4070364-2-f4bug@amsat.org>
Commit: 46c9e2b3dddc63bc85e07e3ad33fceb9d300be67
https://github.com/qemu/qemu/commit/46c9e2b3dddc63bc85e07e3ad33fceb9d300be67
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips/translate: Add declarations for generic code
Some CPU translation functions / registers / macros and
definitions can be used by ISA / ASE / extensions out of
the big translate.c file. Declare them in "translate.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207235539.4070364-3-f4bug@amsat.org>
Commit: 11a7511856a059796812f7c25ceca6b35cae4b3e
https://github.com/qemu/qemu/commit/11a7511856a059796812f7c25ceca6b35cae4b3e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
generate_exception_err(err=0) is simply generate_exception_end().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-11-f4bug@amsat.org>
Commit: 3a4ef3b7ee35613f5318f27321c8255606e4623f
https://github.com/qemu/qemu/commit/3a4ef3b7ee35613f5318f27321c8255606e4623f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction
gen_reserved_instruction() is easier to read than
generate_exception_end(ctx, EXCP_RI), replace it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-12-f4bug@amsat.org>
Commit: 8758d1b8aa3ee91b294ea862f89092c20428928e
https://github.com/qemu/qemu/commit/8758d1b8aa3ee91b294ea862f89092c20428928e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Declare generic FPU / Coprocessor functions in translate.h
Some FPU / Coprocessor translation functions / registers can be
used by ISA / ASE / extensions out of the big translate.c file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-15-f4bug@amsat.org>
Commit: 57eedcf7e33c9833f97101034142cd546ae839bb
https://github.com/qemu/qemu/commit/57eedcf7e33c9833f97101034142cd546ae839bb
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Extract FPU specific definitions to translate.h
Extract FPU specific definitions that can be used by
ISA / ASE / extensions to translate.h header.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-16-f4bug@amsat.org>
Commit: 8b7322add375fb13d199079368bc84e4619478fa
https://github.com/qemu/qemu/commit/8b7322add375fb13d199079368bc84e4619478fa
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/meson.build
Log Message:
-----------
target/mips: Only build TCG code when CONFIG_TCG is set
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-20-f4bug@amsat.org>
Commit: 311edee771510436fc70b2e4fbe5f9fd3cf3d14d
https://github.com/qemu/qemu/commit/311edee771510436fc70b2e4fbe5f9fd3cf3d14d
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips/translate: Extract decode_opc_legacy() from decode_opc()
As we will slowly move to decodetree generated decoders,
extract the legacy decoding from decode_opc(), so new
decoders are added in decode_opc() while old code is
removed from decode_opc_legacy().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-2-f4bug@amsat.org>
Commit: d7efb69382cde8f29cd37df321b399542db9fdd2
https://github.com/qemu/qemu/commit/d7efb69382cde8f29cd37df321b399542db9fdd2
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips/translate: Expose check_mips_64() to 32-bit mode
To allow compiling 64-bit specific translation code more
generically (and removing #ifdef'ry), allow compiling
check_mips_64() on 32-bit targets.
If ever called on 32-bit, we obviously emit a reserved
instruction exception.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201215225757.764263-3-f4bug@amsat.org>
Commit: 25a1362875874936c185eba72203de6e9581251e
https://github.com/qemu/qemu/commit/25a1362875874936c185eba72203de6e9581251e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/kvm.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Introduce ase_msa_available() helper
Instead of accessing CP0_Config3 directly and checking
the 'MSA Present' bit, introduce an explicit helper,
making the code easier to read.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-2-f4bug@amsat.org>
Commit: 72f31f60f829980ad22da8049bb41af0dc49c3f4
https://github.com/qemu/qemu/commit/72f31f60f829980ad22da8049bb41af0dc49c3f4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/cpu.c
Log Message:
-----------
target/mips: Simplify msa_reset()
Call msa_reset() unconditionally, but only reset
the MSA registers if MSA is implemented.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-3-f4bug@amsat.org>
Commit: aa314198ca8d51e5c250e83a5cf160b38db6a7d9
https://github.com/qemu/qemu/commit/aa314198ca8d51e5c250e83a5cf160b38db6a7d9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/internal.h
Log Message:
-----------
target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
MSA presence is expressed by the MSAP bit of CP0_Config3.
We don't need to check anything else.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-4-f4bug@amsat.org>
Commit: 33942f94604153af66f50ad0bc41edc620e82d51
https://github.com/qemu/qemu/commit/33942f94604153af66f50ad0bc41edc620e82d51
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Simplify MSA TCG logic
Only decode MSA opcodes if MSA is present (implemented).
Now than check_msa_access() will only be called if MSA is
present, the only way to have MIPS_HFLAG_MSA unset is if
MSA is disabled (bit CP0C5_MSAEn cleared, see previous
commit). Therefore we can remove the 'reserved instruction'
exception.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-5-f4bug@amsat.org>
Commit: 7e2a619a0436a959fe2795cce829d1cc89448a43
https://github.com/qemu/qemu/commit/7e2a619a0436a959fe2795cce829d1cc89448a43
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/mips-defs.h
Log Message:
-----------
target/mips: Remove now unused ASE_MSA definition
We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-6-f4bug@amsat.org>
Commit: e2665f314d80d7edbfe7f8275abed7e2c93c0ddc
https://github.com/qemu/qemu/commit/e2665f314d80d7edbfe7f8275abed7e2c93c0ddc
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Alias MSA vector registers on FPU scalar registers
Commits 863f264d10f ("add msa_reset(), global msa register") and
cb269f273fd ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.
It is not very clear to have FPU registers displayed with MSA
register names, even if MSA ASE is not present.
Instead of aliasing FPU registers to the MSA ones (even when MSA
is absent), we now alias the MSA ones to the FPU ones (only when
MSA is present).
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-7-f4bug@amsat.org>
Commit: 959c5da28e7e1ae59e122f952fdbad02fb754cad
https://github.com/qemu/qemu/commit/959c5da28e7e1ae59e122f952fdbad02fb754cad
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Extract msa_translate_init() from mips_tcg_init()
The msa_wr_d[] registers are only initialized/used by MSA.
They are declared static. We want to move them to the new
'msa_translate.c' unit in few commits, without having to
declare them global (with extern).
Extract first the logic initialization of the MSA registers
from the generic initialization. We will later move this
function along with the MSA registers to the new C unit.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-8-f4bug@amsat.org>
Commit: 63af5b9018e2983364d7cb4b0047cb8f566fcfe9
https://github.com/qemu/qemu/commit/63af5b9018e2983364d7cb4b0047cb8f566fcfe9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
The gen_msa*() methods don't use the "CPUMIPSState *env"
argument. Remove it to simplify.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-9-f4bug@amsat.org>
Commit: 810fda17c8ea9b93f7c2bcc48e70cf7a3dbc7e91
https://github.com/qemu/qemu/commit/810fda17c8ea9b93f7c2bcc48e70cf7a3dbc7e91
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
In preparation of using the decodetree script, explode
gen_msa_branch() as following:
- OPC_BZ_V -> BxZ_V(EQ)
- OPC_BNZ_V -> BxZ_V(NE)
- OPC_BZ_[BHWD] -> BxZ(false)
- OPC_BNZ_[BHWD] -> BxZ(true)
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-10-f4bug@amsat.org>
Commit: 03e4d95c91fb29e27b0248dd18c236c6fcc8dc02
https://github.com/qemu/qemu/commit/03e4d95c91fb29e27b0248dd18c236c6fcc8dc02
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/cpu.c
M target/mips/internal.h
M target/mips/msa_helper.c
Log Message:
-----------
target/mips: Move msa_reset() to msa_helper.c
translate_init.c.inc mostly contains CPU definitions.
msa_reset() doesn't belong here, move it with the MSA
helpers.
One comment style is updated to avoid checkpatch.pl warning.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-15-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: 3ef60574b6b9caecf539408ceb9f7fe6ece1ce08
https://github.com/qemu/qemu/commit/3ef60574b6b9caecf539408ceb9f7fe6ece1ce08
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/msa_helper.c
M target/mips/op_helper.c
Log Message:
-----------
target/mips: Extract MSA helpers from op_helper.c
We have ~400 lines of MSA helpers in the generic op_helper.c,
move them with the other helpers in 'msa_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201123204448.3260804-5-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: edb23847283341bc22ed3830edb21647f49d15dd
https://github.com/qemu/qemu/commit/edb23847283341bc22ed3830edb21647f49d15dd
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/helper.h
A target/mips/msa_helper.h.inc
Log Message:
-----------
target/mips: Extract MSA helper definitions
Keep all MSA-related code altogether.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201120210844.2625602-4-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: 54ccff51022fcb93d8b3febe18c2bd663ce15ed9
https://github.com/qemu/qemu/commit/54ccff51022fcb93d8b3febe18c2bd663ce15ed9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Declare gen_msa/_branch() in 'translate.h'
Make gen_msa() and gen_msa_branch() public declarations
so we can keep calling them once extracted from the big
translate.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-18-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: 80e64a380feb891700cbb21e4966c898dd9c5af9
https://github.com/qemu/qemu/commit/80e64a380feb891700cbb21e4966c898dd9c5af9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/meson.build
A target/mips/msa_translate.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Extract MSA translation routines
Extract 2200 lines from the huge translate.c to a new file,
'msa_translate.c'. As there are too many inter-dependencies
we don't compile it as another object yet, but keep including
it in the big translate.o. We gain in code maintainability.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201120210844.2625602-5-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: 878b87b54176d7cea4a74ec544703e408776ed34
https://github.com/qemu/qemu/commit/878b87b54176d7cea4a74ec544703e408776ed34
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/msa_translate.c
Log Message:
-----------
target/mips: Pass TCGCond argument to MSA gen_check_zero_element()
Simplify gen_check_zero_element() by passing the TCGCond
argument along.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-25-f4bug@amsat.org>
Commit: c7a9ef75173f090616328d6870f71e8da2b6bd50
https://github.com/qemu/qemu/commit/c7a9ef75173f090616328d6870f71e8da2b6bd50
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/meson.build
A target/mips/msa32.decode
M target/mips/msa_translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Introduce decode tree bindings for MSA ASE
Introduce the 'msa32' decodetree config for the 32-bit MSA ASE.
We start by decoding:
- the branch instructions,
- all instructions based on the MSA opcode.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-20-f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: 96e5b4c7584d623f6cdcb0083829c19141b2b130
https://github.com/qemu/qemu/commit/96e5b4c7584d623f6cdcb0083829c19141b2b130
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/msa_translate.c
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Use decode_ase_msa() generated from decodetree
Now that we can decode the MSA ASE with decode_ase_msa(),
use it and remove the previous code, now unreachable.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-21-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Commit: a685f7d075a7ec09575cbb836cf07b64ae313e30
https://github.com/qemu/qemu/commit/a685f7d075a7ec09575cbb836cf07b64ae313e30
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/meson.build
M target/mips/translate.c
M target/mips/translate.h
A target/mips/translate_addr_const.c
Log Message:
-----------
target/mips: Extract LSA/DLSA translation generators
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-22-f4bug@amsat.org>
Commit: 5f21f30d8554b415142473fc4b58be42be193c46
https://github.com/qemu/qemu/commit/5f21f30d8554b415142473fc4b58be42be193c46
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/meson.build
M target/mips/msa32.decode
A target/mips/msa64.decode
M target/mips/msa_translate.c
Log Message:
-----------
target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
Add the LSA opcode to the MSA32 decodetree config, add DLSA
to a new config for the MSA64 ASE, and call decode_msa64()
in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-23-f4bug@amsat.org>
Commit: 3f7a927847a41fb6def742d5cb8c3dec55755844
https://github.com/qemu/qemu/commit/3f7a927847a41fb6def742d5cb8c3dec55755844
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/meson.build
A target/mips/mips32r6.decode
A target/mips/mips64r6.decode
A target/mips/rel6_translate.c
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes
LSA and LDSA opcodes are also available with MIPS release 6.
Introduce the decodetree config files and call the decode()
helpers in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-24-f4bug@amsat.org>
Commit: 0e9524af2dd55bee8e10896a8579b29b7746efca
https://github.com/qemu/qemu/commit/0e9524af2dd55bee8e10896a8579b29b7746efca
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Remove now unreachable LSA/DLSA opcodes code
Since we switched to decodetree-generated processing,
we can remove this now unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-6-f4bug@amsat.org>
Commit: aac357ec895bfb97b6edca999d91f49b5de5049a
https://github.com/qemu/qemu/commit/aac357ec895bfb97b6edca999d91f49b5de5049a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/rel6_translate.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 Special2 opcode to decodetree
Special2 opcode have been removed from the Release 6.
Add a single decodetree entry for all the opcode class,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-7-f4bug@amsat.org>
Commit: ddc7ef8dfe2408912832ddaac2a21ede4300ce22
https://github.com/qemu/qemu/commit/ddc7ef8dfe2408912832ddaac2a21ede4300ce22
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 COP1X opcode to decodetree
COP1x opcode has been removed from the Release 6.
Add a single decodetree entry for it, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-8-f4bug@amsat.org>
Commit: 6513ca15d8f4034bbc1b68a2cae4f54858fab61e
https://github.com/qemu/qemu/commit/6513ca15d8f4034bbc1b68a2cae4f54858fab61e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
CACHE/PREF opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-9-f4bug@amsat.org>
Commit: 9a7372e35491fc4c8f0bb20359dda87626bdf831
https://github.com/qemu/qemu/commit/9a7372e35491fc4c8f0bb20359dda87626bdf831
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
LWL/LWR/SWL/SWR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-10-f4bug@amsat.org>
Commit: dd5697b2f90c3c6aa4a97b247aa70635914a6041
https://github.com/qemu/qemu/commit/dd5697b2f90c3c6aa4a97b247aa70635914a6041
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from
the Release 6. Add a single decodetree entry for the opcodes,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-11-f4bug@amsat.org>
Commit: 13a839cf48a9cc5eb274021b74cad81976210c7a
https://github.com/qemu/qemu/commit/13a839cf48a9cc5eb274021b74cad81976210c7a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips64r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
LDL/LDR/SDL/SDR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-12-f4bug@amsat.org>
Commit: 1ff668dde2378fb74a4ce590df8b4c5b2a735833
https://github.com/qemu/qemu/commit/1ff668dde2378fb74a4ce590df8b4c5b2a735833
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips64r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
LLD/SCD opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-13-f4bug@amsat.org>
Commit: 27ea1bc077298ce00cde57050875c48ad1ceab7f
https://github.com/qemu/qemu/commit/27ea1bc077298ce00cde57050875c48ad1ceab7f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips32r6.decode
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert Rel6 LL/SC opcodes to decodetree
LL/SC opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-14-f4bug@amsat.org>
Commit: 6648042afb23ad01866af821b5053351a6196ea3
https://github.com/qemu/qemu/commit/6648042afb23ad01866af821b5053351a6196ea3
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/mips-defs.h
Log Message:
-----------
target/mips: Remove CPU_R5900 definition
Commit 823f2897bdd ("target/mips: Disable R5900 support")
removed the single CPU using the CPU_R5900 definition.
As it is unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-2-f4bug@amsat.org>
Commit: fc63010e9bb9efa95221f2873edb2006a40d4b6c
https://github.com/qemu/qemu/commit/fc63010e9bb9efa95221f2873edb2006a40d4b6c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/mips-defs.h
Log Message:
-----------
target/mips: Remove CPU_NANOMIPS32 definition
nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already
defined as ISA_NANOMIPS32.
Remove this incorrect definition and update the single CPU
implementing it, the I7200.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-3-f4bug@amsat.org>
Commit: eaca85763bcd94ddac3fa11f8cc20e974dc11102
https://github.com/qemu/qemu/commit/eaca85763bcd94ddac3fa11f8cc20e974dc11102
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/mips-defs.h
Log Message:
-----------
target/mips: Remove vendor specific CPU definitions
Vendor specific CPU definitions are not very useful. Use the
ISA definitions instead, which are more helpful when looking
at the various CPU definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-4-f4bug@amsat.org>
Commit: cd669e20516fad3d8154629f67d4b6caede9b381
https://github.com/qemu/qemu/commit/cd669e20516fad3d8154629f67d4b6caede9b381
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-01-14 (Thu, 14 Jan 2021)
Changed paths:
M docs/system/deprecated.rst
M docs/system/removed-features.rst
M hw/mips/fuloong2e.c
Log Message:
-----------
docs/system: Remove deprecated 'fulong2e' machine alias
The 'fulong2e' machine alias has been marked as deprecated since
QEMU v5.1 (commit c3a09ff68dd, the machine is renamed 'fuloong2e').
Time to remove it now.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Reviewed-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20210106184602.3771551-1-f4bug@amsat.org>
Commit: 256af05f52b5f944482341273a77511089d64435
https://github.com/qemu/qemu/commit/256af05f52b5f944482341273a77511089d64435
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-01-15 (Fri, 15 Jan 2021)
Changed paths:
M docs/system/deprecated.rst
M docs/system/removed-features.rst
M hw/mips/boston.c
M hw/mips/fuloong2e.c
M linux-user/mips/cpu_loop.c
M target/mips/addr.c
M target/mips/cp0_helper.c
M target/mips/cp0_timer.c
A target/mips/cpu-defs.c.inc
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/fpu_helper.c
A target/mips/fpu_helper.h
M target/mips/gdbstub.c
R target/mips/helper.c
M target/mips/helper.h
M target/mips/internal.h
M target/mips/kvm.c
M target/mips/machine.c
M target/mips/meson.build
M target/mips/mips-defs.h
A target/mips/mips32r6.decode
A target/mips/mips64r6.decode
A target/mips/msa32.decode
A target/mips/msa64.decode
M target/mips/msa_helper.c
A target/mips/msa_helper.h.inc
A target/mips/msa_translate.c
M target/mips/op_helper.c
A target/mips/rel6_translate.c
A target/mips/tlb_helper.c
M target/mips/translate.c
A target/mips/translate.h
A target/mips/translate_addr_const.c
R target/mips/translate_init.c.inc
Log Message:
-----------
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210114' into
staging
MIPS patches queue
- Simplify CPU/ISA definitions
- Various maintenance code movements in translate.c
- Convert part of the MSA ASE instructions to decodetree
- Convert some instructions removed from Release 6 to decodetree
- Remove deprecated 'fulong2e' machine alias
# gpg: Signature made Thu 14 Jan 2021 16:16:29 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/mips-20210114: (69 commits)
docs/system: Remove deprecated 'fulong2e' machine alias
target/mips: Remove vendor specific CPU definitions
target/mips: Remove CPU_NANOMIPS32 definition
target/mips: Remove CPU_R5900 definition
target/mips: Convert Rel6 LL/SC opcodes to decodetree
target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
target/mips: Convert Rel6 COP1X opcode to decodetree
target/mips: Convert Rel6 Special2 opcode to decodetree
target/mips: Remove now unreachable LSA/DLSA opcodes code
target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes
target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
target/mips: Extract LSA/DLSA translation generators
target/mips: Use decode_ase_msa() generated from decodetree
target/mips: Introduce decode tree bindings for MSA ASE
target/mips: Pass TCGCond argument to MSA gen_check_zero_element()
target/mips: Extract MSA translation routines
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/7c79721606be...256af05f52b5
- [Qemu-commits] [qemu/qemu] 8cd0b4: target/mips: Add CP0 Config0 register definitions ...,
Peter Maydell <=