qemu-commits
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] 6d3ef0: tcg: Use memset for large vector byte


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 6d3ef0: tcg: Use memset for large vector byte replication
Date: Tue, 05 Jan 2021 08:26:37 -0800

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 6d3ef04893bdea3e7aa08be3cce5141902836a31
      
https://github.com/qemu/qemu/commit/6d3ef04893bdea3e7aa08be3cce5141902836a31
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-01-04 (Mon, 04 Jan 2021)

  Changed paths:
    M accel/tcg/tcg-runtime.h
    M include/exec/helper-proto.h
    M tcg/tcg-op-gvec.c

  Log Message:
  -----------
  tcg: Use memset for large vector byte replication

In f47db80cc07, we handled odd-sized tail clearing for
the case of hosts that have vector operations, but did
not handle the case of hosts that do not have vector ops.

This was ok until e2e7168a214b, which changed the encoding
of simd_desc such that the odd sizes are impossible.

Add memset as a tcg helper, and use that for all out-of-line
byte stores to vectors.  This includes, but is not limited to,
the tail clearing operation in question.

Cc: qemu-stable@nongnu.org
Buglink: https://bugs.launchpad.net/bugs/1907817
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d2f3066eb2af5d6867974493833834e2aaa427f7
      
https://github.com/qemu/qemu/commit/d2f3066eb2af5d6867974493833834e2aaa427f7
  Author: Zihao Yu <yuzihao@ict.ac.cn>
  Date:   2021-01-04 (Mon, 04 Jan 2021)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Fix illegal shift instructions

Out-of-range shifts have undefined results, but must not trap.
Mask off immediate shift counts to solve this problem.

This bug can be reproduced by running the following guest instructions:

  xor %ecx,%ecx
  sar %cl,%eax
  cmovne %edi,%eax

After optimization, the tcg opcodes of the sar are

  movi_i32 tmp3,$0xffffffffffffffff  pref=all
  sar_i32 tmp3,eax,tmp3              dead: 2  pref=all
  mov_i32 cc_dst,eax                 sync: 0  dead: 1 pref=0xffc0300
  mov_i32 cc_src,tmp3                sync: 0  dead: 0 1  pref=all
  movi_i32 cc_op,$0x31               sync: 0  dead: 0  pref=all

The sar_i32 opcode is a shift by -1, which unmasked generates

  0x200808d618:  fffa5b9b          illegal

Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>
Message-Id: <20201216081206.9628-1-yuzihao@ict.ac.cn>
[rth: Reworded the patch description.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a66424ba17d661007dc13d78c9e3014ccbaf0efb
      
https://github.com/qemu/qemu/commit/a66424ba17d661007dc13d78c9e3014ccbaf0efb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-01-04 (Mon, 04 Jan 2021)

  Changed paths:
    M include/tcg/tcg-op.h

  Log Message:
  -----------
  tcg: Add tcg_gen_bswap_tl alias

The alias is intended to indicate that the bswap is for the
entire target_long.  This should avoid ifdefs on some targets.

Reviewed-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 52d25464605dc20022ad94aa8bc8e8473e600833
      
https://github.com/qemu/qemu/commit/52d25464605dc20022ad94aa8bc8e8473e600833
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-01-05 (Tue, 05 Jan 2021)

  Changed paths:
    M accel/tcg/tcg-runtime.h
    M include/exec/helper-proto.h
    M include/tcg/tcg-op.h
    M tcg/riscv/tcg-target.c.inc
    M tcg/tcg-op-gvec.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210104' into 
staging

Fix vector clear issue.
Fix riscv host shift issue.
Add tcg_gen_bswap_tl.

# gpg: Signature made Mon 04 Jan 2021 17:16:24 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210104:
  tcg: Add tcg_gen_bswap_tl alias
  tcg/riscv: Fix illegal shift instructions
  tcg: Use memset for large vector byte replication

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/74a0a6fcecb9...52d25464605d



reply via email to

[Prev in Thread] Current Thread [Next in Thread]