[Qemu-commits] [qemu/qemu] 10b437: hw/riscv: sifive

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[Qemu-commits] [qemu/qemu] 10b437: hw/riscv: sifive_u: Add UART1 DT node

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 10b437: hw/riscv: sifive_u: Add UART1 DT node in the gener...
Date:	Fri, 18 Dec 2020 03:35:52 -0800
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 10b43754cf299af85bdb1996594ddd54bc517094
      
https://github.com/qemu/qemu/commit/10b43754cf299af85bdb1996594ddd54bc517094
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Add UART1 DT node in the generated DTB

The sifive_u machine emulates two UARTs but we have only UART0 DT
node in the generated DTB so this patch adds UART1 DT node in the
generated DTB.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201111094725.3768755-1-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: dfc973ecc1e8a2c148c0011be89c012891f72384
      
https://github.com/qemu/qemu/commit/dfc973ecc1e8a2c148c0011be89c012891f72384
  Author: Vitaly Wool <vitaly.wool@konsulko.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/riscv/microchip_pfsoc.c
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/riscv: microchip_pfsoc: add QSPI NOR flash

Add QSPI NOR flash definition for Microchip PolarFire SoC.

Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20201112074950.33283-1-vitaly.wool@konsulko.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b3d2a4296ffdf1870669974ae949fffa2ae638ff
      
https://github.com/qemu/qemu/commit/b3d2a4296ffdf1870669974ae949fffa2ae638ff
  Author: Xinhao Zhang <zhangxinhao1@huawei.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/core/register.c

  Log Message:
  -----------
  hw/core/register.c: Don't use '#' flag of printf format

Fix code style. Don't use '#' flag of printf format ('%#') in
format strings, use '0x' prefix instead

Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
Signed-off-by: Kai Deng <dengkai1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201116140148.2850128-1-zhangxinhao1@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c63ca4ff7f81116c26984973052991ff0bd7caec
      
https://github.com/qemu/qemu/commit/c63ca4ff7f81116c26984973052991ff0bd7caec
  Author: Yifei Jiang <jiangyifei@huawei.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Fix the bug of HLVX/HLV/HSV

We found that the hypervisor virtual-machine load and store instructions,
included HLVX/HLV/HSV, couldn't access guest userspace memory.

In the riscv-privileged spec, HLVX/HLV/HSV is defined as follow:
"As usual when V=1, two-stage address translation is applied, and
the HS-level sstatus.SUM is ignored."

But get_physical_address() doesn't ignore sstatus.SUM, when HLVX/HLV/HSV
accesses guest userspace memory. So this patch fixes it.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201130012810.899-1-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 529577457cbba9e429af629c46204f63e50fa832
      
https://github.com/qemu/qemu/commit/529577457cbba9e429af629c46204f63e50fa832
  Author: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR

The TW and TSR fields should be bits 21 and 22 and not 30/29.
This was found while comparing QEMU behaviour against the sail formal
model (https://github.com/rems-project/sail-riscv/).

Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201130170117.71281-1-Alexander.Richardson@cl.cam.ac.uk
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 54a581c22831098e53552d7e33024dc9f4193d7f
      
https://github.com/qemu/qemu/commit/54a581c22831098e53552d7e33024dc9f4193d7f
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/intc/ibex_plic.c

  Log Message:
  -----------
  intc/ibex_plic: Clear interrupts that occur during claim process

Previously if an interrupt occured during the claim process (after the
interrupt is claimed but before it's completed) it would never be
cleared.
This patch ensures that we also clear the hidden_pending bits as well.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Jackie Ke <jackieke724@hotmail.com>
Message-id: 
4e9786084a86f220689123cc8a7837af8fa071cf.1607100423.git.alistair.francis@wdc.com


  Commit: 617448a46b60c353fae0c645a024b628c1f9f700
      
https://github.com/qemu/qemu/commit/617448a46b60c353fae0c645a024b628c1f9f700
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  hw/riscv: Expand the is 32-bit check to support more CPUs

Currently the riscv_is_32_bit() function only supports the generic rv32
CPUs. Extend the function to support the SiFive and LowRISC CPUs as
well.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 
9a13764115ba78688ba61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com


  Commit: c0a635f3973d974befb954463287786fd988bb64
      
https://github.com/qemu/qemu/commit/c0a635f3973d974befb954463287786fd988bb64
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add a TYPE_RISCV_CPU_BASE CPU

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 
86e5ccd9eae2f5d8c2257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com


  Commit: dc4d4aaee31cd3ac4020d3b15729f0a104ce8862
      
https://github.com/qemu/qemu/commit/dc4d4aaee31cd3ac4020d3b15729f0a104ce8862
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/riscv/spike.c
    M include/hw/riscv/spike.h

  Log Message:
  -----------
  riscv: spike: Remove target macro conditionals

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 
04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com


  Commit: 09fe17125ec9a2166cf9bef360811dde714b3874
      
https://github.com/qemu/qemu/commit/09fe17125ec9a2166cf9bef360811dde714b3874
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  riscv: virt: Remove target macro conditionals

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 
aed1174c2efd2f050fa5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com


  Commit: 7893677184681d648165caf9e8a25fccc79b4cf3
      
https://github.com/qemu/qemu/commit/7893677184681d648165caf9e8a25fccc79b4cf3
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: boot: Remove compile time XLEN checks

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 
51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com


  Commit: 9d01143063c1ef0e363e0e4d9bf6d9d950d0a737
      
https://github.com/qemu/qemu/commit/9d01143063c1ef0e363e0e4d9bf6d9d950d0a737
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Remove compile time XLEN checks

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 
d7ca1aca672515e6a4aa0d41716238b055f3f25c.1608142916.git.alistair.francis@wdc.com


  Commit: bd62c13ea89b8ae004aa08802144f1f0cada0ddb
      
https://github.com/qemu/qemu/commit/bd62c13ea89b8ae004aa08802144f1f0cada0ddb
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/riscv/spike.c

  Log Message:
  -----------
  hw/riscv: spike: Remove compile time XLEN checks

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 
ac75037dd58061486de421a0fcd9ac8a92014607.1608142916.git.alistair.francis@wdc.com


  Commit: 2206ffa68fc906a8651d10ca5f53081d0eec41e5
      
https://github.com/qemu/qemu/commit/2206ffa68fc906a8651d10ca5f53081d0eec41e5
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Remove compile time XLEN checks

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 
40d6df4dd05302c566e419be3a1fef7799e57c2e.1608142916.git.alistair.francis@wdc.com


  Commit: 5b6c291b8db8effff625db321be232e0c4dcdb6c
      
https://github.com/qemu/qemu/commit/5b6c291b8db8effff625db321be232e0c4dcdb6c
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/helper.h

  Log Message:
  -----------
  target/riscv: fpu_helper: Match function defs in HELPER macros

Update the function definitions generated in helper.h to match the
actual function implementations.

Also remove all compile time XLEN checks when building.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
614c369cb0000d070873a647b8aac7e023cba145.1608142916.git.alistair.francis@wdc.com


  Commit: 51ae0cabc67c418264d5ae28214603aabc88b9b6
      
https://github.com/qemu/qemu/commit/51ae0cabc67c418264d5ae28214603aabc88b9b6
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add a riscv_cpu_is_32bit() helper function

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 
ebd37b237a8cbe457335b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com


  Commit: 114baaca513d866763ef306a65fcbba1b0c0161f
      
https://github.com/qemu/qemu/commit/114baaca513d866763ef306a65fcbba1b0c0161f
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Specify the XLEN for CPUs

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 
c1da66affbb83ec4a2fbeb0194293bd24d65f5dc.1608142916.git.alistair.francis@wdc.com


  Commit: 5c5a47f10ce8a65ab06b56d7912c7d4d58b287b6
      
https://github.com/qemu/qemu/commit/5c5a47f10ce8a65ab06b56d7912c7d4d58b287b6
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: cpu: Remove compile time XLEN checks

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 
a426ead44db5065a0790066d43e91245683509d7.1608142916.git.alistair.francis@wdc.com


  Commit: f08c7ff3dc552d423439284a725f384b85b99062
      
https://github.com/qemu/qemu/commit/f08c7ff3dc552d423439284a725f384b85b99062
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: cpu_helper: Remove compile time XLEN checks

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 
872d2dfcd1c7c3914655d677e911b9432eb8f340.1608142916.git.alistair.francis@wdc.com


  Commit: 8987cdc48120c268568cdf87ba38591809d3efd1
      
https://github.com/qemu/qemu/commit/8987cdc48120c268568cdf87ba38591809d3efd1
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: csr: Remove compile time XLEN checks

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 
7371180970b7db310d3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com


  Commit: 094b072c6819f251e4cba608585f0f5f59259797
      
https://github.com/qemu/qemu/commit/094b072c6819f251e4cba608585f0f5f59259797
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: cpu: Set XLEN independently from target

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 
7eddba45b5d223321c031431849fdd42eceb514b.1608142916.git.alistair.francis@wdc.com


  Commit: 3ed2b8ac2dacc22c088ec5793ecde31db2fa0414
      
https://github.com/qemu/qemu/commit/3ed2b8ac2dacc22c088ec5793ecde31db2fa0414
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: Use the CPU to determine if 32-bit

Instead of using string compares to determine if a RISC-V machine is
using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids
us having to maintain a list of CPU names to compare against.

This commit also fixes the name of the function to match the
riscv_cpu_is_32bit() function.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com


  Commit: d31e970a01e7399b9cd43ec0dc00c857d968987e
      
https://github.com/qemu/qemu/commit/d31e970a01e7399b9cd43ec0dc00c857d968987e
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-12-17 (Thu, 17 Dec 2020)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  riscv/opentitan: Update the OpenTitan memory layout

OpenTitan is currently only avalible on an FPGA platform and the memory
addresses have changed. Update to use the new memory addresses.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com


  Commit: a05f8ecd88f15273d033b6f044b850a8af84a5b8
      
https://github.com/qemu/qemu/commit/a05f8ecd88f15273d033b6f044b850a8af84a5b8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-18 (Fri, 18 Dec 2020)

  Changed paths:
    M hw/core/register.c
    M hw/intc/ibex_plic.c
    M hw/riscv/boot.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h
    M include/hw/riscv/microchip_pfsoc.h
    M include/hw/riscv/opentitan.h
    M include/hw/riscv/spike.h
    M include/hw/riscv/virt.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/fpu_helper.c
    M target/riscv/helper.h

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20201217-1' into staging

A collection of RISC-V improvements:
 - Improve the sifive_u DTB generation
 - Add QSPI NOR flash to Microchip PFSoC
 - Fix a bug in the Hypervisor HLVX/HLV/HSV instructions
 - Fix some mstatus mask defines
 - Ibex PLIC improvements
 - OpenTitan memory layout update
 - Initial steps towards support for 32-bit CPUs on 64-bit builds

# gpg: Signature made Fri 18 Dec 2020 05:59:42 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20201217-1: (23 commits)
  riscv/opentitan: Update the OpenTitan memory layout
  hw/riscv: Use the CPU to determine if 32-bit
  target/riscv: cpu: Set XLEN independently from target
  target/riscv: csr: Remove compile time XLEN checks
  target/riscv: cpu_helper: Remove compile time XLEN checks
  target/riscv: cpu: Remove compile time XLEN checks
  target/riscv: Specify the XLEN for CPUs
  target/riscv: Add a riscv_cpu_is_32bit() helper function
  target/riscv: fpu_helper: Match function defs in HELPER macros
  hw/riscv: sifive_u: Remove compile time XLEN checks
  hw/riscv: spike: Remove compile time XLEN checks
  hw/riscv: virt: Remove compile time XLEN checks
  hw/riscv: boot: Remove compile time XLEN checks
  riscv: virt: Remove target macro conditionals
  riscv: spike: Remove target macro conditionals
  target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
  hw/riscv: Expand the is 32-bit check to support more CPUs
  intc/ibex_plic: Clear interrupts that occur during claim process
  target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
  target/riscv: Fix the bug of HLVX/HLV/HSV
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/75ee62ac606b...a05f8ecd88f1
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