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[Qemu-commits] [qemu/qemu] 3ddd90: gdbstub: Correct misparsing of vCont

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 3ddd90: gdbstub: Correct misparsing of vCont C/S requests
Date: Tue, 15 Dec 2020 09:18:46 -0800 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 3ddd9036389f5f577e09e1d2f54f8c384660b5ef
      
https://github.com/qemu/qemu/commit/3ddd9036389f5f577e09e1d2f54f8c384660b5ef
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: Correct misparsing of vCont C/S requests

In the vCont packet, two of the command actions (C and S) take an
argument specifying the signal to be sent to the process/thread, which is
sent as an ASCII string of two hex digits which immediately follow the
'C' or 'S' character.

Our code for parsing this packet accidentally skipped the first of the
two bytes of the signal value, because it started parsing the hex string
at 'p + 1' when the preceding code had already moved past the 'C' or
'S' with "cur_action = *p++".

This meant that we would only do the right thing for signals below
10, and would misinterpret the rest.  For instance, when the debugger
wants to send the process a SIGPROF (27 on x86-64) we mangle this into
a SIGSEGV (11).

Remove the accidental double increment.

Fixes: https://bugs.launchpad.net/qemu/+bug/1773743
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20201121210342.10089-1-peter.maydell@linaro.org


  Commit: 1eeffbeb1114441cb1822ce0af952a283e008f31
      
https://github.com/qemu/qemu/commit/1eeffbeb1114441cb1822ce0af952a283e008f31
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/openrisc/Kconfig
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple 
CPUs

openrisc_sim_net_init() attempts to connect the IRQ line from the
ethernet device to both CPUs in an SMP configuration by simply caling
sysbus_connect_irq() for it twice.  This doesn't work, because the
second connection simply overrides the first.

Fix this by creating a TYPE_SPLIT_IRQ to split the IRQ in the SMP
case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stafford Horne <shorne@gmail.com>
Message-id: 20201127225127.14770-2-peter.maydell@linaro.org


  Commit: eaca43a0f7a3548a527e74b7d14d69eeb31dc339
      
https://github.com/qemu/qemu/commit/eaca43a0f7a3548a527e74b7d14d69eeb31dc339
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y"

We're about to refactor the OpenRISC pic_cpu code in a way that means
that just grabbing the whole qemu_irq[] array of inbound IRQs for a
CPU won't be possible any more.  Abstract out a function for "return
the qemu_irq for IRQ x input of CPU y" so we can more easily replace
the implementation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stafford Horne <shorne@gmail.com>
Message-id: 20201127225127.14770-3-peter.maydell@linaro.org


  Commit: 71b3254dd227f4c5e0a1a4005175a98e0a2cdc19
      
https://github.com/qemu/qemu/commit/71b3254dd227f4c5e0a1a4005175a98e0a2cdc19
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/openrisc/meson.build
    M hw/openrisc/openrisc_sim.c
    R hw/openrisc/pic_cpu.c
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h

  Log Message:
  -----------
  target/openrisc: Move pic_cpu code into CPU object proper

The openrisc code uses an old style of interrupt handling, where a
separate standalone set of qemu_irqs invoke a function
openrisc_pic_cpu_handler() which signals the interrupt to the CPU
proper by directly calling cpu_interrupt() and cpu_reset_interrupt().
Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they
can have GPIO input lines themselves, and the neater modern way to
implement this is to simply have the CPU object itself provide the
input IRQ lines.

Create GPIO inputs to the OpenRISC CPU object, and make the only user
of cpu_openrisc_pic_init() wire up directly to those instead.

This allows us to delete the hw/openrisc/pic_cpu.c file entirely.

This fixes a trivial memory leak reported by Coverity of the IRQs
allocated in cpu_openrisc_pic_init().

Fixes: Coverity CID 1421934
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stafford Horne <shorne@gmail.com>
Message-id: 20201127225127.14770-4-peter.maydell@linaro.org


  Commit: cd2528de2cd07d790949c1b5532ae2ab11255e1b
      
https://github.com/qemu/qemu/commit/cd2528de2cd07d790949c1b5532ae2ab11255e1b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M MAINTAINERS
    M hw/intc/meson.build
    R hw/intc/nios2_iic.c
    M hw/nios2/10m50_devboard.c
    M hw/nios2/cpu_pic.c
    M target/nios2/cpu.c
    M target/nios2/cpu.h

  Log Message:
  -----------
  target/nios2: Move IIC code into CPU object proper

The Nios2 architecture supports two different interrupt controller
options:

 * The IIC (Internal Interrupt Controller) is part of the CPU itself;
   it has 32 IRQ input lines and no NMI support.  Interrupt status is
   queried and controlled via the CPU's ipending and istatus
   registers.

 * The EIC (External Interrupt Controller) interface allows the CPU
   to connect to an external interrupt controller.  The interface
   allows the interrupt controller to present a packet of information
   containing:
    - handler address
    - interrupt level
    - register set
    - NMI mode

QEMU does not model an EIC currently.  We do model the IIC, but its
implementation is split across code in hw/nios2/cpu_pic.c and
hw/intc/nios2_iic.c.  The code in those two files has no state of its
own -- the IIC state is in the Nios2CPU state struct.

Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they
can have GPIO input lines themselves, so we can implement the IIC
directly in the CPU object the same way that real hardware does.

Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the
only user of the IIC wire up directly to those instead.

Note that the old code had an "NMI" concept which was entirely unused
and also as far as I can see not architecturally correct, since only
the EIC has a concept of an NMI.

This fixes a Coverity-reported trivial memory leak of the IRQ array
allocated in nios2_cpu_pic_init().

Fixes: Coverity CID 1421916
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201129174022.26530-2-peter.maydell@linaro.org
Reviewed-by: Wentong Wu <wentong.wu@intel.com>
Tested-by: Wentong Wu <wentong.wu@intel.com>


  Commit: 2c87548ef46040d0577cc362cab94561c1d98b8d
      
https://github.com/qemu/qemu/commit/2c87548ef46040d0577cc362cab94561c1d98b8d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    R hw/nios2/cpu_pic.c
    M hw/nios2/meson.build
    M target/nios2/cpu.h
    M target/nios2/op_helper.c

  Log Message:
  -----------
  target/nios2: Move nios2_check_interrupts() into target/nios2

The function nios2_check_interrupts)() looks only at CPU-internal
state; it belongs in target/nios2, not hw/nios2.  Move it into the
same file as its only caller, so it can just be local to that file.

This removes the only remaining code from cpu_pic.c, so we can delete
that file entirely.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201129174022.26530-3-peter.maydell@linaro.org
Reviewed-by: Wentong Wu <wentong.wu@intel.com>
Tested-by: Wentong Wu <wentong.wu@intel.com>


  Commit: 05bcbcf27954e664d85627f026970f62556fefa5
      
https://github.com/qemu/qemu/commit/05bcbcf27954e664d85627f026970f62556fefa5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M target/nios2/cpu.c

  Log Message:
  -----------
  target/nios2: Use deposit32() to update ipending register

In nios2_cpu_set_irq(), use deposit32() rather than raw shift-and-mask
operations to set the appropriate bit in the ipending register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201129174022.26530-4-peter.maydell@linaro.org


  Commit: 5b1de5204776284283019e18a3a45310c6e83be6
      
https://github.com/qemu/qemu/commit/5b1de5204776284283019e18a3a45310c6e83be6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/core/loader.c

  Log Message:
  -----------
  hw/core/loader.c: Track last-seen ROM in rom_check_and_register_reset()

In rom_check_and_register_reset() we detect overlaps by looking at
whether the ROM blob we're currently examining is in the same address
space and starts before the previous ROM blob ends.  (This works
because the ROM list is kept sorted in order by AddressSpace and then
by address.)

Instead of keeping the AddressSpace and last address of the previous ROM
blob in local variables, just keep a pointer to it.

This will allow us to print more useful information when we do detect
an overlap.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201129203923.10622-2-peter.maydell@linaro.org


  Commit: 837a0595160d7184298d7935398aa4234e6a400d
      
https://github.com/qemu/qemu/commit/837a0595160d7184298d7935398aa4234e6a400d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/core/loader.c
    M softmmu/vl.c

  Log Message:
  -----------
  hw/core/loader.c: Improve reporting of ROM overlap errors

In rom_check_and_register_reset() we report to the user if there is
a "ROM region overlap". This has a couple of problems:
 * the reported information is not very easy to intepret
 * the function just prints the overlap to stderr (and relies on
   its single callsite in vl.c to do an error_report() and exit)
 * only the first overlap encountered is diagnosed

Make this function use error_report() and error_printf() and
report a more user-friendly report with all the overlaps
diagnosed.

Sample old output:

rom: requested regions overlap (rom dtb. free=0x0000000000008000, 
addr=0x0000000000000000)
qemu-system-aarch64: rom check and register reset failed

Sample new output:

qemu-system-aarch64: Some ROM regions are overlapping
These ROM regions might have been loaded by direct user request or by default.
They could be BIOS/firmware images, a guest kernel, initrd or some other file 
loaded into guest memory.
Check whether you intended to load all this guest code, and whether it has been 
built to load to the correct addresses.

The following two regions overlap (in the cpu-memory-0 address space):
  phdr #0: /home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf (addresses 
0x0000000000000000 - 0x0000000000008000)
  dtb (addresses 0x0000000000000000 - 0x0000000000100000)

The following two regions overlap (in the cpu-memory-0 address space):
  phdr #1: /home/petmay01/linaro/qemu-misc-tests/bad-psci-call.axf (addresses 
0x0000000040000000 - 0x0000000040000010)
  phdr #0: /home/petmay01/linaro/qemu-misc-tests/bp-test.elf (addresses 
0x0000000040000000 - 0x0000000040000020)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201129203923.10622-3-peter.maydell@linaro.org


  Commit: 926c9063dc7929674f670b43eb6979e3f9677d91
      
https://github.com/qemu/qemu/commit/926c9063dc7929674f670b43eb6979e3f9677d91
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M include/hw/elf_ops.h

  Log Message:
  -----------
  elf_ops.h: Don't truncate name of the ROM blobs we create

Currently the load_elf code assembles the ROM blob name into a
local 128 byte fixed-size array. Use g_strdup_printf() instead so
that we don't truncate the pathname if it happens to be long.
(This matters mostly for monitor 'info roms' output and for the
error messages if ROM blobs overlap.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201129203923.10622-4-peter.maydell@linaro.org


  Commit: 311ca11e3879ba3743cc8ea8e42c12401c5098a9
      
https://github.com/qemu/qemu/commit/311ca11e3879ba3743cc8ea8e42c12401c5098a9
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M include/hw/elf_ops.h

  Log Message:
  -----------
  elf_ops.h: Be more verbose with ROM blob names

Instead of making the ROM blob name something like:
  phdr #0: /home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf
make it a little more self-explanatory for people who don't know
ELF format details:
  /home/petmay01/linaro/qemu-misc-tests/ldmia-fault.axf ELF program header 
segment 0

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201129203923.10622-5-peter.maydell@linaro.org


  Commit: 50e76a73de1f7fb40fd84df3d5a98067c10cc097
      
https://github.com/qemu/qemu/commit/50e76a73de1f7fb40fd84df3d5a98067c10cc097
  Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/usb/meson.build
    A hw/usb/xlnx-versal-usb2-ctrl-regs.c
    A include/hw/usb/xlnx-versal-usb2-ctrl-regs.h

  Log Message:
  -----------
  usb: Add versal-usb2-ctrl-regs module

This module emulates control registers of versal usb2 controller, this is added
just to make guest happy. In general this module would control the phy-reset
signal from usb controller, data coherency of the transactions, signals
the host system errors received from controller.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1607023357-5096-2-git-send-email-sai.pavan.boddu@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8bbe61f3c10446603514aeee0aafebaaa00e8d07
      
https://github.com/qemu/qemu/commit/8bbe61f3c10446603514aeee0aafebaaa00e8d07
  Author: Vikram Garhwal <fnu.vikram@xilinx.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/usb/Kconfig
    A hw/usb/hcd-dwc3.c
    M hw/usb/meson.build
    A include/hw/usb/hcd-dwc3.h

  Log Message:
  -----------
  usb: Add DWC3 model

This patch adds skeleton model of dwc3 usb controller attached to
xhci-sysbus device. It defines global register space of DWC3 controller,
global registers control the AXI/AHB interfaces properties, external FIFO
support and event count support. All of which are unimplemented at
present,we are only supporting core reset and read of ID register.

Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1607023357-5096-3-git-send-email-sai.pavan.boddu@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e29c7db19d2cb71df1c02ba523d0c882009a78ec
      
https://github.com/qemu/qemu/commit/e29c7db19d2cb71df1c02ba523d0c882009a78ec
  Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/usb/Kconfig
    M hw/usb/meson.build
    A hw/usb/xlnx-usb-subsystem.c
    A include/hw/usb/xlnx-usb-subsystem.h

  Log Message:
  -----------
  usb: xlnx-usb-subsystem: Add xilinx usb subsystem

This model is a top level integration wrapper for hcd-dwc3 and
versal-usb2-ctrl-regs modules, this is used by xilinx versal soc's and
future xilinx usb subsystems would also be part of it.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1607023357-5096-4-git-send-email-sai.pavan.boddu@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 144677d41bf513af64e934fba61bf3220cbe8d5a
      
https://github.com/qemu/qemu/commit/144677d41bf513af64e934fba61bf3220cbe8d5a
  Author: Vikram Garhwal <fnu.vikram@xilinx.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  arm: xlnx-versal: Connect usb to virt-versal

Connect VersalUsb2 subsystem to xlnx-versal SOC, its placed
in iou of lpd domain and configure it as dual port host controller.
Add the respective guest dts nodes for "xlnx-versal-virt" machine.

Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1607023357-5096-5-git-send-email-sai.pavan.boddu@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 98a8cc741dad9cb4738f81a994bcf8d77d619152
      
https://github.com/qemu/qemu/commit/98a8cc741dad9cb4738f81a994bcf8d77d619152
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/misc/zynq_slcr.c

  Log Message:
  -----------
  hw/misc/zynq_slcr: Avoid #DIV/0! error

Malicious user can set the feedback divisor for the PLLs
to zero, triggering a floating-point exception (SIGFPE).

As the datasheet [*] is not clear how hardware behaves
when these bits are zeroes, use the maximum divisor
possible (128) to avoid the software FPE.

[*] Zynq-7000 TRM, UG585 (v1.12.2)
    B.28 System Level Control Registers (slcr)
    -> "Register (slcr) ARM_PLL_CTRL"
    25.10.4 PLLs
    -> "Software-Controlled PLL Update"

Fixes: 38867cb7ec9 ("hw/misc/zynq_slcr: add clock generation for uarts")
Reported-by: Gaoning Pan <pgn@zju.edu.cn>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Message-id: 20201210141610.884600-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 09414144cd3860243aab7e0d20d67c5bd91c1986
      
https://github.com/qemu/qemu/commit/09414144cd3860243aab7e0d20d67c5bd91c1986
  Author: Joe Komlodi <joe.komlodi@xilinx.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  hw/block/m25p80: Make Numonyx config field names more accurate

The previous naming of the configuration registers made it sound like that if
the bits were set the settings would be enabled, while the opposite is true.

Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Message-id: 1605568264-26376-2-git-send-email-komlodi@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fc5df349dab3b703b5810a7eea029da13babc756
      
https://github.com/qemu/qemu/commit/fc5df349dab3b703b5810a7eea029da13babc756
  Author: Joe Komlodi <joe.komlodi@xilinx.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  hw/block/m25p80: Fix when VCFG XIP bit is set for Numonyx

VCFG XIP is set (disabled) when the NVCFG XIP bits are all set (disabled).

Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Message-id: 1605568264-26376-3-git-send-email-komlodi@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 23486231170bfdc336646e1e6c6440143003be68
      
https://github.com/qemu/qemu/commit/23486231170bfdc336646e1e6c6440143003be68
  Author: Joe Komlodi <joe.komlodi@xilinx.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  hw/block/m25p80: Check SPI mode before running some Numonyx commands

Some Numonyx flash commands cannot be executed in DIO and QIO mode, such as
trying to do DPP or DOR when in QIO mode.

Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Message-id: 1605568264-26376-4-git-send-email-komlodi@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 23af268566069183285bebbdf95b1b37cb7c0942
      
https://github.com/qemu/qemu/commit/23af268566069183285bebbdf95b1b37cb7c0942
  Author: Joe Komlodi <joe.komlodi@xilinx.com>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  hw/block/m25p80: Fix Numonyx fast read dummy cycle count

Numonyx chips determine the number of cycles to wait based on bits 7:4
in the volatile configuration register.

However, if these bits are 0x0 or 0xF, the number of dummy cycles to
wait is 10 for QIOR and QIOR4 commands or when in QIO mode, and otherwise 8 for
the currently supported fast read commands. [1]

[1]
https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf?rev=9b167fbf2b3645efba6385949a72e453

Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Message-id: 1605568264-26376-5-git-send-email-komlodi@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 657ee88ef3ec55c3a6164da88c11a6640ca7507c
      
https://github.com/qemu/qemu/commit/657ee88ef3ec55c3a6164da88c11a6640ca7507c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-15 (Tue, 15 Dec 2020)

  Changed paths:
    M MAINTAINERS
    M gdbstub.c
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M hw/block/m25p80.c
    M hw/core/loader.c
    M hw/intc/meson.build
    R hw/intc/nios2_iic.c
    M hw/misc/zynq_slcr.c
    M hw/nios2/10m50_devboard.c
    R hw/nios2/cpu_pic.c
    M hw/nios2/meson.build
    M hw/openrisc/Kconfig
    M hw/openrisc/meson.build
    M hw/openrisc/openrisc_sim.c
    R hw/openrisc/pic_cpu.c
    M hw/usb/Kconfig
    A hw/usb/hcd-dwc3.c
    M hw/usb/meson.build
    A hw/usb/xlnx-usb-subsystem.c
    A hw/usb/xlnx-versal-usb2-ctrl-regs.c
    M include/hw/arm/xlnx-versal.h
    M include/hw/elf_ops.h
    A include/hw/usb/hcd-dwc3.h
    A include/hw/usb/xlnx-usb-subsystem.h
    A include/hw/usb/xlnx-versal-usb2-ctrl-regs.h
    M softmmu/vl.c
    M target/nios2/cpu.c
    M target/nios2/cpu.h
    M target/nios2/op_helper.c
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201215' 
into staging

target-arm queue:
 * gdbstub: Correct misparsing of vCont C/S requests
 * openrisc: Move pic_cpu code into CPU object proper
 * nios2: Move IIC code into CPU object proper
 * Improve reporting of ROM overlap errors
 * xlnx-versal: Add USB support
 * hw/misc/zynq_slcr: Avoid #DIV/0! error
 * Numonyx: Fix dummy cycles and check for SPI mode on cmds

# gpg: Signature made Tue 15 Dec 2020 13:59:46 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20201215:
  hw/block/m25p80: Fix Numonyx fast read dummy cycle count
  hw/block/m25p80: Check SPI mode before running some Numonyx commands
  hw/block/m25p80: Fix when VCFG XIP bit is set for Numonyx
  hw/block/m25p80: Make Numonyx config field names more accurate
  hw/misc/zynq_slcr: Avoid #DIV/0! error
  arm: xlnx-versal: Connect usb to virt-versal
  usb: xlnx-usb-subsystem: Add xilinx usb subsystem
  usb: Add DWC3 model
  usb: Add versal-usb2-ctrl-regs module
  elf_ops.h: Be more verbose with ROM blob names
  elf_ops.h: Don't truncate name of the ROM blobs we create
  hw/core/loader.c: Improve reporting of ROM overlap errors
  hw/core/loader.c: Track last-seen ROM in rom_check_and_register_reset()
  target/nios2: Use deposit32() to update ipending register
  target/nios2: Move nios2_check_interrupts() into target/nios2
  target/nios2: Move IIC code into CPU object proper
  target/openrisc: Move pic_cpu code into CPU object proper
  hw/openrisc/openrisc_sim: Abstract out "get IRQ x of CPU y"
  hw/openrisc/openrisc_sim: Use IRQ splitter when connecting IRQ to multiple 
CPUs
  gdbstub: Correct misparsing of vCont C/S requests

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/69e92bd558d7...657ee88ef3ec
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