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[Qemu-commits] [qemu/qemu] dab1e1: MAINTAINERS: address@hidden -> chenhu
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] dab1e1: MAINTAINERS: address@hidden -> chenhuacai@kerne... |
Date: |
Mon, 14 Dec 2020 11:20:07 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: dab1e1e15b559c11b980a6b921027dd4939107e9
https://github.com/qemu/qemu/commit/dab1e1e15b559c11b980a6b921027dd4939107e9
Author: Huacai Chen <zltjiangshi@gmail.com>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M .mailmap
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: chenhc@lemote.com -> chenhuacai@kernel.org
Use @kernel.org address as the main communications end point. Update the
corresponding M-entries and .mailmap (for git shortlog translation).
Signed-off-by: Huacai Chen <chenhuacai@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1607160121-9977-1-git-send-email-chenhuacai@kernel.org>
Commit: 11cb076b26ff25a909f07c593f9a4e0416ac147f
https://github.com/qemu/qemu/commit/11cb076b26ff25a909f07c593f9a4e0416ac147f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/kvm.c
Log Message:
-----------
target/mips/kvm: Assert unreachable code is not used
This code must not be used outside of KVM. Abort if it is.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200429082916.10669-3-f4bug@amsat.org>
Commit: 86deb70172b5aecac65229c88b1a2090179a027c
https://github.com/qemu/qemu/commit/86deb70172b5aecac65229c88b1a2090179a027c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/kvm.c
Log Message:
-----------
target/mips/kvm: Remove unused headers
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-7-f4bug@amsat.org>
Commit: 34cffe960e494ae6dc79efeb87fc3e79fe7de90c
https://github.com/qemu/qemu/commit/34cffe960e494ae6dc79efeb87fc3e79fe7de90c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/internal.h
M target/mips/kvm.c
Log Message:
-----------
target/mips: Include "exec/memattrs.h" in 'internal.h'
mips_cpu_do_transaction_failed() requires MemTxAttrs
and MemTxResult declarations.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-8-f4bug@amsat.org>
Commit: 547b9b17f9cbe7bc16db73f4aaceeead54c03f29
https://github.com/qemu/qemu/commit/547b9b17f9cbe7bc16db73f4aaceeead54c03f29
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/cp0_helper.c
M target/mips/helper.c
Log Message:
-----------
target/mips: Replace magic values by CP0PM_MASK or TARGET_PAGE_BITS_MIN
Replace magic values related to page size:
12 -> TARGET_PAGE_BITS_MIN
13 -> CP0PM_MASK
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <20201109090422.2445166-2-f4bug@amsat.org>
Commit: 55671f80cbb011343cf5786186daed600fcfab4f
https://github.com/qemu/qemu/commit/55671f80cbb011343cf5786186daed600fcfab4f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/cp0_helper.c
M target/mips/meson.build
Log Message:
-----------
target/mips: Do not include CP0 helpers in user-mode emulation
CP0 helpers are restricted to system-mode emulation.
Do not intent do build cp0_helper.c in user-mode (this
allows to simplify some #ifdef'ry).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <20201109090422.2445166-3-f4bug@amsat.org>
Commit: 5777c8a905d5aa35d5308a6785c9d9b60cd498cc
https://github.com/qemu/qemu/commit/5777c8a905d5aa35d5308a6785c9d9b60cd498cc
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/cp0_helper.c
Log Message:
-----------
target/mips: Remove unused headers from cp0_helper.c
Remove unused headers and add missing "qemu/log.h" since
qemu_log() is called.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-5-f4bug@amsat.org>
Commit: 90c429ee765ec6ca2e2384edc9e45b4ddfae9adb
https://github.com/qemu/qemu/commit/90c429ee765ec6ca2e2384edc9e45b4ddfae9adb
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/helper.c
Log Message:
-----------
target/mips: Also display exception names in user-mode
Currently MIPS exceptions are displayed as string in system-mode
emulation, but as number in user-mode.
Unify by extracting the current system-mode code as excp_name()
and use that in user-mode.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201119160536.1980329-1-f4bug@amsat.org>
Commit: 7d6f01a12be534ce2ffaf0aa8741e5f5efca2362
https://github.com/qemu/qemu/commit/7d6f01a12be534ce2ffaf0aa8741e5f5efca2362
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Allow executing MSA instructions on Loongson-3A4000
The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html
Commit af868995e1b correctly set the 'MSA present' bit of Config3
register, but forgot to allow the MSA instructions decoding in
insn_flags, so executing them triggers a 'Reserved Instruction'.
Fix by adding the ASE_MSA mask to insn_flags.
Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <20201130102228.2395100-1-f4bug@amsat.org>
Commit: 1ab3a0de2f40f70bdfbd1a319a9734089bddcf72
https://github.com/qemu/qemu/commit/1ab3a0de2f40f70bdfbd1a319a9734089bddcf72
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/internal.h
Log Message:
-----------
target/mips: Explicit Release 6 MMU types
As of Release 6, MMU type 4 is assigned to "Dual Variable-Page-Size
and Fixed-Page-Size TLBs" and type 2 to "Block Address Translation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201201132817.2863301-4-f4bug@amsat.org>
Commit: ac70f9767cba3a5966f7eefc102fcda8b3c7d09e
https://github.com/qemu/qemu/commit/ac70f9767cba3a5966f7eefc102fcda8b3c7d09e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M hw/mips/boston.c
M hw/mips/malta.c
M target/mips/cpu.h
M target/mips/translate.c
Log Message:
-----------
target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()
As cpu_supports_isa() / cpu_supports_cps_smp() take a 'cpu_type'
name argument, rename them cpu_type_supports_FEAT().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207215257.4004222-2-f4bug@amsat.org>
Commit: df6adb68c1b1808f164c9ed8a04fe14d9c04e82c
https://github.com/qemu/qemu/commit/df6adb68c1b1808f164c9ed8a04fe14d9c04e82c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/cpu.c
M target/mips/cpu.h
Log Message:
-----------
target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument
Introduce cpu_supports_isa() which takes a CPUMIPSState
argument, more useful at runtime when the CPU is created
(no need to call the extensive object_class_by_name()).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207215257.4004222-3-f4bug@amsat.org>
Commit: 2fd9c5ad4449c862932b21e8f6b4573cc50b9ae8
https://github.com/qemu/qemu/commit/2fd9c5ad4449c862932b21e8f6b4573cc50b9ae8
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
R hw/mips/addr.c
M hw/mips/boston.c
M hw/mips/meson.build
M include/hw/mips/cpudevs.h
A target/mips/addr.c
M target/mips/cpu.h
M target/mips/meson.build
M target/mips/translate.c
Log Message:
-----------
hw/mips: Move address translation helpers to target/mips/
Address translation is an architectural thing (not hardware
related). Move the helpers from hw/ to target/.
As physical address and KVM are specific to system mode
emulation, restrict this file to softmmu, so it doesn't
get compiled for user-mode emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-2-f4bug@amsat.org>
Commit: 1379307db20ab2e865d3ec148669c95cfe49b666
https://github.com/qemu/qemu/commit/1379307db20ab2e865d3ec148669c95cfe49b666
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Remove unused headers from translate.c
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-3-f4bug@amsat.org>
Commit: 5f3013654e879bb4b22876617fdb235aa22568d3
https://github.com/qemu/qemu/commit/5f3013654e879bb4b22876617fdb235aa22568d3
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/op_helper.c
Log Message:
-----------
target/mips: Remove unused headers from op_helper.c
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-6-f4bug@amsat.org>
Commit: 585c80ad7bb1bfd62721d03b62424fb1a786f659
https://github.com/qemu/qemu/commit/585c80ad7bb1bfd62721d03b62424fb1a786f659
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/translate.c
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Remove mips_def_t unused argument from mvp_init()
mvp_init() doesn't require any CPU definition (beside the
information accessible via CPUMIPSState). Remove the unused
argument.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-2-f4bug@amsat.org>
Commit: 17c2c320f3c216f80c2fad1f0fa9358c2ffbd0d3
https://github.com/qemu/qemu/commit/17c2c320f3c216f80c2fad1f0fa9358c2ffbd0d3
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M hw/mips/cps.c
M target/mips/cp0_helper.c
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/helper.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Introduce ase_mt_available() helper
Instead of accessing CP0_Config3 directly and checking
the 'Multi-Threading Present' bit, introduce an helper
to simplify code review.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-3-f4bug@amsat.org>
Commit: ecc268e7c2488c0285684fad6d04cac6a794991d
https://github.com/qemu/qemu/commit/ecc268e7c2488c0285684fad6d04cac6a794991d
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Do not initialize MT registers if MT ASE absent
Do not initialize MT-related config registers if the MT ASE
is not present. As some functions access the 'mvp' structure,
we still zero-allocate it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-4-f4bug@amsat.org>
Commit: 8de0f2804676decfa82ce51ef18293523e67af32
https://github.com/qemu/qemu/commit/8de0f2804676decfa82ce51ef18293523e67af32
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Do not initialize MT registers if MT ASE absent
Do not initialize MT-related config register if the MT ASE
is not present.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-5-f4bug@amsat.org>
Commit: 07741e67542d061b45628a5de60637b006ca2de5
https://github.com/qemu/qemu/commit/07741e67542d061b45628a5de60637b006ca2de5
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit()
PTC field has 8 bits, PVPE has 4. We plan to use the
"hw/registerfields.h" API with MIPS CPU definitions
(target/mips/cpu.h). Meanwhile we use magic 8 and 4.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-6-f4bug@amsat.org>
Commit: ffa657ee70ced89168e432ace4b4b8af5a227117
https://github.com/qemu/qemu/commit/ffa657ee70ced89168e432ace4b4b8af5a227117
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/cpu.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Extract cpu_supports*/cpu_set* translate.c
Move cpu_supports*() and cpu_set_exception_base() from
translate.c to cpu.c.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-9-f4bug@amsat.org>
Commit: a10b453a52a1f5c9511a0eed164d5e89c88033e1
https://github.com/qemu/qemu/commit/a10b453a52a1f5c9511a0eed164d5e89c88033e1
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/cpu.c
M target/mips/helper.c
Log Message:
-----------
target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-10-f4bug@amsat.org>
Commit: c20cf02bbd88146ffc75c7722423b1ef6991676c
https://github.com/qemu/qemu/commit/c20cf02bbd88146ffc75c7722423b1ef6991676c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/cpu.c
M target/mips/internal.h
M target/mips/translate.c
Log Message:
-----------
target/mips: Move cpu definitions, reset() and realize() to cpu.c
Nothing TCG specific there, move to common cpu code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-16-f4bug@amsat.org>
Commit: 7b884bf51e7feb6aee2a6293aee0c40a07bf8080
https://github.com/qemu/qemu/commit/7b884bf51e7feb6aee2a6293aee0c40a07bf8080
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/cpu.c
Log Message:
-----------
target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn()
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-17-f4bug@amsat.org>
Commit: 98cf80baa75fb8d3d6516e39895247c07a6f83ff
https://github.com/qemu/qemu/commit/98cf80baa75fb8d3d6516e39895247c07a6f83ff
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/fpu_helper.c
Log Message:
-----------
target/mips: Remove unused headers from fpu_helper.c
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-4-f4bug@amsat.org>
Commit: 3533ee301c46620fd5699cb97f2d4bd194fe0c24
https://github.com/qemu/qemu/commit/3533ee301c46620fd5699cb97f2d4bd194fe0c24
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-12-13 (Sun, 13 Dec 2020)
Changed paths:
M target/mips/fpu_helper.c
M target/mips/internal.h
Log Message:
-----------
target/mips: Use FloatRoundMode enum for FCR31 modes conversion
Use the FloatRoundMode enum type introduced in commit 3dede407cc6
("softfloat: Name rounding mode enum") instead of 'unsigned int'.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201123204448.3260804-2-f4bug@amsat.org>
Commit: aa14de086675280206dbc1849da6f85b75f62f1b
https://github.com/qemu/qemu/commit/aa14de086675280206dbc1849da6f85b75f62f1b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-12-14 (Mon, 14 Dec 2020)
Changed paths:
M .mailmap
M MAINTAINERS
R hw/mips/addr.c
M hw/mips/boston.c
M hw/mips/cps.c
M hw/mips/malta.c
M hw/mips/meson.build
M include/hw/mips/cpudevs.h
A target/mips/addr.c
M target/mips/cp0_helper.c
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/fpu_helper.c
M target/mips/helper.c
M target/mips/internal.h
M target/mips/kvm.c
M target/mips/meson.build
M target/mips/op_helper.c
M target/mips/translate.c
M target/mips/translate_init.c.inc
Log Message:
-----------
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20201213' into
staging
MIPS patches queue
. Allow executing MSA instructions on Loongson-3A4000
. Update Huacai Chen email address
. Various cleanups:
- unused headers removal
- use definitions instead of magic values
- remove dead code
- avoid calling unused code
. Various code movements
CI jobs results:
https://gitlab.com/philmd/qemu/-/pipelines/229120169
https://cirrus-ci.com/build/4857731557359616
# gpg: Signature made Sun 13 Dec 2020 20:18:52 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/mips-20201213: (26 commits)
target/mips: Use FloatRoundMode enum for FCR31 modes conversion
target/mips: Remove unused headers from fpu_helper.c
target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn()
target/mips: Move cpu definitions, reset() and realize() to cpu.c
target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c
target/mips: Extract cpu_supports*/cpu_set* translate.c
hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit()
hw/mips/malta: Do not initialize MT registers if MT ASE absent
target/mips: Do not initialize MT registers if MT ASE absent
target/mips: Introduce ase_mt_available() helper
target/mips: Remove mips_def_t unused argument from mvp_init()
target/mips: Remove unused headers from op_helper.c
target/mips: Remove unused headers from translate.c
hw/mips: Move address translation helpers to target/mips/
target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument
target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()
target/mips: Explicit Release 6 MMU types
target/mips: Allow executing MSA instructions on Loongson-3A4000
target/mips: Also display exception names in user-mode
target/mips: Remove unused headers from cp0_helper.c
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/37f04b71a9cd...aa14de086675
- [Qemu-commits] [qemu/qemu] dab1e1: MAINTAINERS: address@hidden -> chenhuacai@kerne...,
Peter Maydell <=