[Qemu-commits] [qemu/qemu] d9aad8: hw/arm/smmuv3: Fix up L1STD

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[Qemu-commits] [qemu/qemu] d9aad8: hw/arm/smmuv3: Fix up L1STD_SPAN deco

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] d9aad8: hw/arm/smmuv3: Fix up L1STD_SPAN decoding
Date:	Thu, 10 Dec 2020 04:07:51 -0800
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: d9aad887e80c8002a866326d2ec7c3bf2463da87
      
https://github.com/qemu/qemu/commit/d9aad887e80c8002a866326d2ec7c3bf2463da87
  Author: Kunkun Jiang <jiangkunkun@huawei.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/arm/smmuv3-internal.h

  Log Message:
  -----------
  hw/arm/smmuv3: Fix up L1STD_SPAN decoding

Accroding to the SMMUv3 spec, the SPAN field of Level1 Stream Table
Descriptor is 5 bits([4:0]).

Fixes: 9bde7f0674f(hw/arm/smmuv3: Implement translate callback)
Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
Message-id: 20201124023711.1184-1-jiangkunkun@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 98e5d7a2b726947081fe2733ec869f9aa967c890
      
https://github.com/qemu/qemu/commit/98e5d7a2b726947081fe2733ec869f9aa967c890
  Author: Vikram Garhwal <fnu.vikram@xilinx.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/Kconfig
    M hw/net/can/meson.build
    A hw/net/can/trace-events
    A hw/net/can/trace.h
    A hw/net/can/xlnx-zynqmp-can.c
    A include/hw/net/xlnx-zynqmp-can.h
    M meson.build

  Log Message:
  -----------
  hw/net/can: Introduce Xilinx ZynqMP CAN controller

The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.

Example for using single CAN:
    -object can-bus,id=canbus0 \
    -machine xlnx-zcu102.canbus0=canbus0 \
    -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0

Example for connecting both CAN to same virtual CAN on host machine:
    -object can-bus,id=canbus0 -object can-bus,id=canbus1 \
    -machine xlnx-zcu102.canbus0=canbus0 \
    -machine xlnx-zcu102.canbus1=canbus1 \
    -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0 \
    -object can-host-socketcan,id=socketcan1,if=vcan0,canbus=canbus1

To create virtual CAN on the host machine, please check the QEMU CAN docs:
https://github.com/qemu/qemu/blob/master/docs/can.txt

Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Message-id: 1605728926-352690-2-git-send-email-fnu.vikram@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 840c22cd542e6210d65cc6f24944c5870f34e5d8
      
https://github.com/qemu/qemu/commit/840c22cd542e6210d65cc6f24944c5870f34e5d8
  Author: Vikram Garhwal <fnu.vikram@xilinx.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/arm/xlnx-zcu102.c
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers

Connect CAN0 and CAN1 on the ZynqMP.

Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Message-id: 1605728926-352690-3-git-send-email-fnu.vikram@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ab5e842c4ba9cc543ce86729a042fa444e49de61
      
https://github.com/qemu/qemu/commit/ab5e842c4ba9cc543ce86729a042fa444e49de61
  Author: Vikram Garhwal <fnu.vikram@xilinx.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M tests/qtest/meson.build
    A tests/qtest/xlnx-can-test.c

  Log Message:
  -----------
  tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller

The QTests perform five tests on the Xilinx ZynqMP CAN controller:
    Tests the CAN controller in loopback, sleep and snoop mode.
    Tests filtering of incoming CAN messages.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Message-id: 1605728926-352690-4-git-send-email-fnu.vikram@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d36d71121324063c1f0328cd288aec1ee271293d
      
https://github.com/qemu/qemu/commit/d36d71121324063c1f0328cd288aec1ee271293d
  Author: Vikram Garhwal <fnu.vikram@xilinx.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller

Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Message-id: 1605728926-352690-5-git-send-email-fnu.vikram@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ce3adffc3c56b30b54eb712ff92889e87e7f30f0
      
https://github.com/qemu/qemu/commit/ce3adffc3c56b30b54eb712ff92889e87e7f30f0
  Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  sbsa-ref: allow to use Cortex-A53/57/72 cpus

Trusted Firmware now supports A72 on sbsa-ref by default [1] so enable
it for QEMU as well. A53 was already enabled there.

1. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7117

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201120141705.246690-1-marcin.juszkiewicz@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1af979b492e2008578ecf3a7940f4ebd7118af15
      
https://github.com/qemu/qemu/commit/1af979b492e2008578ecf3a7940f4ebd7118af15
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M tests/qtest/npcm7xx_rng-test.c

  Log Message:
  -----------
  tests/qtest/npcm7xx_rng-test: dump random data on failure

Dump the collected random data after a randomness test failure.

Note that this relies on the test having called
g_test_set_nonfatal_assertions() so we don't abort immediately on the
assertion failure.

Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: minor commit message tweak]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 26c69099f762d53731fb3268db990f3e65dc3d1e
      
https://github.com/qemu/qemu/commit/26c69099f762d53731fb3268db990f3e65dc3d1e
  Author: Alex Chen <alex.chen@huawei.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/misc/imx25_ccm.c

  Log Message:
  -----------
  i.MX25: Fix bad printf format specifiers

We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201126111109.112238-2-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a88ae037572f23a54cf865e7a07df2d734288927
      
https://github.com/qemu/qemu/commit/a88ae037572f23a54cf865e7a07df2d734288927
  Author: Alex Chen <alex.chen@huawei.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/misc/imx31_ccm.c
    M hw/misc/imx_ccm.c

  Log Message:
  -----------
  i.MX31: Fix bad printf format specifiers

We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201126111109.112238-3-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9197c7bddee830d8bc6077581b23450a5b27a460
      
https://github.com/qemu/qemu/commit/9197c7bddee830d8bc6077581b23450a5b27a460
  Author: Alex Chen <alex.chen@huawei.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/misc/imx6_ccm.c
    M hw/misc/imx6_src.c

  Log Message:
  -----------
  i.MX6: Fix bad printf format specifiers

We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201126111109.112238-4-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6c4e50b27874330d560780645af39d8d5932cd42
      
https://github.com/qemu/qemu/commit/6c4e50b27874330d560780645af39d8d5932cd42
  Author: Alex Chen <alex.chen@huawei.com>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/misc/imx6ul_ccm.c

  Log Message:
  -----------
  i.MX6ul: Fix bad printf format specifiers

We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201126111109.112238-5-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a724377a11a436e711cd91c817ff6428d7ccb829
      
https://github.com/qemu/qemu/commit/a724377a11a436e711cd91c817ff6428d7ccb829
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/arm/armv7m.c
    M hw/intc/armv7m_nvic.c
    M include/hw/intc/armv7m_nvic.h

  Log Message:
  -----------
  hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault

For M-profile CPUs, the range from 0xe0000000 to 0xe00fffff is the
Private Peripheral Bus range, which includes all of the memory mapped
devices and registers that are part of the CPU itself, including the
NVIC, systick timer, and debug and trace components like the Data
Watchpoint and Trace unit (DWT).  Within this large region, the range
0xe000e000 to 0xe000efff is the System Control Space (NVIC, system
registers, systick) and 0xe002e000 to 0exe002efff is its Non-secure
alias.

The architecture is clear that within the SCS unimplemented registers
should be RES0 for privileged accesses and generate BusFault for
unprivileged accesses, and we currently implement this.

It is less clear about how to handle accesses to unimplemented
regions of the wider PPB.  Unprivileged accesses should definitely
cause BusFaults (R_DQQS), but the behaviour of privileged accesses is
not given as a general rule.  However, the register definitions of
individual registers for components like the DWT all state that they
are RES0 if the relevant component is not implemented, so the
simplest way to provide that is to provide RAZ/WI for the whole range
for privileged accesses.  (The v7M Arm ARM does say that reserved
registers should be UNK/SBZP.)

Expand the container MemoryRegion that the NVIC exposes so that
it covers the whole PPB space. This means:
 * moving the address that the ARMV7M device maps it to down by
   0xe000 bytes
 * moving the off and the offsets within the container of all the
   subregions forward by 0xe000 bytes
 * adding a new default MemoryRegion that covers the whole container
   at a lower priority than anything else and which provides the
   RAZWI/BusFault behaviour

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-2-peter.maydell@linaro.org


  Commit: cad8e2e3160dd10371552fce6cd8c6e171503e13
      
https://github.com/qemu/qemu/commit/cad8e2e3160dd10371552fce6cd8c6e171503e13
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement v8.1M PXN extension

In v8.1M the PXN architecture extension adds a new PXN bit to the
MPU_RLAR registers, which forbids execution of code in the region
from a privileged mode.

This is another feature which is just in the generic "in v8.1M" set
and has no ID register field indicating its presence.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-3-peter.maydell@linaro.org


  Commit: 4018818840f499d0a478508aedbb6802c8eae928
      
https://github.com/qemu/qemu/commit/4018818840f499d0a478508aedbb6802c8eae928
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Don't clobber ID_PFR1.Security on M-profile cores

In arm_cpu_realizefn() we check whether the board code disabled EL3
via the has_el3 CPU object property, which we create if the CPU
starts with the ARM_FEATURE_EL3 feature bit.  If it is disabled, then
we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in
the ID_PFR1 and ID_AA64PFR0 registers.

This codepath was incorrectly being taken for M-profile CPUs, which
do not have an EL3 and don't set ARM_FEATURE_EL3, but which may have
the M-profile Security extension and so should have non-zero values
in the ID_PFR1.Security field.

Restrict the handling of the feature flag to A/R-profile cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-4-peter.maydell@linaro.org


  Commit: 83ff3d6add965c9752324de11eac5687121ea826
      
https://github.com/qemu/qemu/commit/83ff3d6add965c9752324de11eac5687121ea826
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/m-nocp.decode
    M target/arm/translate-vfp.c.inc
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Implement VSCCLRM insn

Implement the v8.1M VSCCLRM insn, which zeros floating point
registers if there is an active floating point context.
This requires support in write_neon_element32() for the MO_32
element size, so add it.

Because we want to use arm_gen_condlabel(), we need to move
the definition of that function up in translate.c so it is
before the #include of translate-vfp.c.inc.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-5-peter.maydell@linaro.org


  Commit: 6e21a013fbdf54960a079dccc90772bb622e28e8
      
https://github.com/qemu/qemu/commit/6e21a013fbdf54960a079dccc90772bb622e28e8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/t32.decode
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Implement CLRM instruction

In v8.1M the new CLRM instruction allows zeroing an arbitrary set of
the general-purpose registers and APSR.  Implement this.

The encoding is a subset of the LDMIA T2 encoding, using what would
be Rn=0b1111 (which UNDEFs for LDMIA).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-6-peter.maydell@linaro.org


  Commit: ede97c9d71110821738a48f88ff9f10d6bec017f
      
https://github.com/qemu/qemu/commit/ede97c9d71110821738a48f88ff9f10d6bec017f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc

  Log Message:
  -----------
  target/arm: Enforce M-profile VMRS/VMSR register restrictions

For M-profile before v8.1M, the only valid register for VMSR/VMRS is
the FPSCR.  We have a comment that states this, but the actual logic
to forbid accesses for any other register value is missing, so we
would end up with A-profile style behaviour.  Add the missing check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-7-peter.maydell@linaro.org


  Commit: 32a290b8c3c2dc85cd88bd8983baf900d575cabc
      
https://github.com/qemu/qemu/commit/32a290b8c3c2dc85cd88bd8983baf900d575cabc
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/translate-vfp.c.inc

  Log Message:
  -----------
  target/arm: Refactor M-profile VMSR/VMRS handling

Currently M-profile borrows the A-profile code for VMSR and VMRS
(access to the FP system registers), because all it needs to support
is the FPSCR.  In v8.1M things become significantly more complicated
in two ways:

 * there are several new FP system registers; some have side effects
   on read, and one (FPCXT_NS) needs to avoid the usual
   vfp_access_check() and the "only if FPU implemented" check

 * all sysregs are now accessible both by VMRS/VMSR (which
   reads/writes a general purpose register) and also by VLDR/VSTR
   (which reads/writes them directly to memory)

Refactor the structure of how we handle VMSR/VMRS to cope with this:

 * keep the M-profile code entirely separate from the A-profile code

 * abstract out the "read or write the general purpose register" part
   of the code into a loadfn or storefn function pointer, so we can
   reuse it for VLDR/VSTR.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-8-peter.maydell@linaro.org


  Commit: f7ed0c9433e7c5c157d2e6235eb5c8b93234a71a
      
https://github.com/qemu/qemu/commit/f7ed0c9433e7c5c157d2e6235eb5c8b93234a71a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Move general-use constant expanders up in translate.c

The constant-expander functions like negate, plus_2, etc, are
generally useful; move them up in translate.c so we can use them in
the VFP/Neon decoders as well as in the A32/T32/T16 decoders.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-9-peter.maydell@linaro.org


  Commit: 0bf0dd4dcbd9fab324700ac6e0cd061cd043de0d
      
https://github.com/qemu/qemu/commit/0bf0dd4dcbd9fab324700ac6e0cd061cd043de0d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp.decode

  Log Message:
  -----------
  target/arm: Implement VLDR/VSTR system register

Implement the new-in-v8.1M VLDR/VSTR variants which directly
read or write FP system registers to memory.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-10-peter.maydell@linaro.org


  Commit: 9542c30bcf13c495400d63616dd8dfa825b04685
      
https://github.com/qemu/qemu/commit/9542c30bcf13c495400d63616dd8dfa825b04685
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/translate-vfp.c.inc

  Log Message:
  -----------
  target/arm: Implement M-profile FPSCR_nzcvqc

v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves
like the existing FPSCR, except that it reads and writes only bits
[31:27] of the FPSCR (the N, Z, C, V and QC flag bits).  (Unlike the
FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not
permitted.)

Implement the register.  Since we don't yet implement MVE, we handle
the QC bit as RES0, with todo comments for where we will need to add
support later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-11-peter.maydell@linaro.org


  Commit: 6a017acdf83e3bb6bd5e85289ca90b2ea3282b7e
      
https://github.com/qemu/qemu/commit/6a017acdf83e3bb6bd5e85289ca90b2ea3282b7e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc

  Log Message:
  -----------
  target/arm: Use new FPCR_NZCV_MASK constant

We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR
in the previous commit; use it in a couple of places in existing code,
where we're masking out everything except NZCV for the "load to Rt=15
sets CPSR.NZCV" special case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-12-peter.maydell@linaro.org


  Commit: 96dfae686628fc14ba4f993824322b93395e221b
      
https://github.com/qemu/qemu/commit/96dfae686628fc14ba4f993824322b93395e221b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc

  Log Message:
  -----------
  target/arm: Factor out preserve-fp-state from full_vfp_access_check()

Factor out the code which handles M-profile lazy FP state preservation
from full_vfp_access_check(); accesses to the FPCXT_NS register are
a special case which need to do just this part (corresponding in the
pseudocode to the PreserveFPState() function), and not the full
set of actions matching the pseudocode ExecuteFPCheck() which
normal FP instructions need to do.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201119215617.29887-13-peter.maydell@linaro.org


  Commit: 64f863baeedc86590a608e2f1722dd8640aa9431
      
https://github.com/qemu/qemu/commit/64f863baeedc86590a608e2f1722dd8640aa9431
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc

  Log Message:
  -----------
  target/arm: Implement FPCXT_S fp system register

Implement the new-in-v8.1M FPCXT_S floating point system register.
This is for saving and restoring the secure floating point context,
and it reads and writes bits [27:0] from the FPSCR and the
CONTROL.SFPA bit in bit [31].

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-14-peter.maydell@linaro.org


  Commit: 99c7834fba4e5f204a82a1c456de2148b9595135
      
https://github.com/qemu/qemu/commit/99c7834fba4e5f204a82a1c456de2148b9595135
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M target/arm/cpu.c
    M target/arm/cpu.h

  Log Message:
  -----------
  hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M

The FPDSCR register has a similar layout to the FPSCR.  In v8.1M it
gains new fields FZ16 (if half-precision floating point is supported)
and LTPSIZE (always reads as 4).  Update the reset value and the code
that handles writes to this register accordingly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-16-peter.maydell@linaro.org


  Commit: a59b1ed618415212c5f0f05abc1192e14ad5fdbb
      
https://github.com/qemu/qemu/commit/a59b1ed618415212c5f0f05abc1192e14ad5fdbb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry

In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR
are zeroed for an exception taken to Non-secure state; for an
exception taken to Secure state they become UNKNOWN, and we chose to
leave them at their previous values.

In v8.1M the behaviour is specified more tightly and these registers
are always zeroed regardless of the security state that the exception
targets (see rule R_KPZV).  Implement this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-17-peter.maydell@linaro.org


  Commit: be9500bb17e1266ac5505a50c198397e16a56de4
      
https://github.com/qemu/qemu/commit/be9500bb17e1266ac5505a50c198397e16a56de4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures

In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule
R_LLRP).  (In previous versions of the architecture this was either
required or IMPDEF.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-18-peter.maydell@linaro.org


  Commit: cb45adb654bb34de9de6301b6981972dd107e342
      
https://github.com/qemu/qemu/commit/cb45adb654bb34de9de6301b6981972dd107e342
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  target/arm: Implement v8.1M REVIDR register

In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc
and is a read-only IMPDEF register providing implementation specific
minor revision information, like the v8A REVIDR_EL1. Implement this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-19-peter.maydell@linaro.org


  Commit: 3423fbf10427db7680d3237d4f62d8370052fca0
      
https://github.com/qemu/qemu/commit/3423fbf10427db7680d3237d4f62d8370052fca0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: Implement new v8.1M NOCP check for exception return

In v8.1M a new exception return check is added which may cause a NOCP
UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR
we must check whether access to CP10 from the Security state of the
returning exception is disabled; if it is then we must take a fault.

(Note that for our implementation CPPWR is always RAZ/WI and so can
never cause CP10 accesses to fail.)

The other v8.1M change to this register-clearing code is that if MVE
is implemented VPR must also be cleared, so add a TODO comment to
that effect.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-20-peter.maydell@linaro.org


  Commit: fe6fa228a71f0eb8b8ee315452e6a7736c537b1f
      
https://github.com/qemu/qemu/commit/fe6fa228a71f0eb8b8ee315452e6a7736c537b1f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/m-nocp.decode
    M target/arm/translate-vfp.c.inc

  Log Message:
  -----------
  target/arm: Implement new v8.1M VLLDM and VLSTM encodings

v8.1M adds new encodings of VLLDM and VLSTM (where bit 7 is set).
The only difference is that:
 * the old T1 encodings UNDEF if the implementation implements 32
   Dregs (this is currently architecturally impossible for M-profile)
 * the new T2 encodings have the implementation-defined option to
   read from memory (discarding the data) or write UNKNOWN values to
   memory for the stack slots that would be D16-D31

We choose not to make those accesses, so for us the two
instructions behave identically assuming they don't UNDEF.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-21-peter.maydell@linaro.org


  Commit: 0e83f905fb043cedb0282f77b97c50292e148faa
      
https://github.com/qemu/qemu/commit/0e83f905fb043cedb0282f77b97c50292e148faa
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M target/arm/cpu.h

  Log Message:
  -----------
  hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit

v8.1M introduces a new TRD flag in the CCR register, which enables
checking for stack frame integrity signatures on SG instructions.
This bit is not banked, and is always RAZ/WI to Non-secure code.
Adjust the code for handling CCR reads and writes to handle this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-23-peter.maydell@linaro.org


  Commit: 7f484147369080d36c411c4ba969f90d025aed55
      
https://github.com/qemu/qemu/commit/7f484147369080d36c411c4ba969f90d025aed55
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: Implement CCR_S.TRD behaviour for SG insns

v8.1M introduces a new TRD flag in the CCR register, which enables
checking for stack frame integrity signatures on SG instructions.
Add the code in the SG insn implementation for the new behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-24-peter.maydell@linaro.org


  Commit: 194cde6df20d139dbb952ef6c8c011f2126d03a4
      
https://github.com/qemu/qemu/commit/194cde6df20d139dbb952ef6c8c011f2126d03a4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  hw/intc/armv7m_nvic: Fix "return from inactive handler" check

In commit 077d7449100d824a4 we added code to handle the v8M
requirement that returns from NMI or HardFault forcibly deactivate
those exceptions regardless of what interrupt the guest is trying to
deactivate.  Unfortunately this broke the handling of the "illegal
exception return because the returning exception number is not
active" check for those cases.  In the pseudocode this test is done
on the exception the guest asks to return from, but because our
implementation was doing this in armv7m_nvic_complete_irq() after the
new "deactivate NMI/HardFault regardless" code we ended up doing the
test on the VecInfo for that exception instead, which usually meant
failing to raise the illegal exception return fault.

In the case for "configurable exception targeting the opposite
security state" we detected the illegal-return case but went ahead
and deactivated the VecInfo anyway, which is wrong because that is
the VecInfo for the other security state.

Rearrange the code so that we first identify the illegal return
cases, then see if we really need to deactivate NMI or HardFault
instead, and finally do the deactivation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-25-peter.maydell@linaro.org


  Commit: 46f4976f22a4549322307b34272e053d38653243
      
https://github.com/qemu/qemu/commit/46f4976f22a4549322307b34272e053d38653243
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M target/arm/cpu.h
    M target/arm/t32.decode

  Log Message:
  -----------
  target/arm: Implement M-profile "minimal RAS implementation"

For v8.1M the architecture mandates that CPUs must provide at
least the "minimal RAS implementation" from the Reliability,
Availability and Serviceability extension. This consists of:
 * an ESB instruction which is a NOP
   -- since it is in the HINT space we need only add a comment
 * an RFSR register which will RAZ/WI
 * a RAZ/WI AIRCR.IESB bit
   -- the code which handles writes to AIRCR does not allow setting
      of RES0 bits, so we already treat this as RAZ/WI; add a comment
      noting that this is deliberate
 * minimal implementation of the RAS register block at 0xe0005000
   -- this will be in a subsequent commit
 * setting the ID_PFR0.RAS field to 0b0010
   -- we will do this when we add the Cortex-M55 CPU model

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-26-peter.maydell@linaro.org


  Commit: 6ba430b58abfdbe03cbdbad6188c7d0384fffbea
      
https://github.com/qemu/qemu/commit/6ba430b58abfdbe03cbdbad6188c7d0384fffbea
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M include/hw/intc/armv7m_nvic.h

  Log Message:
  -----------
  hw/intc/armv7m_nvic: Implement read/write for RAS register block

The RAS feature has a block of memory-mapped registers at offset
0x5000 within the PPB.  For a "minimal RAS" implementation we provide
no error records and so the only registers that exist in the block
are ERRIIDR and ERRDEVID.

The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour
of the "nvic-default" region is actually valid for minimal-RAS,
so the main benefit of providing an explicit implementation of
the register block is more accurate LOG_UNIMP messages, and a
framework for where we could add a real RAS implementation later
if necessary.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-27-peter.maydell@linaro.org


  Commit: 71f916be1c7e9ede0e37d9cabc781b5a9e8638ff
      
https://github.com/qemu/qemu/commit/71f916be1c7e9ede0e37d9cabc781b5a9e8638ff
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M hw/arm/armv7m.c

  Log Message:
  -----------
  hw/arm/armv7m: Correct typo in QOM object name

Correct a typo in the name we give the NVIC object.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-28-peter.maydell@linaro.org


  Commit: 180834dcb8277a687b62f035b477abfd5a1ff978
      
https://github.com/qemu/qemu/commit/180834dcb8277a687b62f035b477abfd5a1ff978
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-12-10 (Thu, 10 Dec 2020)

  Changed paths:
    M MAINTAINERS
    M hw/Kconfig
    M hw/arm/armv7m.c
    M hw/arm/sbsa-ref.c
    M hw/arm/smmuv3-internal.h
    M hw/arm/xlnx-zcu102.c
    M hw/arm/xlnx-zynqmp.c
    M hw/intc/armv7m_nvic.c
    M hw/misc/imx25_ccm.c
    M hw/misc/imx31_ccm.c
    M hw/misc/imx6_ccm.c
    M hw/misc/imx6_src.c
    M hw/misc/imx6ul_ccm.c
    M hw/misc/imx_ccm.c
    M hw/net/can/meson.build
    A hw/net/can/trace-events
    A hw/net/can/trace.h
    A hw/net/can/xlnx-zynqmp-can.c
    M include/hw/arm/xlnx-zynqmp.h
    M include/hw/intc/armv7m_nvic.h
    A include/hw/net/xlnx-zynqmp-can.h
    M meson.build
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/m-nocp.decode
    M target/arm/m_helper.c
    M target/arm/t32.decode
    M target/arm/translate-vfp.c.inc
    M target/arm/translate.c
    M target/arm/vfp.decode
    M tests/qtest/meson.build
    M tests/qtest/npcm7xx_rng-test.c
    A tests/qtest/xlnx-can-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201210' 
into staging

target-arm queue:
 * hw/arm/smmuv3: Fix up L1STD_SPAN decoding
 * xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers
 * sbsa-ref: allow to use Cortex-A53/57/72 cpus
 * Various minor code cleanups
 * hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
 * Implement more pieces of ARMv8.1M support

# gpg: Signature made Thu 10 Dec 2020 11:46:43 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20201210: (36 commits)
  hw/arm/armv7m: Correct typo in QOM object name
  hw/intc/armv7m_nvic: Implement read/write for RAS register block
  target/arm: Implement M-profile "minimal RAS implementation"
  hw/intc/armv7m_nvic: Fix "return from inactive handler" check
  target/arm: Implement CCR_S.TRD behaviour for SG insns
  hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
  target/arm: Implement new v8.1M VLLDM and VLSTM encodings
  target/arm: Implement new v8.1M NOCP check for exception return
  target/arm: Implement v8.1M REVIDR register
  target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures
  target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry
  hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
  target/arm: Implement FPCXT_S fp system register
  target/arm: Factor out preserve-fp-state from full_vfp_access_check()
  target/arm: Use new FPCR_NZCV_MASK constant
  target/arm: Implement M-profile FPSCR_nzcvqc
  target/arm: Implement VLDR/VSTR system register
  target/arm: Move general-use constant expanders up in translate.c
  target/arm: Refactor M-profile VMSR/VMRS handling
  target/arm: Enforce M-profile VMRS/VMSR register restrictions
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


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