[Qemu-commits] [qemu/qemu] d5c90c: hw/riscv: sifive

qemu-commits
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] d5c90c: hw/riscv: sifive_u: Allow passing cus

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] d5c90c: hw/riscv: sifive_u: Allow passing custom DTB
Date:	Tue, 03 Nov 2020 13:07:46 -0800
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d5c90cf3f648c544af7a75a8908b58722062dc57
      
https://github.com/qemu/qemu/commit/d5c90cf3f648c544af7a75a8908b58722062dc57
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Allow passing custom DTB

Extend sifive_u machine to allow passing custom DTB using "-dtb"
command-line parameter. This will help users pass modified DTB
or Linux SiFive DTB to sifive_u machine.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201022053225.2596110-1-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4e1e3003fbfbba38bd46d0fd3677b2d43b0a91e3
      
https://github.com/qemu/qemu/commit/4e1e3003fbfbba38bd46d0fd3677b2d43b0a91e3
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Allow passing custom DTB

Extend virt machine to allow passing custom DTB using "-dtb"
command-line parameter. This will help users pass modified DTB
to virt machine.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201022053225.2596110-2-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 284d697c74ef3f4210cbccc5cd6b4894740e4ab3
      
https://github.com/qemu/qemu/commit/284d697c74ef3f4210cbccc5cd6b4894740e4ab3
  Author: Yifei Jiang <jiangyifei@huawei.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit

mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32.
This patch expands mstatus and vsstatus to uint64_t instead of
target_ulong so that it can be saved as one unit and reduce some
ifdefs in the code.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-2-jiangyifei@huawei.com


  Commit: f7697f0e629eb75d411bc6f314c6fff68fa4c238
      
https://github.com/qemu/qemu/commit/f7697f0e629eb75d411bc6f314c6fff68fa4c238
  Author: Yifei Jiang <jiangyifei@huawei.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/internals.h
    A target/riscv/machine.c
    M target/riscv/meson.build

  Log Message:
  -----------
  target/riscv: Add basic vmstate description of CPU

Add basic CPU state description to the newly created machine.c

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 24beb03e46de8602b318d5f234ce0ba489a7dbfc
      
https://github.com/qemu/qemu/commit/24beb03e46de8602b318d5f234ce0ba489a7dbfc
  Author: Yifei Jiang <jiangyifei@huawei.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M target/riscv/machine.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h

  Log Message:
  -----------
  target/riscv: Add PMP state description

In the case of supporting PMP feature, add PMP state description
to vmstate_riscv_cpu.

'vmstate_pmp_addr' and 'num_rules' could be regenerated by
pmp_update_rule(). But there exists the problem of updating
num_rules repeatedly in pmp_update_rule(). So here extracts
pmp_update_rule_addr() and pmp_update_rule_nums() to update
'vmstate_pmp_addr' and 'num_rules' respectively.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-4-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 35e07821ff99a7511cf2594bd14bbcf8e8b7a528
      
https://github.com/qemu/qemu/commit/35e07821ff99a7511cf2594bd14bbcf8e8b7a528
  Author: Yifei Jiang <jiangyifei@huawei.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Add H extension state description

In the case of supporting H extension, add H extension description
to vmstate_riscv_cpu.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-5-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bb02edcd86755a15535b3f8956e6f75df41770ad
      
https://github.com/qemu/qemu/commit/bb02edcd86755a15535b3f8956e6f75df41770ad
  Author: Yifei Jiang <jiangyifei@huawei.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M target/riscv/machine.c

  Log Message:
  -----------
  target/riscv: Add V extension state description

In the case of supporting V extension, add V extension description
to vmstate_riscv_cpu.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-6-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: dbd3ec548ae9ada6e6a5c1f5b6359521fd29fd4b
      
https://github.com/qemu/qemu/commit/dbd3ec548ae9ada6e6a5c1f5b6359521fd29fd4b
  Author: Yifei Jiang <jiangyifei@huawei.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M hw/intc/sifive_plic.c
    M include/hw/intc/sifive_plic.h

  Log Message:
  -----------
  target/riscv: Add sifive_plic vmstate

Add sifive_plic vmstate for supporting sifive_plic migration.
Current vmstate framework only supports one structure parameter
as num field to describe variable length arrays, so introduce
num_enables.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-7-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 08b86e3b8f5209b1c39f22a6d367f347eaf0f8be
      
https://github.com/qemu/qemu/commit/08b86e3b8f5209b1c39f22a6d367f347eaf0f8be
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M hw/riscv/microchip_pfsoc.c

  Log Message:
  -----------
  hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps

It is not easy to find out the memory map for a specific component
in the PolarFire SoC as the information is scattered in different
documents. Add some comments so that people can know where to get
such information from the Microchip website.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-2-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3400b15bbe0fbc672fee9a18268154b07a1fed2e
      
https://github.com/qemu/qemu/commit/3400b15bbe0fbc672fee9a18268154b07a1fed2e
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M MAINTAINERS
    M hw/misc/Kconfig
    A hw/misc/mchp_pfsoc_dmc.c
    M hw/misc/meson.build
    A include/hw/misc/mchp_pfsoc_dmc.h

  Log Message:
  -----------
  hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support

The PolarFire SoC DDR Memory Controller mainly includes 2 modules,
called SGMII PHY module and the CFG module, as documented in the
chipset datasheet.

This creates a single file that groups these 2 modules, providing
the minimum functionalities that make the HSS DDR initialization
codes happy.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-3-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 933f73f13e5ceb9357e9c9d51ce39c43aa1d534f
      
https://github.com/qemu/qemu/commit/933f73f13e5ceb9357e9c9d51ce39c43aa1d534f
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M hw/riscv/Kconfig
    M hw/riscv/microchip_pfsoc.c
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/riscv: microchip_pfsoc: Connect DDR memory controller modules

Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a937b302831f12094437cdbdfc859bff9f093525
      
https://github.com/qemu/qemu/commit/a937b302831f12094437cdbdfc859bff9f093525
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M MAINTAINERS
    M hw/misc/Kconfig
    A hw/misc/mchp_pfsoc_ioscb.c
    M hw/misc/meson.build
    A include/hw/misc/mchp_pfsoc_ioscb.h

  Log Message:
  -----------
  hw/misc: Add Microchip PolarFire SoC IOSCB module support

This creates a model for PolarFire SoC IOSCB [1] module. It actually
contains lots of sub-modules like various PLLs to control different
peripherals. Only the mininum capabilities are emulated to make the
HSS DDR memory initialization codes happy. Lots of sub-modules are
created as an unimplemented devices.

[1] PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm in
    
https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-5-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e35d617919a76b92af799baa483c4ff0e7c090e3
      
https://github.com/qemu/qemu/commit/e35d617919a76b92af799baa483c4ff0e7c090e3
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M hw/riscv/Kconfig
    M hw/riscv/microchip_pfsoc.c
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/riscv: microchip_pfsoc: Connect the IOSCB module

Previously IOSCB_CFG was created as an unimplemented device. With
the new IOSCB model, its memory range is already covered by the
IOSCB hence remove the previous unimplemented device creation in
the SoC codes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-6-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0f25065cb616f74729383fbf30369c374305ebb1
      
https://github.com/qemu/qemu/commit/0f25065cb616f74729383fbf30369c374305ebb1
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M MAINTAINERS
    M hw/misc/Kconfig
    A hw/misc/mchp_pfsoc_sysreg.c
    M hw/misc/meson.build
    A include/hw/misc/mchp_pfsoc_sysreg.h

  Log Message:
  -----------
  hw/misc: Add Microchip PolarFire SoC SYSREG module support

This creates a minimum model for Microchip PolarFire SoC SYSREG
module. It only implements the ENVM_CR register to tell guest
software that eNVM is running at the configured divider rate.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-7-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cdd58c70fbcb7276d3df656941278e4395ecce14
      
https://github.com/qemu/qemu/commit/cdd58c70fbcb7276d3df656941278e4395ecce14
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M hw/riscv/Kconfig
    M hw/riscv/microchip_pfsoc.c
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/riscv: microchip_pfsoc: Connect the SYSREG module

Previously SYSREG was created as an unimplemented device. Now that
we have a simple SYSREG module, connect it.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-8-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 27c22b2de08f71500df581563cc9d22638a14b4d
      
https://github.com/qemu/qemu/commit/27c22b2de08f71500df581563cc9d22638a14b4d
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M hw/riscv/microchip_pfsoc.c
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/riscv: microchip_pfsoc: Map the reserved memory at address 0

Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's reserved memory. Let's map it.

[1] See the config_copy() calls in various places in ddr_setup() in
    the HSS source codes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f03100d718579f022316349687dc9127ff01f0ee
      
https://github.com/qemu/qemu/commit/f03100d718579f022316349687dc9127ff01f0ee
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M hw/riscv/microchip_pfsoc.c
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/riscv: microchip_pfsoc: Correct DDR memory map

When system memory is larger than 1 GiB (high memory), PolarFire SoC
maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is
aliased to the same 1 GiB low memory with different cache attributes.

At present QEMU maps the system memory contiguously from 0x8000_0000.
This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is
the alias to the high memory, and even physical memory is only 1 GiB,
the HSS codes still tries to probe the high memory alias address.
It seems there is no issue on the real hardware, so we will have to
take that into the consideration in our emulation. Due to this, we
we increase the default system memory size to 1537 MiB (the minimum
required high memory size by HSS) so that user gets notified an error
when less than 1537 MiB is specified.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201101170538.3732-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 90742c5496f3bf76203c0759f783444af10fb61a
      
https://github.com/qemu/qemu/commit/90742c5496f3bf76203c0759f783444af10fb61a
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M hw/riscv/microchip_pfsoc.c
    M include/hw/riscv/microchip_pfsoc.h

  Log Message:
  -----------
  hw/riscv: microchip_pfsoc: Hook the I2C1 controller

The latest SD card image [1] released by Microchip ships a Linux
kernel with built-in PolarFire SoC I2C driver support. The device
tree file includes the description for the I2C1 node hence kernel
tries to probe the I2C1 device during boot.

It is enough to create an unimplemented device for I2C1 to allow
the kernel to continue booting to the shell.

[1] 
ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-11-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 422819776101520cb56658ee5facf926526cf870
      
https://github.com/qemu/qemu/commit/422819776101520cb56658ee5facf926526cf870
  Author: Xinhao Zhang <zhangxinhao1@huawei.com>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv/csr.c : add space before the open parenthesis '('

Fix code style. Space required before the open parenthesis '('.

Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
Signed-off-by: Kai Deng <dengkai1@huawei.com>
Reported-by: Euler Robot <euler.robot@huawei.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201030004815.4172849-1-zhangxinhao1@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9167d34921fdd4d2cccfd71aad3409ae1090c95a
      
https://github.com/qemu/qemu/commit/9167d34921fdd4d2cccfd71aad3409ae1090c95a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-11-03 (Tue, 03 Nov 2020)

  Changed paths:
    M MAINTAINERS
    M hw/intc/sifive_plic.c
    M hw/misc/Kconfig
    A hw/misc/mchp_pfsoc_dmc.c
    A hw/misc/mchp_pfsoc_ioscb.c
    A hw/misc/mchp_pfsoc_sysreg.c
    M hw/misc/meson.build
    M hw/riscv/Kconfig
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c
    M include/hw/intc/sifive_plic.h
    A include/hw/misc/mchp_pfsoc_dmc.h
    A include/hw/misc/mchp_pfsoc_ioscb.h
    A include/hw/misc/mchp_pfsoc_sysreg.h
    M include/hw/riscv/microchip_pfsoc.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/internals.h
    A target/riscv/machine.c
    M target/riscv/meson.build
    M target/riscv/op_helper.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20201103' into staging

This series adds support for migration to RISC-V QEMU and expands the
Microchip PFSoC to allow unmodified HSS and Linux boots.

# gpg: Signature made Tue 03 Nov 2020 15:19:45 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20201103:
  target/riscv/csr.c : add space before the open parenthesis '('
  hw/riscv: microchip_pfsoc: Hook the I2C1 controller
  hw/riscv: microchip_pfsoc: Correct DDR memory map
  hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
  hw/riscv: microchip_pfsoc: Connect the SYSREG module
  hw/misc: Add Microchip PolarFire SoC SYSREG module support
  hw/riscv: microchip_pfsoc: Connect the IOSCB module
  hw/misc: Add Microchip PolarFire SoC IOSCB module support
  hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
  hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
  hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps
  target/riscv: Add sifive_plic vmstate
  target/riscv: Add V extension state description
  target/riscv: Add H extension state description
  target/riscv: Add PMP state description
  target/riscv: Add basic vmstate description of CPU
  target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
  hw/riscv: virt: Allow passing custom DTB
  hw/riscv: sifive_u: Allow passing custom DTB

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/8507c9d5c9a6...9167d34921fd
[Prev in Thread]
Current Thread
[Next in Thread]
[Qemu-commits] [qemu/qemu] d5c90c: hw/riscv: sifive_u: Allow passing custom DTB, Peter Maydell <=
Prev by Date: [Qemu-commits] [qemu/qemu] eada6d: qmp: fix aio_poll() assertion failure on Windows
Next by Date: [Qemu-commits] [qemu/qemu] 3d6e32: Update version for v5.2.0-rc0 release
Previous by thread: [Qemu-commits] [qemu/qemu] eada6d: qmp: fix aio_poll() assertion failure on Windows
Next by thread: [Qemu-commits] [qemu/qemu] 3d6e32: Update version for v5.2.0-rc0 release
Index(es):
- Date
- Thread