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[Qemu-commits] [qemu/qemu] 015ee8: target/arm: Introduce neon_full_reg_o
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 015ee8: target/arm: Introduce neon_full_reg_offset |
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Date: |
Tue, 03 Nov 2020 03:36:48 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 015ee81a4c06b644969f621fd9965cc6372b879e
https://github.com/qemu/qemu/commit/015ee81a4c06b644969f621fd9965cc6372b879e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/translate-neon.c.inc
M target/arm/translate-vfp.c.inc
M target/arm/translate.c
Log Message:
-----------
target/arm: Introduce neon_full_reg_offset
This function makes it clear that we're talking about the whole
register, and not the 32-bit piece at index 0. This fixes a bug
when running on a big-endian host.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7ec85c02833f4264840c6ed78b749443a7b4ffe0
https://github.com/qemu/qemu/commit/7ec85c02833f4264840c6ed78b749443a7b4ffe0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/translate-neon.c.inc
M target/arm/translate.c
Log Message:
-----------
target/arm: Move neon_element_offset to translate.c
This will shortly have users outside of translate-neon.c.inc.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0f2cdc82276a723ee58562b56b9d537a4bd7bfef
https://github.com/qemu/qemu/commit/0f2cdc82276a723ee58562b56b9d537a4bd7bfef
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use neon_element_offset in neon_load/store_reg
These are the only users of neon_reg_offset, so remove that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d8719785fde2f5041986853a314c05c6f567d3cb
https://github.com/qemu/qemu/commit/d8719785fde2f5041986853a314c05c6f567d3cb
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Use neon_element_offset in vfp_reg_offset
This seems a bit more readable than using offsetof CPU_DoubleU.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a712266f5d5a36d04b22fe69fa15592d62bed019
https://github.com/qemu/qemu/commit/a712266f5d5a36d04b22fe69fa15592d62bed019
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/translate-neon.c.inc
M target/arm/translate.c
Log Message:
-----------
target/arm: Add read/write_neon_element32
Model these off the aa64 read/write_vec_element functions.
Use it within translate-neon.c.inc. The new functions do
not allocate or free temps, so this rearranges the calling
code a bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4d5fa5a80ac28f34b8497be1e85371272413a12e
https://github.com/qemu/qemu/commit/4d5fa5a80ac28f34b8497be1e85371272413a12e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/translate-vfp.c.inc
M target/arm/translate.c
Log Message:
-----------
target/arm: Expand read/write_neon_element32 to all MemOp
We can then use this to improve VMOV (scalar to gp) and
VMOV (gp to scalar) so that we simply perform the memory
operation that we wanted, rather than inserting or
extracting from a 32-bit quantity.
These were the last uses of neon_load/store_reg, so remove them.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 21c1c0e50b73c580c6bfc8f2314d1b6a14793561
https://github.com/qemu/qemu/commit/21c1c0e50b73c580c6bfc8f2314d1b6a14793561
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/translate-vfp.c.inc
M target/arm/translate.c
Log Message:
-----------
target/arm: Rename neon_load_reg32 to vfp_load_reg32
The only uses of this function are for loading VFP
single-precision values, and nothing to do with NEON.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0aa8e700a53b0aa7275ed747b8fa3acb61d35f2d
https://github.com/qemu/qemu/commit/0aa8e700a53b0aa7275ed747b8fa3acb61d35f2d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/translate-neon.c.inc
M target/arm/translate.c
Log Message:
-----------
target/arm: Add read/write_neon_element64
Replace all uses of neon_load/store_reg64 within translate-neon.c.inc.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b38b96ca90827012ab8eb045c1337cea83a54c4b
https://github.com/qemu/qemu/commit/b38b96ca90827012ab8eb045c1337cea83a54c4b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/translate-vfp.c.inc
M target/arm/translate.c
Log Message:
-----------
target/arm: Rename neon_load_reg64 to vfp_load_reg64
The only uses of this function are for loading VFP
double-precision values, and nothing to do with NEON.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-10-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9f1a5f93c2dd345dc6c8fe86ed14bf1485056f6e
https://github.com/qemu/qemu/commit/9f1a5f93c2dd345dc6c8fe86ed14bf1485056f6e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/translate-neon.c.inc
Log Message:
-----------
target/arm: Simplify do_long_3d and do_2scalar_long
In both cases, we can sink the write-back and perform
the accumulate into the normal destination temps.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-11-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8aab18a2c5209e4e48998a61fbc2d89f374331ed
https://github.com/qemu/qemu/commit/8aab18a2c5209e4e48998a61fbc2d89f374331ed
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/translate-neon.c.inc
M target/arm/translate.c
Log Message:
-----------
target/arm: Improve do_prewiden_3d
We can use proper widening loads to extend 32-bit inputs,
and skip the "widenfn" step.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 552714c0812a10e5cff239bd29928e5fcb8d8b3b
https://github.com/qemu/qemu/commit/552714c0812a10e5cff239bd29928e5fcb8d8b3b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/vec_helper.c
Log Message:
-----------
target/arm: Fix float16 pairwise Neon ops on big-endian hosts
In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error
meant we were using the H4() address swizzler macro rather than the
H2() which is required for 2-byte data. This had no effect on
little-endian hosts but meant we put the result data into the
destination Dreg in the wrong order on big-endian hosts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201028191712.4910-2-peter.maydell@linaro.org
Commit: d1a9254be5cc93afb15be19f7543da6ff4806256
https://github.com/qemu/qemu/commit/d1a9254be5cc93afb15be19f7543da6ff4806256
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/vec_helper.c
Log Message:
-----------
target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts
The helper functions for performing the udot/sdot operations against
a scalar were not using an address-swizzling macro when converting
the index of the scalar element into a pointer into the vm array.
This had no effect on little-endian hosts but meant we generated
incorrect results on big-endian hosts.
For these insns, the index is indexing over group of 4 8-bit values,
so 32 bits per indexed entity, and H4() is therefore what we want.
(For Neon the only possible input indexes are 0 and 1.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201028191712.4910-3-peter.maydell@linaro.org
Commit: 373e7ffde9bae90a20fb5db21b053f23091689f4
https://github.com/qemu/qemu/commit/373e7ffde9bae90a20fb5db21b053f23091689f4
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: fix handling of HCR.FB
HCR should be applied when NS is set, not when it is cleared.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9bd268bae5c4760870522292fb1d46e7da7e372a
https://github.com/qemu/qemu/commit/9bd268bae5c4760870522292fb1d46e7da7e372a
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: fix LORID_EL1 access check
Secure mode is not exempted from checking SCR_EL3.TLOR, and in the
future HCR_EL2.TLOR when S-EL2 is enabled.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 437588d81d99ac91cb1e4ff060610458e67852d5
https://github.com/qemu/qemu/commit/437588d81d99ac91cb1e4ff060610458e67852d5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M disas/capstone.c
Log Message:
-----------
disas/capstone: Fix monitor disassembly of >32 bytes
If we're using the capstone disassembler, disassembly of a run of
instructions more than 32 bytes long disassembles the wrong data for
instructions beyond the 32 byte mark:
(qemu) xp /16x 0x100
0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000
0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000
0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574
0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000
(qemu) xp /16i 0x100
0x00000100: 00000005 andeq r0, r0, r5
0x00000104: 54410001 strbpl r0, [r1], #-1
0x00000108: 00000001 andeq r0, r0, r1
0x0000010c: 00001000 andeq r1, r0, r0
0x00000110: 00000000 andeq r0, r0, r0
0x00000114: 00000004 andeq r0, r0, r4
0x00000118: 54410002 strbpl r0, [r1], #-2
0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
0x00000120: 54410001 strbpl r0, [r1], #-1
0x00000124: 00000001 andeq r0, r0, r1
0x00000128: 00001000 andeq r1, r0, r0
0x0000012c: 00000000 andeq r0, r0, r0
0x00000130: 00000004 andeq r0, r0, r4
0x00000134: 54410002 strbpl r0, [r1], #-2
0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
0x0000013c: 00000000 andeq r0, r0, r0
Here the disassembly of 0x120..0x13f is using the data that is in
0x104..0x123.
This is caused by passing the wrong value to the read_memory_func().
The intention is that at this point in the loop the 'cap_buf' buffer
already contains 'csize' bytes of data for the instruction at guest
addr 'pc', and we want to read in an extra 'tsize' bytes. Those
extra bytes are therefore at 'pc + csize', not 'pc'. On the first
time through the loop 'csize' happens to be zero, so the initial read
of 32 bytes into cap_buf is correct and as long as the disassembly
never needs to read more data we return the correct information.
Use the correct guest address in the call to read_memory_func().
Cc: qemu-stable@nongnu.org
Fixes: https://bugs.launchpad.net/qemu/+bug/1900779
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201022132445.25039-1-peter.maydell@linaro.org
Commit: 744a790ec01a30033309e6a2155df4d61061e184
https://github.com/qemu/qemu/commit/744a790ec01a30033309e6a2155df4d61061e184
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
Use the BIT_ULL() macro to ensure we use 64-bit arithmetic.
This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN):
CID 1432363 (#1 of 1): Unintentional integer overflow:
overflow_before_widen:
Potentially overflowing expression 1 << scale with type int
(32 bits, signed) is evaluated using 32-bit arithmetic, and
then used in a context that expects an expression of type
hwaddr (64 bits, unsigned).
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20201030144617.1535064-1-philmd@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3f0b59070c89f2261ff5961980ff5203b0c6bea9
https://github.com/qemu/qemu/commit/3f0b59070c89f2261ff5961980ff5203b0c6bea9
Author: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: fix SVE for EL3 direct kernel boot
When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so
that SVE will not trap to EL3.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030151541.11976-1-remi@remlab.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0080edc45e93324e085e93db89180a2945897c5a
https://github.com/qemu/qemu/commit/0080edc45e93324e085e93db89180a2945897c5a
Author: AlexChen <alex.chen@huawei.com>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M hw/display/omap_lcdc.c
Log Message:
-----------
hw/display/omap_lcdc: Fix potential NULL pointer dereference
In omap_lcd_interrupts(), the pointer omap_lcd is dereferinced before
being check if it is valid, which may lead to NULL pointer dereference.
So move the assignment to surface after checking that the omap_lcd is valid
and move surface_bits_per_pixel(surface) to after the surface assignment.
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: AlexChen <alex.chen@huawei.com>
Message-id: 5F9CDB8A.9000001@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 18520fa465a08b81972afd9a25056f102f0180c9
https://github.com/qemu/qemu/commit/18520fa465a08b81972afd9a25056f102f0180c9
Author: AlexChen <alex.chen@huawei.com>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M hw/display/exynos4210_fimd.c
Log Message:
-----------
hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
In exynos4210_fimd_update(), the pointer s is dereferinced before
being check if it is valid, which may lead to NULL pointer dereference.
So move the assignment to global_width after checking that the s is valid.
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 5F9F8D88.9030102@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7142eb9e24b4aa5118cd67038057f15694d782aa
https://github.com/qemu/qemu/commit/7142eb9e24b4aa5118cd67038057f15694d782aa
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M target/arm/m_helper.c
Log Message:
-----------
target/arm: Get correct MMU index for other-security-state
In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to
armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el().
This is incorrect when the security state being queried is not the
current one, because arm_current_el() uses the current security state
to determine which of the banked CONTROL.nPRIV bits to look at.
The effect was that if (for instance) Secure state was in privileged
mode but Non-Secure was not then we would return the wrong MMU index.
The only places where we are using this function in a way that could
trigger this bug are for the stack loads during a v8M function-return
and for the instruction fetch of a v8M SG insn.
Fix the bug by expanding out the M-profile version of the
arm_current_el() logic inline so it can use the passed in secstate
rather than env->v7m.secure.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201022164408.13214-1-peter.maydell@linaro.org
Commit: 76346b6264a9b01979829a5d4366c3799e2dd15a
https://github.com/qemu/qemu/commit/76346b6264a9b01979829a5d4366c3799e2dd15a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M configure
Log Message:
-----------
configure: Test that gio libs from pkg-config work
On some hosts (eg Ubuntu Bionic) pkg-config returns a set of
libraries for gio-2.0 which don't actually work when compiling
statically. (Specifically, the returned library string includes
-lmount, but not -lblkid which -lmount depends upon, so linking
fails due to missing symbols.)
Check that the libraries work, and don't enable gio if they don't,
in the same way we do for gnutls.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200928160402.7961-1-peter.maydell@linaro.org
Commit: c20a135a7a14d846699b0cfc9f74bcc2a226bee6
https://github.com/qemu/qemu/commit/c20a135a7a14d846699b0cfc9f74bcc2a226bee6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt
into the GICv3CPUState struct's maintenance_irq field. This will
only work if the board happens to have already wired up the CPU
maintenance IRQ before the GIC was realized. Unfortunately this is
not the case for the 'virt' board, and so the value that gets copied
is NULL (since a qemu_irq is really a pointer to an IRQState struct
under the hood). The effect is that the CPU interface code never
actually raises the maintenance interrupt line.
Instead, since the GICv3CPUState has a pointer to the CPUState, make
the dereference at the point where we want to raise the interrupt, to
avoid an implicit requirement on board code to wire things up in a
particular order.
Reported-by: Jose Martins <josemartins90@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201009153904.28529-1-peter.maydell@linaro.org
Reviewed-by: Luc Michel <luc@lmichel.fr>
Commit: 92bb29f9b2c3d4a98eef5f0db935d4be291eec72
https://github.com/qemu/qemu/commit/92bb29f9b2c3d4a98eef5f0db935d4be291eec72
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M scripts/kernel-doc
Log Message:
-----------
scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments
The kerneldoc script currently emits Sphinx markup for a macro with
arguments that uses the c:function directive. This is correct for
Sphinx versions earlier than Sphinx 3, where c:macro doesn't allow
documentation of macros with arguments and c:function is not picky
about the syntax of what it is passed. However, in Sphinx 3 the
c:macro directive was enhanced to support macros with arguments,
and c:function was made more picky about what syntax it accepted.
When kerneldoc is told that it needs to produce output for Sphinx
3 or later, make it emit c:function only for functions and c:macro
for macros with arguments. We assume that anything with a return
type is a function and anything without is a macro.
This fixes the Sphinx error:
/home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/qom/object.h:155:Error
in declarator
If declarator-id with parameters (e.g., 'void f(int arg)'):
Invalid C declaration: Expected identifier in nested name. [error at 25]
DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME)
-------------------------^
If parenthesis in noptr-declarator (e.g., 'void (*f(int arg))(double)'):
Error in declarator or parameters
Invalid C declaration: Expecting "(" in parameters. [error at 39]
DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME)
---------------------------------------^
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 20201030174700.7204-2-peter.maydell@linaro.org
Commit: 5a4b0d411283c92c5a394aaa4b7c19f6568a54fd
https://github.com/qemu/qemu/commit/5a4b0d411283c92c5a394aaa4b7c19f6568a54fd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M docs/qemu-option-trace.rst.inc
Log Message:
-----------
qemu-option-trace.rst.inc: Don't use option:: markup
Sphinx 3.2 is pickier than earlier versions about the option:: markup,
and complains about our usage in qemu-option-trace.rst:
../../docs/qemu-option-trace.rst.inc:4:Malformed option description
'[enable=]PATTERN', should look like "opt", "-opt args", "--opt args",
"/opt args" or "+opt args"
In this file, we're really trying to document the different parts of
the top-level --trace option, which qemu-nbd.rst and qemu-img.rst
have already introduced with an option:: markup. So it's not right
to use option:: here anyway. Switch to a different markup
(definition lists) which gives about the same formatted output.
(Unlike option::, this markup doesn't produce index entries; but
at the moment we don't do anything much with indexes anyway, and
in any case I think it doesn't make much sense to have individual
index entries for the sub-parts of the --trace option.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 20201030174700.7204-3-peter.maydell@linaro.org
Commit: ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a
https://github.com/qemu/qemu/commit/ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-11-02 (Mon, 02 Nov 2020)
Changed paths:
M tests/qtest/npcm7xx_rng-test.c
Log Message:
-----------
tests/qtest/npcm7xx_rng-test: Disable randomness tests
The randomness tests in the NPCM7xx RNG test fail intermittently
but fairly frequently. On my machine running the test in a loop:
while QTEST_QEMU_BINARY=./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-test;
do true; done
will fail in less than a minute with an error like:
ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs:
assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01):
(0.00286205989 > 0.01)
(Failures have been observed on all 4 of the randomness tests,
not just first_byte_runs.)
It's not clear why these tests are failing like this, but intermittent
failures make CI and merge testing awkward, so disable running them
unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when
running the test suite, until we work out the cause.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20201102152454.8287-1-peter.maydell@linaro.org
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Commit: c7a7a877b716cf14848f1fd5c754d293e2f8d852
https://github.com/qemu/qemu/commit/c7a7a877b716cf14848f1fd5c754d293e2f8d852
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-11-03 (Tue, 03 Nov 2020)
Changed paths:
M configure
M disas/capstone.c
M docs/qemu-option-trace.rst.inc
M hw/arm/boot.c
M hw/arm/smmuv3.c
M hw/display/exynos4210_fimd.c
M hw/display/omap_lcdc.c
M hw/intc/arm_gicv3_cpuif.c
M include/hw/intc/arm_gicv3_common.h
M scripts/kernel-doc
M target/arm/helper.c
M target/arm/m_helper.c
M target/arm/translate-neon.c.inc
M target/arm/translate-vfp.c.inc
M target/arm/translate.c
M target/arm/vec_helper.c
M tests/qtest/npcm7xx_rng-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201102'
into staging
target-arm queue:
* target/arm: Fix Neon emulation bugs on big-endian hosts
* target/arm: fix handling of HCR.FB
* target/arm: fix LORID_EL1 access check
* disas/capstone: Fix monitor disassembly of >32 bytes
* hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
* hw/arm/boot: fix SVE for EL3 direct kernel boot
* hw/display/omap_lcdc: Fix potential NULL pointer dereference
* hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
* target/arm: Get correct MMU index for other-security-state
* configure: Test that gio libs from pkg-config work
* hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
* docs: Fix building with Sphinx 3
* tests/qtest/npcm7xx_rng-test: Disable randomness tests
# gpg: Signature made Mon 02 Nov 2020 17:09:00 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20201102: (26 commits)
tests/qtest/npcm7xx_rng-test: Disable randomness tests
qemu-option-trace.rst.inc: Don't use option:: markup
scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments
hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
configure: Test that gio libs from pkg-config work
target/arm: Get correct MMU index for other-security-state
hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
hw/display/omap_lcdc: Fix potential NULL pointer dereference
hw/arm/boot: fix SVE for EL3 direct kernel boot
hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
disas/capstone: Fix monitor disassembly of >32 bytes
target/arm: fix LORID_EL1 access check
target/arm: fix handling of HCR.FB
target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts
target/arm: Fix float16 pairwise Neon ops on big-endian hosts
target/arm: Improve do_prewiden_3d
target/arm: Simplify do_long_3d and do_2scalar_long
target/arm: Rename neon_load_reg64 to vfp_load_reg64
target/arm: Add read/write_neon_element64
target/arm: Rename neon_load_reg32 to vfp_load_reg32
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/8545ae485b1e...c7a7a877b716
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