[Qemu-commits] [qemu/qemu] 694301: riscv: Convert interrupt logs to use qemu_log_mask()

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 69430111ab2fe3f32548a0e70437655d0d937a6a
      
https://github.com/qemu/qemu/commit/69430111ab2fe3f32548a0e70437655d0d937a6a
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M target/riscv/cpu_helper.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  riscv: Convert interrupt logs to use qemu_log_mask()

Currently we log interrupts and exceptions using the trace backend in
riscv_cpu_do_interrupt(). We also log exceptions using the interrupt log
mask (-d int) in riscv_raise_exception().

This patch converts riscv_cpu_do_interrupt() to log both interrupts and
exceptions with the interrupt log mask, so that both are printed when a
user runs QEMU with -d int.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 
29a8c766c7c4748d0f2711c3a0abb81208138c5e.1601652179.git.alistair.francis@wdc.com


  Commit: 801da1701cbc3f904639706e830ba20098d0ab5f
      
https://github.com/qemu/qemu/commit/801da1701cbc3f904639706e830ba20098d0ab5f
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    R hw/intc/sifive_plic.h
    A include/hw/intc/sifive_plic.h

  Log Message:
  -----------
  hw/intc: Move sifive_plic.h to the include directory

Since sifive_plic.h is used by hw/intc/sifive_plic.c,
it has to be in the public include directory. Move it.

Fixes: 84fcf3c15111 ("hw/riscv: Move sifive_plic model to hw/intc")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1602578033-68384-1-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ace544532c4064e995ef69ec9dc93aad62e19988
      
https://github.com/qemu/qemu/commit/ace544532c4064e995ef69ec9dc93aad62e19988
  Author: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Fix update of hstatus.SPVP

When trapping from virt into HS mode, hstatus.SPVP was set to
the value of sstatus.SPP, as according to the specification both
flags should be set to the same value.
However, the assignment of SPVP takes place before SPP itself is
updated, which results in SPVP having an outdated value.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201013151054.396481-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4aeb9e26c219a85f465eb2cc7ef6939a3c71944f
      
https://github.com/qemu/qemu/commit/4aeb9e26c219a85f465eb2cc7ef6939a3c71944f
  Author: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt

The hstatus.GVA bit was not set if the faulting guest virtual address
was zero.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201013173054.451135-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa
      
https://github.com/qemu/qemu/commit/1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa
  Author: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Fix implementation of HLVX.WU instruction

The HLVX.WU instruction is supposed to read a machine word,
but prior to this change it read a byte instead.

Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv instructions")
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201013172223.443645-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 099be0358ee2cfb1cadf80d14297511215885219
      
https://github.com/qemu/qemu/commit/099be0358ee2cfb1cadf80d14297511215885219
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv: sifive_u: Allow specifying the CPU

Allow the user to specify the main application CPU for the sifive_u
machine.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 
b8412086c8aea0eff30fb7a17f0acf2943381b6a.1602634524.git.alistair.francis@wdc.com


  Commit: e66c531e13f8ba3d8b7f32719f7964ba1b185a23
      
https://github.com/qemu/qemu/commit/e66c531e13f8ba3d8b7f32719f7964ba1b185a23
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M hw/riscv/boot.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: Return the end address of the loaded firmware

Instead of returning the unused entry address from riscv_load_firmware()
instead return the end address. Also return the end address from
riscv_find_and_load_firmware().

This tells the caller if a firmware was loaded and how big it is. This
can be used to determine the load address of the next image (usually the
kernel).

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 
558cf67162342d65a23262248b040563716628b2.1602634524.git.alistair.francis@wdc.com


  Commit: c40778429157afbd9ba2236f1e06ca24d980cdfe
      
https://github.com/qemu/qemu/commit/c40778429157afbd9ba2236f1e06ca24d980cdfe
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M hw/riscv/boot.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: Add a riscv_is_32_bit() function

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 
4c6a85dfb6dd470aa79356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com


  Commit: 38bc4e34f29b913d28a8d2abcf2bf74a4a4a816e
      
https://github.com/qemu/qemu/commit/38bc4e34f29b913d28a8d2abcf2bf74a4a4a816e
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: Load the kernel after the firmware

Instead of loading the kernel at a hardcoded start address, let's load
the kernel at the next aligned address after the end of the firmware.

This should have no impact for current users of OpenSBI, but will
allow loading a noMMU kernel at the start of memory.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 
46c00c4f15b42feb792090e3d74359e180a6d954.1602634524.git.alistair.francis@wdc.com


  Commit: 33a9a57d2c31ec9ed68858911dc490b5de15f342
      
https://github.com/qemu/qemu/commit/33a9a57d2c31ec9ed68858911dc490b5de15f342
  Author: Yifei Jiang <jiangyifei@huawei.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: raise exception to HS-mode at get_physical_address

VS-stage translation at get_physical_address needs to translate pte
address by G-stage translation. But the G-stage translation error
can not be distinguished from VS-stage translation error in
riscv_cpu_tlb_fill. On migration, destination needs to rebuild pte,
and this G-stage translation error must be handled by HS-mode. So
introduce TRANSLATE_STAGE2_FAIL so that riscv_cpu_tlb_fill could
distinguish and raise it to HS-mode.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201014101728.848-1-jiangyifei@huawei.com
[ Change by AF:
 - Clarify the fault_pte_addr shift
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a54d259157e2575b69e2cf7cf03592c74559cb7e
      
https://github.com/qemu/qemu/commit/a54d259157e2575b69e2cf7cf03592c74559cb7e
  Author: Green Wan <green.wan@sifive.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M hw/misc/sifive_u_otp.c
    M include/hw/misc/sifive_u_otp.h

  Log Message:
  -----------
  hw/misc/sifive_u_otp: Add write function and write-once protection

 - Add write operation to update fuse data bit when PWE bit is on.
 - Add array, fuse_wo, to store the 'written' status for all bits
   of OTP to block the write operation.

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20201020033732.12921-2-green.wan@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 51b6c1bbc3dd1b139a9e9b021d87bcfd7d82299e
      
https://github.com/qemu/qemu/commit/51b6c1bbc3dd1b139a9e9b021d87bcfd7d82299e
  Author: Green Wan <green.wan@sifive.com>
  Date:   2020-10-22 (Thu, 22 Oct 2020)

  Changed paths:
    M hw/misc/sifive_u_otp.c
    M include/hw/misc/sifive_u_otp.h

  Log Message:
  -----------
  hw/misc/sifive_u_otp: Add backend drive support

Add '-drive' support to OTP device. Allow users to assign a raw file
as OTP image.

test commands for 16k otp.img filled with zero:

$ dd if=/dev/zero of=./otp.img bs=1k count=16
$ ./qemu-system-riscv64 -M sifive_u -m 256M -nographic -bios none \
-kernel ../opensbi/build/platform/sifive/fu540/firmware/fw_payload.elf \
-d guest_errors -drive if=none,format=raw,file=otp.img

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201020033732.12921-3-green.wan@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 288a1cc6345ed0b04e0dc887905ebeef17141608
      
https://github.com/qemu/qemu/commit/288a1cc6345ed0b04e0dc887905ebeef17141608
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-10-26 (Mon, 26 Oct 2020)

  Changed paths:
    R hw/intc/sifive_plic.h
    M hw/misc/sifive_u_otp.c
    M hw/riscv/boot.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    A include/hw/intc/sifive_plic.h
    M include/hw/misc/sifive_u_otp.h
    M include/hw/riscv/boot.h
    M include/hw/riscv/sifive_u.h
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20201023' into staging

A collection of RISC-V fixes for the next QEMU release.

This includes:
 - Improvements to logging output
 - Hypervisor instruction fixups
 - The ability to load a noMMU kernel
 - SiFive OTP support

# gpg: Signature made Fri 23 Oct 2020 16:13:57 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20201023:
  hw/misc/sifive_u_otp: Add backend drive support
  hw/misc/sifive_u_otp: Add write function and write-once protection
  target/riscv: raise exception to HS-mode at get_physical_address
  hw/riscv: Load the kernel after the firmware
  hw/riscv: Add a riscv_is_32_bit() function
  hw/riscv: Return the end address of the loaded firmware
  hw/riscv: sifive_u: Allow specifying the CPU
  target/riscv: Fix implementation of HLVX.WU instruction
  target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt
  target/riscv: Fix update of hstatus.SPVP
  hw/intc: Move sifive_plic.h to the include directory
  riscv: Convert interrupt logs to use qemu_log_mask()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/a5fac424c76d...288a1cc6345e