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[Qemu-commits] [qemu/qemu] 709616: util/cutils: Introduce freq_to_str()
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] 709616: util/cutils: Introduce freq_to_str() to display He... |
Date: |
Tue, 20 Oct 2020 13:41:00 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 709616c713f9471a993ad7d16bce23e8b88ce958
https://github.com/qemu/qemu/commit/709616c713f9471a993ad7d16bce23e8b88ce958
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-16 (Fri, 16 Oct 2020)
Changed paths:
M include/qemu/cutils.h
M util/cutils.c
Log Message:
-----------
util/cutils: Introduce freq_to_str() to display Hertz units
Introduce freq_to_str() to convert frequency values in human
friendly units using the SI units for Hertz.
Suggested-by: Luc Michel <luc@lmichel.fr>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-Id: <20201012095804.3335117-2-f4bug@amsat.org>
Commit: 01d858629eae532f50f3dac6df9e6ab912626e00
https://github.com/qemu/qemu/commit/01d858629eae532f50f3dac6df9e6ab912626e00
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-16 (Fri, 16 Oct 2020)
Changed paths:
M hw/core/qdev-clock.c
Log Message:
-----------
hw/qdev-clock: Display error hint when clock is missing from device
Instead of directly aborting, display a hint to help the developer
figure out the problem (likely trying to connect a clock to a device
pre-dating the Clock API, thus not expecting clocks).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <20201012095804.3335117-4-f4bug@amsat.org>
Commit: 5ebc664800b66f886f58cd4d5bcc7785644c9980
https://github.com/qemu/qemu/commit/5ebc664800b66f886f58cd4d5bcc7785644c9980
Author: Luc Michel <luc@lmichel.fr>
Date: 2020-10-16 (Fri, 16 Oct 2020)
Changed paths:
M hw/core/clock.c
M include/hw/clock.h
Log Message:
-----------
hw/core/clock: Add the clock_new helper function
This function creates a clock and parents it to another object with a
given name. It calls clock_setup_canonical_path before returning the
new clock.
This function is useful to create clocks in devices when one doesn't
want to expose it at the qdev level (as an input or an output).
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201010135759.437903-4-luc@lmichel.fr>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 8cdf88690dc79511cfa1b2557434c09e3685f090
https://github.com/qemu/qemu/commit/8cdf88690dc79511cfa1b2557434c09e3685f090
Author: zhaolichang <zhaolichang@huawei.com>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/internal.h
M target/mips/translate.c
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Fix some comment spelling errors
There are many spelling errors in the comments in target/mips/.
Use spellcheck to check the spelling errors.
Signed-off-by: zhaolichang <zhaolichang@huawei.com>
Reviewed-by: David Edmondson <david.edmondson@oracle.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201009064449.2336-7-zhaolichang@huawei.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 8a6c9e0fdd10dce2240b2058fdedc5557e36adbd
https://github.com/qemu/qemu/commit/8a6c9e0fdd10dce2240b2058fdedc5557e36adbd
Author: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/fpu_helper.c
Log Message:
-----------
target/mips: Demacro helpers for <ABS|CHS>.<D|S|PS>
Remove function definitions via macros to achieve better code clarity.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1602103041-32017-2-git-send-email-aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: be0cb99426badb2fa0b02404144b2b80ac82f4c9
https://github.com/qemu/qemu/commit/be0cb99426badb2fa0b02404144b2b80ac82f4c9
Author: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/fpu_helper.c
Log Message:
-----------
target/mips: Demacro helpers for M<ADD|SUB>F.<D|S>
Remove function definitions via macros to achieve better code clarity.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1602103041-32017-3-git-send-email-aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 32eb97b5eb24c1fc1a1c366f25e1ffe31f0e096a
https://github.com/qemu/qemu/commit/32eb97b5eb24c1fc1a1c366f25e1ffe31f0e096a
Author: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/fpu_helper.c
Log Message:
-----------
target/mips: Demacro helpers for <MAX|MAXA|MIN|MINA>.<D|S>
Remove function definitions via macros to achieve better code clarity.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1602103041-32017-4-git-send-email-aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: e10a0ca17dfeac25afb58f163b99d784b88d4e23
https://github.com/qemu/qemu/commit/e10a0ca17dfeac25afb58f163b99d784b88d4e23
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add loongson-ext lswc2 group of instructions (Part 1)
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslq: load 16 bytes to GPR
gssq: store 16 bytes from GPR
gslqc1: load 16 bytes to FPR
gssqc1: store 16 bytes from FPR
Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <1602831120-3377-3-git-send-email-chenhc@lemote.com>
[PMD: Restrict t1 variable to TARGET_MIPS64, remove unused t2/fp0]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: fd723105c15e09b8a9eaad29fa59347e63cfdb20
https://github.com/qemu/qemu/commit/fd723105c15e09b8a9eaad29fa59347e63cfdb20
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add loongson-ext lswc2 group of instructions (Part 2)
LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE
as "load/store quad word" and "shifted load/store" groups of
instructions.
This patch add implementation of these instructions:
gslwlc1: similar to lwl but RT is FPR instead of GPR
gslwrc1: similar to lwr but RT is FPR instead of GPR
gsldlc1: similar to ldl but RT is FPR instead of GPR
gsldrc1: similar to ldr but RT is FPR instead of GPR
gsswlc1: similar to swl but RT is FPR instead of GPR
gsswrc1: similar to swr but RT is FPR instead of GPR
gssdlc1: similar to sdl but RT is FPR instead of GPR
gssdrc1: similar to sdr but RT is FPR instead of GPR
Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <1602831120-3377-4-git-send-email-chenhc@lemote.com>
[PMD: Reuse t1 on MIPS32, reintroduce t2/fp0]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 90e22a57af975dea08b3015dfac072709f131616
https://github.com/qemu/qemu/commit/90e22a57af975dea08b3015dfac072709f131616
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add loongson-ext lsdc2 group of instructions
LDC2/SDC2 opcodes have been rewritten as "load & store with offset"
group of instructions by loongson-ext ASE.
This patch add implementation of these instructions:
gslbx: load 1 bytes to GPR
gslhx: load 2 bytes to GPR
gslwx: load 4 bytes to GPR
gsldx: load 8 bytes to GPR
gslwxc1: load 4 bytes to FPR
gsldxc1: load 8 bytes to FPR
gssbx: store 1 bytes from GPR
gsshx: store 2 bytes from GPR
gsswx: store 4 bytes from GPR
gssdx: store 8 bytes from GPR
gsswxc1: store 4 bytes from FPR
gssdxc1: store 8 bytes from FPR
Details of Loongson-EXT is here:
https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1602831120-3377-5-git-send-email-chenhc@lemote.com>
Commit: 4a367cfb00d3779f0113f871e4b7cb550d068098
https://github.com/qemu/qemu/commit/4a367cfb00d3779f0113f871e4b7cb550d068098
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/op_helper.c
Log Message:
-----------
target/mips/op_helper: Convert multiple if() to switch case
The cache operation is encoded in bits [20:18] of the instruction.
The 'op' argument of helper_cache() contains the bits [20:16].
Extract the 3 bits and parse them using a switch case. This allow
us to handle multiple cache types (the cache type is encoded in
bits [17:16]).
Previously the if() block was only checking the D-Cache (Primary
Data or Unified Primary). Now we also handle the I-Cache (Primary
Instruction), S-Cache (Secondary) and T-Cache (Terciary).
Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20200813181527.22551-2-f4bug@amsat.org>
Commit: 45964263e42b9728dd206936c157bfd1bdb6918a
https://github.com/qemu/qemu/commit/45964263e42b9728dd206936c157bfd1bdb6918a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/op_helper.c
Log Message:
-----------
target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op
QEMU does not model caches, so there is not much to do with the
Invalidate/Writeback opcodes. Make it explicit adding a comment.
Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20200813181527.22551-3-f4bug@amsat.org>
Commit: 88a844545e0fb1fa95a55888fb31024fcfc9720b
https://github.com/qemu/qemu/commit/88a844545e0fb1fa95a55888fb31024fcfc9720b
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/op_helper.c
Log Message:
-----------
target/mips/op_helper: Log unimplemented cache opcode
In case the guest uses a cache opcode we are not expecting,
log it to give us a chance to notice it, in case we should
actually do something.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20200813181527.22551-4-f4bug@amsat.org>
Commit: 2dc29222a6f7c87300c1a7e1982e11422d34595e
https://github.com/qemu/qemu/commit/2dc29222a6f7c87300c1a7e1982e11422d34595e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/cp0_helper.c
M target/mips/cp0_timer.c
M target/mips/internal.h
Log Message:
-----------
target/mips: Move cpu_mips_get_random() with CP0 helpers
The get_random() helper uses the CP0_Wired register, which is
unrelated to the CP0_Count register used as timer.
Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file")
incorrectly moved this get_random() helper with timer specific
code. Move it back to generic CP0 helpers.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-Id: <20201012095804.3335117-6-f4bug@amsat.org>
Commit: 62f8f2603da7fbcc481489d2903558001a896cad
https://github.com/qemu/qemu/commit/62f8f2603da7fbcc481489d2903558001a896cad
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/cp0_timer.c
Log Message:
-----------
target/mips/cp0_timer: Explicit unit in variable name
Name variables holding nanoseconds with the '_ns' suffix.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20201012095804.3335117-7-f4bug@amsat.org>
Commit: 8dadffc01700f79fd66db972fff3a93a594715ee
https://github.com/qemu/qemu/commit/8dadffc01700f79fd66db972fff3a93a594715ee
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/cp0_timer.c
Log Message:
-----------
target/mips/cp0_timer: Document TIMER_PERIOD origin
TIMER_PERIOD value of '10 ns' can be explained looking at
commit 6af0bf9c7c3doc, where the CPU frequency is 200 MHz
and CP0 default count rate is half the frequency of the
CPU. Document that.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-8-f4bug@amsat.org>
Commit: d225b5122029c3d6293aab6e2d0a05597fc92ba4
https://github.com/qemu/qemu/commit/d225b5122029c3d6293aab6e2d0a05597fc92ba4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/cp0_timer.c
M target/mips/cpu.c
M target/mips/cpu.h
Log Message:
-----------
target/mips: Move cp0_count_ns to CPUMIPSState
Currently the CP0 timer period is fixed at 10 ns, corresponding
to a fixed CPU frequency of 200 MHz (using half the speed of the
CPU).
In few commits we will be able to use a different CPU frequency.
In preparation, move the cp0_count_ns variable to CPUMIPSState
so we can modify it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-9-f4bug@amsat.org>
Commit: 68b981aa76079216f5765a6aecaf8728f27d3696
https://github.com/qemu/qemu/commit/68b981aa76079216f5765a6aecaf8728f27d3696
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/cpu.c
Log Message:
-----------
target/mips/cpu: Calculate the CP0 timer period using the CPU frequency
The CP0 timer period is a function of the CPU frequency.
Start using the default values, which will be replaced by
properties in the next commits.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-10-f4bug@amsat.org>
Commit: d0bec217ee0f6c948ba4579ca0f43a1a3f346cb4
https://github.com/qemu/qemu/commit/d0bec217ee0f6c948ba4579ca0f43a1a3f346cb4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/cpu.c
M target/mips/cpu.h
Log Message:
-----------
target/mips/cpu: Make cp0_count_rate a property
Since not all CPU implementations use a cores use a CP0 timer
at half the frequency of the CPU, make this variable a property.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-11-f4bug@amsat.org>
Commit: a0713e85bfaec4d787b978640096322716938a56
https://github.com/qemu/qemu/commit/a0713e85bfaec4d787b978640096322716938a56
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/cpu.c
M target/mips/cpu.h
Log Message:
-----------
target/mips/cpu: Allow the CPU to use dynamic frequencies
Use the Clock API and let the CPU object have an input clock.
If no clock is connected, keep using the default frequency of
200 MHz used since the introduction of the 'r4k' machine in
commit 6af0bf9c7c3.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-12-f4bug@amsat.org>
Commit: 7aaab96a9b1c37f473f73363ff815eb059a2f823
https://github.com/qemu/qemu/commit/7aaab96a9b1c37f473f73363ff815eb059a2f823
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/cpu.c
M target/mips/cpu.h
Log Message:
-----------
target/mips/cpu: Introduce mips_cpu_create_with_clock() helper
Introduce an helper to create a MIPS CPU and connect it to
a reference clock. This helper is not MIPS specific, but so
far only MIPS CPUs need it.
Suggested-by: Huacai Chen <zltjiangshi@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-13-f4bug@amsat.org>
Commit: dccf092d67e05c76fe47ed92cab0aa59e77c6e08
https://github.com/qemu/qemu/commit/dccf092d67e05c76fe47ed92cab0aa59e77c6e08
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/r4k.c
Log Message:
-----------
hw/mips/r4k: Explicit CPU frequency is 200 MHz
Since its introduction in commit 6af0bf9c7c3,
the 'r4k' machine runs at 200 MHz.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-14-f4bug@amsat.org>
Commit: 3ca7639ff0077ef1869c88523360c017defecaad
https://github.com/qemu/qemu/commit/3ca7639ff0077ef1869c88523360c017defecaad
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/fuloong2e.c
Log Message:
-----------
hw/mips/fuloong2e: Set CPU frequency to 533 MHz
The CPU frequency is normally provided by the firmware in the
"cpuclock" environment variable. The 2E board can handles up
to 660MHz, but be conservative and take the same value used
by the Linux kernel: 533 MHz.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201012095804.3335117-15-f4bug@amsat.org>
Commit: 8543a806912da7cdbc45303226762372f92f689b
https://github.com/qemu/qemu/commit/8543a806912da7cdbc45303226762372f92f689b
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/mipssim.c
Log Message:
-----------
hw/mips/mipssim: Correct CPU frequency
The MIPSsim machine CPU frequency is too fast running at 200 MHz,
while it should be 12 MHz for the 24K and 6 MHz for the 5K core.
Ref: Linux commit c78cbf49c4ed
("Support for MIPSsim, the cycle accurate MIPS simulator.")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-16-f4bug@amsat.org>
Commit: 79b99fe3f09979b6ba0a8d9f4603dc43e7e066c4
https://github.com/qemu/qemu/commit/79b99fe3f09979b6ba0a8d9f4603dc43e7e066c4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/jazz.c
Log Message:
-----------
hw/mips/jazz: Correct CPU frequencies
The Magnum 4000PC CPU runs at 100 MHz, and the Acer PICA-61
CPU at ~134 MHz.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-17-f4bug@amsat.org>
Commit: e8373c56531cec8eb48743f261e8b216bcda589a
https://github.com/qemu/qemu/commit/e8373c56531cec8eb48743f261e8b216bcda589a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/cps.c
M include/hw/mips/cps.h
Log Message:
-----------
hw/mips/cps: Expose input clock and connect it to CPU cores
Expose a qdev input clock named 'clk-in', and connect it to each
core to forward-propagate the clock.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-18-f4bug@amsat.org>
Commit: 6b290b41cb533b93548248846e0e320af0a419ed
https://github.com/qemu/qemu/commit/6b290b41cb533b93548248846e0e320af0a419ed
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/boston.c
Log Message:
-----------
hw/mips/boston: Set CPU frequency to 1 GHz
The I6400 can run at 1 GHz or more. Create a 'cpuclk'
output clock and connect it to the CPU input clock.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-19-f4bug@amsat.org>
Commit: eea1f5bac6f7ea71ef357bb8166512ef759a7b32
https://github.com/qemu/qemu/commit/eea1f5bac6f7ea71ef357bb8166512ef759a7b32
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Set CPU frequency to 320 MHz
The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create
a 'cpuclk' output clock and connect it to the CPU input clock.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-20-f4bug@amsat.org>
Commit: ba25670c1d3e122bfa5a43cd785f5eb4988861d9
https://github.com/qemu/qemu/commit/ba25670c1d3e122bfa5a43cd785f5eb4988861d9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/cps.c
Log Message:
-----------
hw/mips/cps: Do not allow use without input clock
Now than all QOM users provides the input clock, do not allow
using a CPS without input clock connected.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-21-f4bug@amsat.org>
Commit: 8a6359f937632d4b47bfaf0640c5acbf73736521
https://github.com/qemu/qemu/commit/8a6359f937632d4b47bfaf0640c5acbf73736521
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/cpu.c
Log Message:
-----------
target/mips/cpu: Display warning when CPU is used without input clock
All our QOM users provides an input clock. In order to avoid
avoid future machines added without clock, display a warning.
User-mode emulation use the CP0 timer with the RDHWR instruction
(see commit cdfcad788394) so keep using the fixed 200 MHz clock
without diplaying any warning. Only display it in system-mode
emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-22-f4bug@amsat.org>
Commit: 9a2133f45c287e99ef23896a7a33b3d2dbfe97fd
https://github.com/qemu/qemu/commit/9a2133f45c287e99ef23896a7a33b3d2dbfe97fd
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Fix FPGA I/O region size
The FPGA present on the CoreCard has an I/O region 1MiB wide.
Refs:
- Atlas User’s Manual (Document Number: MD00005)
- Malta User’s Manual (Document Number: MD00048)
Fixes: ea85df72b60 ("mips_malta: convert to memory API")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200905213049.761949-1-f4bug@amsat.org>
Commit: c5cdf7561311a2dd37eb7af636247440182e6e0b
https://github.com/qemu/qemu/commit/c5cdf7561311a2dd37eb7af636247440182e6e0b
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Move gt64120 related code together
The 'empty_slot' region created is related to the gt64120.
Move its creation close to the gt64120 instance creation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201012160503.3472140-2-f4bug@amsat.org>
Commit: 8df525a558e85aee7a2c757dd7654173ef369544
https://github.com/qemu/qemu/commit/8df525a558e85aee7a2c757dd7654173ef369544
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Use clearer qdev style
In order to be consistent with the other code base uses,
rewrite slightly how the MIPS_MALTA object is created.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201012160503.3472140-3-f4bug@amsat.org>
Commit: 9d585eaa87bf1c5f66e12d6c4a8a38c80f69c5da
https://github.com/qemu/qemu/commit/9d585eaa87bf1c5f66e12d6c4a8a38c80f69c5da
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/mipssim.c
M hw/mips/r4k.c
Log Message:
-----------
hw/mips: Simplify loading 64-bit ELF kernels
Since 82790064116 ("Cast ELF datatypes properly to host 64bit types")
we don't need to sign-extend the entry_point address. Remove this
unnecessary code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200927163943.614604-2-f4bug@amsat.org>
Commit: acab36ca25101930b263dd9e8afd9b244354d338
https://github.com/qemu/qemu/commit/acab36ca25101930b263dd9e8afd9b244354d338
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/fuloong2e.c
M hw/mips/malta.c
M hw/mips/mipssim.c
M hw/mips/r4k.c
M include/hw/mips/mips.h
Log Message:
-----------
hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)
Instead of using a INITRD_PAGE_MASK definition, use the
simpler INITRD_PAGE_SIZE one which allows us to simplify
the code by using directly the self-explicit ROUND_UP()
macro.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200927163943.614604-3-f4bug@amsat.org>
Commit: 27cf0896bfd84a9ccb2cfe315952338f00aa086e
https://github.com/qemu/qemu/commit/27cf0896bfd84a9ccb2cfe315952338f00aa086e
Author: Eduardo Habkost <ehabkost@redhat.com>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/boston.c
Log Message:
-----------
hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON
This will make the type name constant consistent with the name of
the type checking macro.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200902224311.1321159-19-ehabkost@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: a4374f86dc648b6cf10a7c8c40bde33722e5b25d
https://github.com/qemu/qemu/commit/a4374f86dc648b6cf10a7c8c40bde33722e5b25d
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M hw/mips/fuloong2e.c
M hw/mips/jazz.c
M hw/mips/malta.c
M hw/mips/mipssim.c
Log Message:
-----------
hw/mips: Remove exit(1) in case of missing ROM
This patch updates MIPS-based machines to allow starting them without ROM.
In this case CPU starts to execute instructions from the empty memory,
but QEMU allows introspecting the machine configuration.
Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <159531210571.24117.231100997794891819.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 1d2ff14b72ed11d577cbe42a3fef9fcce522418a
https://github.com/qemu/qemu/commit/1d2ff14b72ed11d577cbe42a3fef9fcce522418a
Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M tests/acceptance/replay_kernel.py
Log Message:
-----------
tests/acceptance: Add MIPS record/replay tests
This patch adds MIPS-targeted acceptance tests for
record/replay functions.
Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <160276110297.2705.10918105269658307206.stgit@pasha-ThinkPad-X280>
[PMD: Moved 'override timeout' comment from instance to class,
moved nanomips tests to ReplayKernelSlow class,
tagged ReplayKernelSlow class with AVOCADO_TIMEOUT_EXPECTED]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: b5330cf19ad29a71c3981d315a14f17db539ec80
https://github.com/qemu/qemu/commit/b5330cf19ad29a71c3981d315a14f17db539ec80
Author: Huacai Chen <zltjiangshi@gmail.com>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M docs/system/cpu-models-mips.rst.inc
Log Message:
-----------
docs/system: Update MIPS CPU documentation
Add Loongson-3A CPU models description.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <1602059975-10115-10-git-send-email-chenhc@lemote.com>
[PMD: Split patch in 2: CPU / machine]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: ca263c0fb9f33cc746e6e3d968b7db80072ecf86
https://github.com/qemu/qemu/commit/ca263c0fb9f33cc746e6e3d968b7db80072ecf86
Author: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Remove myself
I have been working on project other than QEMU for some time, and would
like to devote myself to that project. It is impossible for me to find
enough time to perform maintainer's duties with needed meticulousness
and patience.
I wish prosperous future to QEMU and all colleagues in QEMU community.
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1602103041-32017-6-git-send-email-aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: cf960317cb644c772610c1a275a88635af4a40d9
https://github.com/qemu/qemu/commit/cf960317cb644c772610c1a275a88635af4a40d9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Put myself forward for MIPS target
To avoid the MIPS target being orphan, volunteer to keep an eye
on it and put together pull requests.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20201013101659.3557154-2-f4bug@amsat.org>
Commit: 4ba98e96e0d1cf8c6188a3169fbb2e1f08838a63
https://github.com/qemu/qemu/commit/4ba98e96e0d1cf8c6188a3169fbb2e1f08838a63
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton mail
Paul's Wavecomp email has been bouncing for months. He told us
he "no longer has access to modern MIPS CPUs or Boston hardware,
and wouldn't currently have time to spend on them if he did." [1]
but "perhaps that might change in the future." [2].
Be fair and downgrade the status of the Boston board to "Odd Fixes"
(has a maintainer but they don't have time to do much other).
Similarly to commit 2b107c2c1c (".mailmap: Update Paul Burton email
address"), update his email address here too.
[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg718739.html
[2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg728605.html
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20201013101659.3557154-4-f4bug@amsat.org>
Commit: 5ca2b252692761e9c7bea60634d3ecca96be0599
https://github.com/qemu/qemu/commit/5ca2b252692761e9c7bea60634d3ecca96be0599
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Remove duplicated Malta test entries
The Malta tests are already covered in the Malta section.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20201013101659.3557154-3-f4bug@amsat.org>
Commit: 68fa519a6cb455005317bd61f95214b58b2f1e69
https://github.com/qemu/qemu/commit/68fa519a6cb455005317bd61f95214b58b2f1e69
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-17 (Sat, 17 Oct 2020)
Changed paths:
M target/mips/translate_init.c.inc
Log Message:
-----------
target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)
Per "MIPS32 34K Processor Core Family Software User's Manual,
Revision 01.13" page 8 in "Joint TLB (JTLB)" section:
"The JTLB is a fully associative TLB cache containing 16, 32,
or 64-dual-entries mapping up to 128 virtual pages to their
corresponding physical addresses."
There is no particular reason to restrict the 34Kf core model to
16 TLB entries, so raise its config to 64.
This is helpful for other projects, in particular the Yocto Project:
Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit
MIPS CI loop. It was observed that in this case CI test execution
time was almost twice longer than 64bit MIPS variant that runs
under MIPS64R2-generic model. It was investigated and concluded
that the difference in number of TLBs 16 in 34Kf case vs 64 in
MIPS64R2-generic is responsible for most of CI real time execution
difference. Because with 16 TLBs linux user-land trashes TLB more
and it needs to execute more instructions in TLB refill handler
calls, as result it runs much longer.
(https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html)
Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992
Reported-by: Victor Kamensky <kamensky@cisco.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201016133317.553068-1-f4bug@amsat.org>
Commit: 348b8d1a76b4ab4b5a9ec756500547c5f2756d9c
https://github.com/qemu/qemu/commit/348b8d1a76b4ab4b5a9ec756500547c5f2756d9c
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2020-10-18 (Sun, 18 Oct 2020)
Changed paths:
M hw/misc/macio/macio.c
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
Log Message:
-----------
macio: don't reference serial_hd() directly within the device
Instead use qdev_prop_set_chr() to configure the ESCC serial chardevs at the
Mac Old World and New World machine level.
Also remove the now obsolete comment referring to the use of serial_hd() and
the setting of user_creatable to false accordingly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201013114922.2946-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: b950914df3a2a936d4eca00eeb4ca0254423d265
https://github.com/qemu/qemu/commit/b950914df3a2a936d4eca00eeb4ca0254423d265
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2020-10-18 (Sun, 18 Oct 2020)
Changed paths:
M hw/pci-host/grackle.c
M hw/ppc/mac_oldworld.c
Log Message:
-----------
grackle: use qdev gpios for PCI IRQs
Currently an object link property is used to pass a reference to the Heathrow
PIC into the PCI host bridge so that grackle_init_irqs() can connect the PCI
IRQs to the PIC itself.
This can be simplified by defining the PCI IRQs as qdev gpios and then wiring
up the PCI IRQs to the PIC in the Old World machine init function.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201013114922.2946-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 40a0deb74bf433d5fce2cc882a61e4c9c479e9f9
https://github.com/qemu/qemu/commit/40a0deb74bf433d5fce2cc882a61e4c9c479e9f9
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2020-10-18 (Sun, 18 Oct 2020)
Changed paths:
M hw/pci-host/uninorth.c
M hw/ppc/mac_newworld.c
M include/hw/pci-host/uninorth.h
Log Message:
-----------
uninorth: use qdev gpios for PCI IRQs
Currently an object link property is used to pass a reference to the OpenPIC
into the PCI host bridge so that pci_unin_init_irqs() can connect the PCI
IRQs to the PIC itself.
This can be simplified by defining the PCI IRQs as qdev gpios and then wiring
up the PCI IRQs to the PIC in the New World machine init function.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201013114922.2946-4-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 669b96484caab266f71625426b4983d31e490f96
https://github.com/qemu/qemu/commit/669b96484caab266f71625426b4983d31e490f96
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2020-10-18 (Sun, 18 Oct 2020)
Changed paths:
M hw/rtc/m48t59-isa.c
M include/hw/rtc/m48t59.h
Log Message:
-----------
m48t59-isa: remove legacy m48t59_init_isa() function
This function is no longer used within the codebase.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201016182739.22875-2-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: cb0fa36b31d15ab862517b4150d85d885f38ae35
https://github.com/qemu/qemu/commit/cb0fa36b31d15ab862517b4150d85d885f38ae35
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2020-10-18 (Sun, 18 Oct 2020)
Changed paths:
M hw/sparc/sun4m.c
Log Message:
-----------
sun4m: use qdev properties instead of legacy m48t59_init() function
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201016182739.22875-3-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: dc7a05da69613d5c87ec0359c5dbb9d2b4765301
https://github.com/qemu/qemu/commit/dc7a05da69613d5c87ec0359c5dbb9d2b4765301
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2020-10-18 (Sun, 18 Oct 2020)
Changed paths:
M hw/sparc64/sun4u.c
Log Message:
-----------
sun4u: use qdev properties instead of legacy m48t59_init() function
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201016182739.22875-4-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: e8a02431ecd5b5e72fb471b01880252bcc0613cb
https://github.com/qemu/qemu/commit/e8a02431ecd5b5e72fb471b01880252bcc0613cb
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2020-10-18 (Sun, 18 Oct 2020)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc405_boards: use qdev properties instead of legacy m48t59_init() function
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201016182739.22875-5-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 3e7e134d827790c3714cae1d5b8aff8612000116
https://github.com/qemu/qemu/commit/3e7e134d827790c3714cae1d5b8aff8612000116
Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: 2020-10-18 (Sun, 18 Oct 2020)
Changed paths:
M hw/rtc/m48t59.c
M include/hw/rtc/m48t59.h
Log Message:
-----------
m48t59: remove legacy m48t59_init() function
Now that all of the callers of this function have been switched to use qdev
properties, this legacy init function can now be removed.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201016182739.22875-6-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 464c73e8eb0f52b5644768c095e553cf97cb041b
https://github.com/qemu/qemu/commit/464c73e8eb0f52b5644768c095e553cf97cb041b
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/ppc/mac_oldworld.c
Log Message:
-----------
mac_oldworld: Allow loading binary ROM image
The beige G3 Power Macintosh has a 4MB firmware ROM. Fix the size of
the rom region and fall back to loading a binary image with -bios if
loading ELF image failed. This allows testing emulation with a ROM
image from real hardware as well as using an ELF OpenBIOS image.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201017155139.5A36A746331@zero.eik.bme.hu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 31a6f3534aba275aa9b3da21a58e79065ba865b5
https://github.com/qemu/qemu/commit/31a6f3534aba275aa9b3da21a58e79065ba865b5
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
Log Message:
-----------
mac_newworld: Allow loading binary ROM image
Fall back to load binary ROM image if loading ELF fails. This also
moves PROM_BASE and PROM_SIZE defines to board as these are matching
the ROM size and address on this board and removes the now unused
PROM_ADDR and BIOS_SIZE defines from common mac.h.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<4d58ffe7645a0c746c8fed6aa8775c0867b624e0.1602805637.git.balaton@eik.bme.hu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: c3481ab096f35d7fa1c2945b05e22bef280b235b
https://github.com/qemu/qemu/commit/c3481ab096f35d7fa1c2945b05e22bef280b235b
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/ppc/mac_oldworld.c
Log Message:
-----------
mac_oldworld: Drop a variable, use get_system_memory() directly
Half of the occurances already use get_system_memory() directly
instead of sysmem variable, convert the two other uses to
get_system_memory() too which seems to be more common and drop the
variable.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<b4c714e03690deb6f94f80f7a5b2af47d90550ae.1602805637.git.balaton@eik.bme.hu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: b8df32555ce5bdae268e7bcc5b6c647c63c32373
https://github.com/qemu/qemu/commit/b8df32555ce5bdae268e7bcc5b6c647c63c32373
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/ppc/mac_oldworld.c
Log Message:
-----------
mac_oldworld: Drop some variables
Values not used frequently enough may not worth putting in a local
variable, especially with names almost as long as the original value
because that does not improve readability, to the contrary it makes it
harder to see what value is used. Drop a few such variables.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<d67bc8d914a366ca6822b5190c1308d31af5c9b3.1602805637.git.balaton@eik.bme.hu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: bb997e5c967b3b6f19f1461811df6317ed37c5ff
https://github.com/qemu/qemu/commit/bb997e5c967b3b6f19f1461811df6317ed37c5ff
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/ppc/mac_oldworld.c
Log Message:
-----------
mac_oldworld: Change PCI address of macio to match real hardware
The board firmware expect these to be at fixed addresses and programs
them without probing, this patch puts the macio device at the expected
PCI address.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id:
<f14bcaf3cf129500710ba5289980a134086bd949.1602805637.git.balaton@eik.bme.hu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit: 69958d8a3d9535f43a457044b2b277c3c6a5ef3d
https://github.com/qemu/qemu/commit/69958d8a3d9535f43a457044b2b277c3c6a5ef3d
Author: Paul Zimmerman <pauldzim@gmail.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/usb/hcd-dwc2.c
Log Message:
-----------
usb: hcd-dwc2: change assert()s to qemu_log_mask(LOG_GUEST_ERROR...)
Change several assert()s to qemu_log_mask(LOG_GUEST_ERROR...),
to prevent the guest from causing Qemu to assert. Also fix up
several existing qemu_log_mask()s to include the function name in
the message.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200920021449.830-1-pauldzim@gmail.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Commit: ccee80c68db14b3e965582a19393992b5c2b97f4
https://github.com/qemu/qemu/commit/ccee80c68db14b3e965582a19393992b5c2b97f4
Author: Anthony PERARD <anthony.perard@citrix.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/usb/hcd-ehci.c
Log Message:
-----------
usb/hcd-ehci: Fix error handling on missing device for iTD
The EHCI Host Controller emulation attempt to locate the device
associated with a periodic isochronous transfer description (iTD) and
when this fail the host controller is reset.
But according the EHCI spec 1.0 section 5.15.2.4 Host System
Error, the host controller is supposed to reset itself only when it
failed to communicate with the Host (Operating System), like when
there's an error on the PCI bus. If a transaction fails, there's
nothing in the spec that say to reset the host controller.
This patch rework the error path so that the host controller can keep
working when the OS setup a bogus transaction, it also revert to the
behavior of the EHCI emulation to before commits:
e94682f1fe ("ehci: check device is not NULL before calling usb_ep_get()")
7011baece2 ("usb: remove unnecessary NULL device check from usb_ep_get()")
The issue has been found while trying to passthrough a USB device to a
Windows Server 2012 Xen guest via "usb-ehci", which prevent the USB
device from working in Windows. ("usb-ehci" alone works, windows only
setup this weird periodic iTD to device 127 endpoint 15 when the USB
device is passthrough.)
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Message-id: 20201014104106.2962640-1-anthony.perard@citrix.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Commit: bea2a9e3e00b275dc40cfa09c760c715b8753e03
https://github.com/qemu/qemu/commit/bea2a9e3e00b275dc40cfa09c760c715b8753e03
Author: Mauro Matteo Cascella <mcascell@redhat.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/usb/hcd-dwc2.c
Log Message:
-----------
hw/usb/hcd-dwc2: fix divide-by-zero in dwc2_handle_packet()
Check the value of mps to avoid potential divide-by-zero later in the function.
Since HCCHAR_MPS is guest controllable, this prevents a malicious/buggy guest
from crashing the QEMU process on the host.
Signed-off-by: Mauro Matteo Cascella <mcascell@redhat.com>
Reviewed-by: Paul Zimmerman <pauldzim@gmail.com>
Reported-by: Gaoning Pan <gaoning.pgn@antgroup.com>
Reported-by: Xingwei Lin <linyi.lxw@antfin.com>
Message-id: 20201015075957.268823-1-mcascell@redhat.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Commit: 22d30b340aa5d8a2b1fbc90d5263f801f1584d01
https://github.com/qemu/qemu/commit/22d30b340aa5d8a2b1fbc90d5263f801f1584d01
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M MAINTAINERS
M docs/system/cpu-models-mips.rst.inc
M hw/core/clock.c
M hw/core/qdev-clock.c
M hw/mips/boston.c
M hw/mips/cps.c
M hw/mips/fuloong2e.c
M hw/mips/jazz.c
M hw/mips/malta.c
M hw/mips/mipssim.c
M hw/mips/r4k.c
M include/hw/clock.h
M include/hw/mips/cps.h
M include/hw/mips/mips.h
M include/qemu/cutils.h
M target/mips/cp0_helper.c
M target/mips/cp0_timer.c
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/fpu_helper.c
M target/mips/internal.h
M target/mips/op_helper.c
M target/mips/translate.c
M target/mips/translate_init.c.inc
M tests/acceptance/replay_kernel.py
M util/cutils.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-next-20201017'
into staging
MIPS patches queue
. Fix some comment spelling errors
. Demacro some TCG helpers
. Add loongson-ext lswc2/lsdc2 group of instructions
. Log unimplemented cache opcode
. Increase number of TLB entries on the 34Kf core
. Allow the CPU to use dynamic frequencies
. Calculate the CP0 timer period using the CPU frequency
. Set CPU frequency for each machine
. Fix Malta FPGA I/O region size
. Allow running qtests when ROM is missing
. Add record/replay acceptance tests
. Update MIPS CPU documentation
. MAINTAINERS updates
CI jobs results:
https://gitlab.com/philmd/qemu/-/pipelines/203931842
https://travis-ci.org/github/philmd/qemu/builds/736491461
https://cirrus-ci.com/build/6272264062631936
https://app.shippable.com/github/philmd/qemu/runs/886/summary/console
# gpg: Signature made Sat 17 Oct 2020 14:59:53 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/mips-next-20201017: (44 commits)
target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)
MAINTAINERS: Remove duplicated Malta test entries
MAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton mail
MAINTAINERS: Put myself forward for MIPS target
MAINTAINERS: Remove myself
docs/system: Update MIPS CPU documentation
tests/acceptance: Add MIPS record/replay tests
hw/mips: Remove exit(1) in case of missing ROM
hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON
hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)
hw/mips: Simplify loading 64-bit ELF kernels
hw/mips/malta: Use clearer qdev style
hw/mips/malta: Move gt64120 related code together
hw/mips/malta: Fix FPGA I/O region size
target/mips/cpu: Display warning when CPU is used without input clock
hw/mips/cps: Do not allow use without input clock
hw/mips/malta: Set CPU frequency to 320 MHz
hw/mips/boston: Set CPU frequency to 1 GHz
hw/mips/cps: Expose input clock and connect it to CPU cores
hw/mips/jazz: Correct CPU frequencies
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ba2a9a9e6318bfd93a2306dec40137e198205b86
https://github.com/qemu/qemu/commit/ba2a9a9e6318bfd93a2306dec40137e198205b86
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/misc/macio/macio.c
M hw/pci-host/grackle.c
M hw/pci-host/uninorth.c
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
M hw/ppc/ppc405_boards.c
M hw/rtc/m48t59-isa.c
M hw/rtc/m48t59.c
M hw/sparc/sun4m.c
M hw/sparc64/sun4u.c
M include/hw/pci-host/uninorth.h
M include/hw/rtc/m48t59.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-macppc-20201019'
into staging
qemu-macppc updates
# gpg: Signature made Mon 19 Oct 2020 08:13:16 BST
# gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg: issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>"
[full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F
* remotes/mcayland/tags/qemu-macppc-20201019:
mac_oldworld: Change PCI address of macio to match real hardware
mac_oldworld: Drop some variables
mac_oldworld: Drop a variable, use get_system_memory() directly
mac_newworld: Allow loading binary ROM image
mac_oldworld: Allow loading binary ROM image
m48t59: remove legacy m48t59_init() function
ppc405_boards: use qdev properties instead of legacy m48t59_init() function
sun4u: use qdev properties instead of legacy m48t59_init() function
sun4m: use qdev properties instead of legacy m48t59_init() function
m48t59-isa: remove legacy m48t59_init_isa() function
uninorth: use qdev gpios for PCI IRQs
grackle: use qdev gpios for PCI IRQs
macio: don't reference serial_hd() directly within the device
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b036d9ac690943af93929ede376c4482c8f97bf2
https://github.com/qemu/qemu/commit/b036d9ac690943af93929ede376c4482c8f97bf2
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/9pfs/9p-synth.c
M hw/9pfs/virtio-9p-device.c
Log Message:
-----------
9pfs: suppress performance warnings on qtest runs
Don't trigger any performance warning if we're just running test cases,
because tests intentionally run for edge cases.
So far performance warnings were suppressed for the 'synth' fs driver
backend only. This patch suppresses them for all 9p fs driver backends.
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id:
<a2d2ff2163f8853ea782a7a1d4e6f2afd7c29ffe.1603106145.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Commit: eefd2394efd6ba379d36d80c52de9ad956343b47
https://github.com/qemu/qemu/commit/eefd2394efd6ba379d36d80c52de9ad956343b47
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M tests/qtest/virtio-9p-test.c
Log Message:
-----------
tests/9pfs: change qtest name prefix to synth
All existing 9pfs test cases are using the 'synth' fs driver so far, which
means they are not accessing real files, but a purely simulated (in RAM
only) file system.
Let's make this clear by changing the prefix of the individual qtest case
names from 'fs/' to 'synth/'. That way they'll be easily distinguishable
from upcoming new 9pfs test cases supposed to be using a different fs
driver.
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Message-Id:
<e04e75acb849b085c6d6320b2433a15fa935bcff.1602182956.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Commit: 3a565c641a5c50bd6d0cb4df881b607a279505f6
https://github.com/qemu/qemu/commit/3a565c641a5c50bd6d0cb4df881b607a279505f6
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M tests/qtest/libqos/virtio-9p.c
M tests/qtest/libqos/virtio-9p.h
M tests/qtest/virtio-9p-test.c
Log Message:
-----------
tests/9pfs: introduce local tests
This patch introduces 9pfs test cases using the 9pfs 'local'
filesystem driver which reads/writes/creates/deletes real files
and directories.
In this initial version, there is only one local test which actually
only checks if the 9pfs 'local' device was created successfully.
Before the 9pfs 'local' tests are run, a test directory 'qtest-9p-local'
is created (with world rwx permissions) under the current working
directory. At this point that test directory is not auto deleted yet.
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Message-Id:
<81fc4b3b6b6c9bf7999e79f5e7cbc364a5f09ddb.1602182956.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Commit: 051f0e5be12b2760d7fb2095b864b26ffe21f6de
https://github.com/qemu/qemu/commit/051f0e5be12b2760d7fb2095b864b26ffe21f6de
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M tests/qtest/libqos/virtio-9p.c
Log Message:
-----------
tests/9pfs: wipe local 9pfs test directory
Before running the first 9pfs test case, make sure the test directory
for running the 9pfs 'local' tests on is entirely empty. For that
reason simply delete the test directory (if any) before (re)creating
it on test suite startup.
Note: The preferable precise behaviour would be the test directory
only being wiped once *before* a test suite run. Right now the test
directory is also wiped at the *end* of a test suite run because
libqos is calling the virtio_9p_register_nodes() callback for some
reason also when a test suite completed. This is suboptimal as
developers cannot immediately see what files and directories the
9pfs local tests created precisely after the test suite completed.
But fortunately the test directory is not wiped if some test failed.
So it is probably not worth it drilling another hole into libqos
for this issue.
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Message-Id:
<b30776ea3289dc40dabc7d0063d825d21d9a65bf.1602182956.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Commit: e55b178b5e139fc1b951ac8f56e48db716909006
https://github.com/qemu/qemu/commit/e55b178b5e139fc1b951ac8f56e48db716909006
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M tests/qtest/libqos/virtio-9p.c
M tests/qtest/libqos/virtio-9p.h
Log Message:
-----------
tests/9pfs: add virtio_9p_test_path()
This new public function virtio_9p_test_path() allows 9pfs
'local' tests to translate a path from guest scope to host
scope. For instance by passing an empty string it would
return the root path on host of the exported 9pfs tree.
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Message-Id:
<b563d3c73c6391ec927a2622c9f65c09ca56bd83.1602182956.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Commit: 653daf38978d101d8810f96b9337ebc6b7b1423f
https://github.com/qemu/qemu/commit/653daf38978d101d8810f96b9337ebc6b7b1423f
Author: Christian Schoenebeck <qemu_oss@crudebyte.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M tests/qtest/virtio-9p-test.c
Log Message:
-----------
tests/9pfs: add local Tmkdir test
This test case uses the 9pfs 'local' driver to create a directory
and then checks if the expected directory was actually created
(as real directory) on host side.
This patch introduces a custom split() implementation, because
the test code requires non empty array elements as result. For
that reason g_strsplit() would not be a good alternative, as
it would require additional filter code for reshuffling the
array, and the resulting code would be even more complex than
this split() function.
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Message-Id:
<be342f236842272275f65dbe05587f0a5409ad77.1602182956.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Commit: 000f5b8f46f9a9f0a0d5304b605d89808ad92d4e
https://github.com/qemu/qemu/commit/000f5b8f46f9a9f0a0d5304b605d89808ad92d4e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/usb/hcd-dwc2.c
M hw/usb/hcd-ehci.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20201019-pull-request'
into staging
usb: fixes for dwc2 + ehci.
# gpg: Signature made Mon 19 Oct 2020 13:33:16 BST
# gpg: using RSA key 4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/usb-20201019-pull-request:
hw/usb/hcd-dwc2: fix divide-by-zero in dwc2_handle_packet()
usb/hcd-ehci: Fix error handling on missing device for iTD
usb: hcd-dwc2: change assert()s to qemu_log_mask(LOG_GUEST_ERROR...)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d76f4f97eb2772bf85fe286097183d0c7db19ae8
https://github.com/qemu/qemu/commit/d76f4f97eb2772bf85fe286097183d0c7db19ae8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/9pfs/9p-synth.c
M hw/9pfs/virtio-9p-device.c
M tests/qtest/libqos/virtio-9p.c
M tests/qtest/libqos/virtio-9p.h
M tests/qtest/virtio-9p-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201019'
into staging
9pfs: add tests using local fs driver
The currently existing 9pfs test cases are all solely using the 9pfs 'synth'
fileystem driver, which is a very simple and purely simulated (in RAM only)
filesystem. There are issues though where the 'synth' fs driver is not
sufficient. For example the following two bugs need test cases running the
9pfs 'local' fs driver:
https://bugs.launchpad.net/qemu/+bug/1336794
https://bugs.launchpad.net/qemu/+bug/1877384
This patch set for that reason introduces 9pfs test cases using the 9pfs
'local' filesystem driver along to the already existing tests on 'synth'.
# gpg: Signature made Mon 19 Oct 2020 13:39:08 BST
# gpg: using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395
# gpg: issuer "qemu_oss@crudebyte.com"
# gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: ECAB 1A45 4014 1413 BA38 4926 30DB 47C3 A012 D5F4
# Subkey fingerprint: 96D8 D110 CF7A F808 4F88 5901 34C2 B587 65A4 7395
* remotes/cschoenebeck/tags/pull-9p-20201019:
tests/9pfs: add local Tmkdir test
tests/9pfs: add virtio_9p_test_path()
tests/9pfs: wipe local 9pfs test directory
tests/9pfs: introduce local tests
tests/9pfs: change qtest name prefix to synth
9pfs: suppress performance warnings on qtest runs
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5b6a8f4392146c9c130cf510f780dbf5ba7f6046
https://github.com/qemu/qemu/commit/5b6a8f4392146c9c130cf510f780dbf5ba7f6046
Author: Michael Tokarev <mjt@tls.msk.ru>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M configure
M hw/i386/xen/xen_platform.c
Log Message:
-----------
xen: xenguest is not used so is not needed
There's no references in only file which includes xenguest.h
to any xen definitions. And there's no references to -lxenguest
in qemu, either. Drop it.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20200727140048.19779-1-mjt@msgid.tls.msk.ru>
[perard: rebased]
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Commit: 2211118a2acb6f36bc497713479050e45a3ec693
https://github.com/qemu/qemu/commit/2211118a2acb6f36bc497713479050e45a3ec693
Author: Eduardo Habkost <ehabkost@redhat.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M include/hw/xen/xen-legacy-backend.h
Log Message:
-----------
xen: Rename XENBACKEND_DEVICE to XENBACKEND
Make the type checking macro name consistent with the TYPE_*
constant.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20200902224311.1321159-58-ehabkost@redhat.com>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Commit: c4583c8c394ee49ce7d5271f572abd3b000fa9e4
https://github.com/qemu/qemu/commit/c4583c8c394ee49ce7d5271f572abd3b000fa9e4
Author: Paul Durrant <pdurrant@amazon.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/xen/xen-backend.c
M hw/xen/xen-bus.c
M include/hw/xen/xen-backend.h
M include/hw/xen/xen-bus.h
Log Message:
-----------
xen-bus: reduce scope of backend watch
Currently a single watch on /local/domain/X/backend is registered by each
QEMU process running in service domain X (where X is usually 0). The purpose
of this watch is to ensure that QEMU is notified when the Xen toolstack
creates a new device backend area.
Such a backend area is specific to a single frontend area created for a
specific guest domain and, since each QEMU process is also created to service
a specfic guest domain, it is unnecessary and inefficient to notify all QEMU
processes.
Only the QEMU process associated with the same guest domain need
receive the notification. This patch re-factors the watch registration code
such that notifications are targetted appropriately.
Reported-by: Jerome Leseinne <jerome.leseinne@gmail.com>
Signed-off-by: Paul Durrant <pdurrant@amazon.com>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20201001081500.1026-1-paul@xen.org>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Commit: 8959e0a63a3a681a31ff8397d9345a88e6d905bf
https://github.com/qemu/qemu/commit/8959e0a63a3a681a31ff8397d9345a88e6d905bf
Author: Jason Andryuk <jandryuk@gmail.com>
Date: 2020-10-19 (Mon, 19 Oct 2020)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/xen: Set suppress-vmdesc for Xen machines
xen-save-devices-state doesn't currently generate a vmdesc, so restore
always triggers "Expected vmdescription section, but got 0". This is
not a problem when restore comes from a file. However, when QEMU runs
in a linux stubdom and comes over a console, EOF is not received. This
causes a delay restoring - though it does restore.
Setting suppress-vmdesc skips looking for the vmdesc during restore and
avoids the wait.
The other approach would be generate a vmdesc in qemu_save_device_state.
Since COLO shared that function, and the vmdesc is just discarded on
restore, we choose to skip it.
Reported-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
Signed-off-by: Jason Andryuk <jandryuk@gmail.com>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20201013190506.3325-1-jandryuk@gmail.com>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Commit: 4c41341af76cfc85b5a6c0f87de4838672ab9f89
https://github.com/qemu/qemu/commit/4c41341af76cfc85b5a6c0f87de4838672ab9f89
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M configure
M hw/i386/pc_piix.c
M hw/i386/xen/xen_platform.c
M hw/xen/xen-backend.c
M hw/xen/xen-bus.c
M include/hw/xen/xen-backend.h
M include/hw/xen/xen-bus.h
M include/hw/xen/xen-legacy-backend.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20201020' into
staging
Xen queue
* cleanup patches.
* improve xen backend setup performance when other xen guests are
running/booting.
* improve xen guest migration when running in a stubdomain.
# gpg: Signature made Tue 20 Oct 2020 10:55:11 BST
# gpg: using RSA key F80C006308E22CFD8A92E7980CF5572FD7FB55AF
# gpg: issuer "anthony.perard@citrix.com"
# gpg: Good signature from "Anthony PERARD <anthony.perard@gmail.com>"
[marginal]
# gpg: aka "Anthony PERARD <anthony.perard@citrix.com>"
[marginal]
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 5379 2F71 024C 600F 778A 7161 D8D5 7199 DF83 42C8
# Subkey fingerprint: F80C 0063 08E2 2CFD 8A92 E798 0CF5 572F D7FB 55AF
* remotes/aperard/tags/pull-xen-20201020:
hw/xen: Set suppress-vmdesc for Xen machines
xen-bus: reduce scope of backend watch
xen: Rename XENBACKEND_DEVICE to XENBACKEND
xen: xenguest is not used so is not needed
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5288145d716338ace0f83e3ff05c4d07715bb4f4
https://github.com/qemu/qemu/commit/5288145d716338ace0f83e3ff05c4d07715bb4f4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Fix SMLAD incorrect setting of Q bit
The SMLAD instruction is supposed to:
* signed multiply Rn[15:0] * Rm[15:0]
* signed multiply Rn[31:16] * Rm[31:16]
* perform a signed addition of the products and Ra
* set Rd to the low 32 bits of the theoretical
infinite-precision result
* set the Q flag if the sign-extension of Rd
would differ from the infinite-precision result
(ie on overflow)
Our current implementation doesn't quite do this, though: it performs
an addition of the products setting Q on overflow, and then it adds
Ra, again possibly setting Q. This sometimes incorrectly sets Q when
the architecturally mandated only-check-for-overflow-once algorithm
does not. For instance:
r1 = 0x80008000; r2 = 0x80008000; r3 = 0xffffffff
smlad r0, r1, r2, r3
This is (-32768 * -32768) + (-32768 * -32768) - 1
The products are both 0x4000_0000, so when added together as 32-bit
signed numbers they overflow (and QEMU sets Q), but because the
addition of Ra == -1 brings the total back down to 0x7fff_ffff
there is no overflow for the complete operation and setting Q is
incorrect.
Fix this edge case by resorting to 64-bit arithmetic for the
case where we need to add three values together.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201009144712.11187-1-peter.maydell@linaro.org
Commit: 61db12d9f9eb36761edba4d9a414cd8dd34c512b
https://github.com/qemu/qemu/commit/61db12d9f9eb36761edba4d9a414cd8dd34c512b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/helper.h
M target/arm/translate-vfp.c.inc
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest
For AArch32, unlike the VCVT of integer to float, which honours the
rounding mode specified by the FPSCR, VCVT of fixed-point to float is
always round-to-nearest. (AArch64 fixed-point-to-float conversions
always honour the FPCR rounding mode.)
Implement this by providing _round_to_nearest versions of the
relevant helpers which set the rounding mode temporarily when making
the call to the underlying softfloat function.
We only need to change the VFP VCVT instructions, because the
standard- FPSCR value used by the Neon VCVT is always set to
round-to-nearest, so we don't need to do the extra work of saving
and restoring the rounding mode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201013103532.13391-1-peter.maydell@linaro.org
Commit: 8ddd611a50481826a8e583b7ccdf6e1866e22c15
https://github.com/qemu/qemu/commit/8ddd611a50481826a8e583b7ccdf6e1866e22c15
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M hw/arm/strongarm.c
Log Message:
-----------
hw/arm/strongarm: Fix 'time to transmit a char' unit comment
The time to transmit a char is expressed in nanoseconds, not in ticks.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201014213601.205222-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b77a52a0c14163e4d8602c94b64bae9cf3524ee1
https://github.com/qemu/qemu/commit/b77a52a0c14163e4d8602c94b64bae9cf3524ee1
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M default-configs/devices/arm-softmmu.mak
M hw/arm/Kconfig
Log Message:
-----------
hw/arm: Restrict APEI tables generation to the 'virt' machine
While APEI is a generic ACPI feature (usable by X86 and ARM64), only
the 'virt' machine uses it, by enabling the RAS Virtualization. See
commit 2afa8c8519: "hw/arm/virt: Introduce a RAS machine option").
Restrict the APEI tables generation code to the single user: the virt
machine. If another machine wants to use it, it simply has to 'select
ACPI_APEI' in its Kconfig.
Fixes: aa16508f1d ("ACPI: Build related register address fields via hardware
error fw_cfg blob")
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Dongjiu Geng <gengdongjiu@huawei.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20201008161414.2672569-1-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f3f69362fdd957dbdc6b5bd1120347560752e4b2
https://github.com/qemu/qemu/commit/f3f69362fdd957dbdc6b5bd1120347560752e4b2
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M hw/timer/bcm2835_systmr.c
M include/hw/timer/bcm2835_systmr.h
Log Message:
-----------
hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition
Use the BCM2835_SYSTIMER_COUNT definition instead of the
magic '4' value.
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201010203709.3116542-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cdb490da8695ec67dbc151335b31450abb9e564e
https://github.com/qemu/qemu/commit/cdb490da8695ec67dbc151335b31450abb9e564e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M hw/timer/bcm2835_systmr.c
M include/hw/timer/bcm2835_systmr.h
Log Message:
-----------
hw/timer/bcm2835: Rename variable holding CTRL_STATUS register
The variable holding the CTRL_STATUS register is misnamed
'status'. Rename it 'ctrl_status' to make it more obvious
this register is also used to control the peripheral.
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201010203709.3116542-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: be95dffa326a63f6f850d389dbe358d25e8ba20b
https://github.com/qemu/qemu/commit/be95dffa326a63f6f850d389dbe358d25e8ba20b
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M hw/timer/bcm2835_systmr.c
M hw/timer/trace-events
M include/hw/timer/bcm2835_systmr.h
Log Message:
-----------
hw/timer/bcm2835: Support the timer COMPARE registers
This peripheral has 1 free-running timer and 4 compare registers.
Only the free-running timer is implemented. Add support the
COMPARE registers (each register is wired to an IRQ).
Reference: "BCM2835 ARM Peripherals" datasheet [*]
chapter 12 "System Timer":
The System Timer peripheral provides four 32-bit timer channels
and a single 64-bit free running counter. Each channel has an
output compare register, which is compared against the 32 least
significant bits of the free running counter values. When the
two values match, the system timer peripheral generates a signal
to indicate a match for the appropriate channel. The match signal
is then fed into the interrupt controller.
This peripheral is used since Linux 3.7, commit ee4af5696720
("ARM: bcm2835: add system timer").
[*] https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20201010203709.3116542-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 722bde6789c55f9f872026f796ecabecbec5d82b
https://github.com/qemu/qemu/commit/722bde6789c55f9f872026f796ecabecbec5d82b
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M hw/arm/bcm2835_peripherals.c
Log Message:
-----------
hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs
The SYS_timer is not directly wired to the ARM core, but to the
SoC (peripheral) interrupt controller.
Fixes: 0e5bbd74064 ("hw/arm/bcm2835_peripherals: Use the SYS_timer")
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201010203709.3116542-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3ab6e68cd035de244d9bf999900349a69939ad41
https://github.com/qemu/qemu/commit/3ab6e68cd035de244d9bf999900349a69939ad41
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/exec-all.h
Log Message:
-----------
accel/tcg: Add tlb_flush_page_bits_by_mmuidx*
On ARM, the Top Byte Ignore feature means that only 56 bits of
the address are significant in the virtual address. We are
required to give the entire 64-bit address to FAR_ELx on fault,
which means that we do not "clean" the top byte early in TCG.
This new interface allows us to flush all 256 possible aliases
for a given page, currently missed by tlb_flush_page*.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201016210754.818257-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ea04dce7bb4ccd3e464e5189c0d6d53510b7c212
https://github.com/qemu/qemu/commit/ea04dce7bb4ccd3e464e5189c0d6d53510b7c212
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Use tlb_flush_page_bits_by_mmuidx*
When TBI is enabled in a given regime, 56 bits of the address
are significant and we need to clear out any other matching
virtual addresses with differing tags.
The other uses of tlb_flush_page (without mmuidx) in this file
are only used by aarch32 mode.
Fixes: 38d931687fa1
Reported-by: Jordan Frank <jordanfrank@fb.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201016210754.818257-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 19d50149c857e50ccb1ee35dd4277f9d4954877f
https://github.com/qemu/qemu/commit/19d50149c857e50ccb1ee35dd4277f9d4954877f
Author: Havard Skinnemoen <hskinnemoen@google.com>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/npcm7xx_timer-test.c
Log Message:
-----------
tests/qtest: Add npcm7xx timer test
This test exercises the various modes of the npcm7xx timer. In
particular, it triggers the bug found by the fuzzer, as reported here:
https://lists.gnu.org/archive/html/qemu-devel/2020-09/msg02992.html
It also found several other bugs, especially related to interrupt
handling.
The test exercises all the timers in all the timer modules, which
expands to 180 test cases in total.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20201008232154.94221-2-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a0c0c9f8b4093bf1564d705d8977b6ba46cd2f5a
https://github.com/qemu/qemu/commit/a0c0c9f8b4093bf1564d705d8977b6ba46cd2f5a
Author: Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M docs/devel/loads-stores.rst
Log Message:
-----------
loads-stores.rst: add footnote that clarifies GETPC usage
Current documentation is not too clear on the GETPC usage.
In particular, when used outside the top level helper function
it causes unexpected behavior.
Signed-off-by: Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com>
Message-id: 20201015095147.1691-1-e.emanuelegiuseppe@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b68a92f4cb16115025f41bc59e1b2f182a610370
https://github.com/qemu/qemu/commit/b68a92f4cb16115025f41bc59e1b2f182a610370
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M hw/intc/bcm2835_ic.c
M hw/intc/trace-events
Log Message:
-----------
hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
Add trace events for GPU and CPU IRQs.
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201017180731.1165871-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e7534f29b1587527613fdce3e460ac4720e5d18b
https://github.com/qemu/qemu/commit/e7534f29b1587527613fdce3e460ac4720e5d18b
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M hw/intc/bcm2836_control.c
Log Message:
-----------
hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
The IRQ values are defined few lines earlier, use them instead of
the magic numbers.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201017180731.1165871-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4aedfc0f633fd06dd2a5dc8ffa93f4c56117e37f
https://github.com/qemu/qemu/commit/4aedfc0f633fd06dd2a5dc8ffa93f4c56117e37f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/mte_helper.c
Log Message:
-----------
target/arm: Remove redundant mmu_idx lookup
We already have the full ARMMMUIdx as computed from the
function parameter.
For the purpose of regime_has_2_ranges, we can ignore any
difference between AccType_Normal and AccType_Unpriv, which
would be the only difference between the passed mmu_idx
and arm_mmu_idx_el.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Message-id: 20201008162155.161886-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 50244cc76abcac3296cff3d84826f5ff71808c80
https://github.com/qemu/qemu/commit/50244cc76abcac3296cff3d84826f5ff71808c80
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/mte_helper.c
Log Message:
-----------
target/arm: Fix reported EL for mte_check_fail
The reporting in AArch64.TagCheckFail only depends on PSTATE.EL,
and not the AccType of the operation. There are two guest
visible problems that affect LDTR and STTR because of this:
(1) Selecting TCF0 vs TCF1 to decide on reporting,
(2) Report "data abort same el" not "data abort lower el".
Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Message-id: 20201008162155.161886-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4301acd7d7d455792ea873ced75c0b5d653618b1
https://github.com/qemu/qemu/commit/4301acd7d7d455792ea873ced75c0b5d653618b1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11
Unlike many other bits in HCR_EL2, the description for this
bit does not contain the phrase "if ... this field behaves
as 0 for all purposes other than", so do not squash the bit
in arm_hcr_el2_eff.
Instead, replicate the E2H+TGE test in the two places that
require it.
Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Message-id: 20201008162155.161886-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3cd27b58dd2045580689bdece677fa14e12c324d
https://github.com/qemu/qemu/commit/3cd27b58dd2045580689bdece677fa14e12c324d
Author: Peng Liang <liangpeng10@huawei.com>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M hw/i2c/microbit_i2c.c
Log Message:
-----------
microbit_i2c: Fix coredump when dump-vmstate
VMStateDescription.fields should be end with VMSTATE_END_OF_LIST().
However, microbit_i2c_vmstate doesn't follow it. Let's change it.
Fixes: 9d68bf564e ("arm: Stub out NRF51 TWI magnetometer/accelerometer
detection")
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20201019093401.2993833-1-liangpeng10@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b3267ff675dd410b4c2a569e209cb7d468cf1873
https://github.com/qemu/qemu/commit/b3267ff675dd410b4c2a569e209cb7d468cf1873
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M hw/arm/nseries.c
Log Message:
-----------
hw/arm/nseries: Fix loading kernel image on n8x0 machines
Commit 7998beb9c2e removed the ram_size initialization in the
arm_boot_info structure, however it is used by arm_load_kernel().
Initialize the field to fix:
$ qemu-system-arm -M n800 -append 'console=ttyS1' \
-kernel meego-arm-n8x0-1.0.80.20100712.1431-vmlinuz-2.6.35~rc4-129.1-n8x0
qemu-system-arm: kernel
'meego-arm-n8x0-1.0.80.20100712.1431-vmlinuz-2.6.35~rc4-129.1-n8x0' is too
large to fit in RAM (kernel size 1964608, RAM size 0)
Noticed while running the test introduced in commit 050a82f0c5b
("tests/acceptance: Add a test for the N800 and N810 arm machines").
Fixes: 7998beb9c2e ("arm/nseries: use memdev for RAM")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Thomas Huth <thuth@redhat.com>
Message-id: 20201019095148.1602119-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 514101c0b931f0a11a40d29d26af1cc40482f951
https://github.com/qemu/qemu/commit/514101c0b931f0a11a40d29d26af1cc40482f951
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M scripts/decodetree.py
Log Message:
-----------
decodetree: Fix codegen for non-overlapping group inside overlapping group
For nested groups like:
{
[
pattern 1
pattern 2
]
pattern 3
}
the intended behaviour is that patterns 1 and 2 must not
overlap with each other; if the insn matches neither then
we fall through to pattern 3 as the next thing in the
outer overlapping group.
Currently we generate incorrect code for this situation,
because in the code path for a failed match inside the
inner non-overlapping group we generate a "return" statement,
which causes decode to stop entirely rather than continuing
to the next thing in the outer group.
Generate a "break" instead, so that decode flow behaves
as required for this nested group case.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-2-peter.maydell@linaro.org
Commit: 5d2555a1fe7370feeb1efbbf276a653040910017
https://github.com/qemu/qemu/commit/5d2555a1fe7370feeb1efbbf276a653040910017
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/m-nocp.decode
M target/arm/translate-vfp.c.inc
Log Message:
-----------
target/arm: Implement v8.1M NOCP handling
>From v8.1M, disabled-coprocessor handling changes slightly:
* coprocessors 8, 9, 14 and 15 are also governed by the
cp10 enable bit, like cp11
* an extra range of instruction patterns is considered
to be inside the coprocessor space
We previously marked these up with TODO comments; implement the
correct behaviour.
Unfortunately there is no ID register field which indicates this
behaviour. We could in theory test an unrelated ID register which
indicates guaranteed-to-be-in-v8.1M behaviour like ID_ISAR0.CmpBranch
>= 3 (low-overhead-loops), but it seems better to simply define a new
ARM_FEATURE_V8_1M feature flag and use it for this and other
new-in-v8.1M behaviour that isn't identifiable from the ID registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201019151301.2046-3-peter.maydell@linaro.org
Commit: cc73bbded0dfb5612b0e416f7eda13a66950542a
https://github.com/qemu/qemu/commit/cc73bbded0dfb5612b0e416f7eda13a66950542a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/t32.decode
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement v8.1M conditional-select insns
v8.1M brings four new insns to M-profile:
* CSEL : Rd = cond ? Rn : Rm
* CSINC : Rd = cond ? Rn : Rm+1
* CSINV : Rd = cond ? Rn : ~Rm
* CSNEG : Rd = cond ? Rn : -Rm
Implement these.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-4-peter.maydell@linaro.org
Commit: 45f11876ae86128bdee27e0b089045de43cc88e4
https://github.com/qemu/qemu/commit/45f11876ae86128bdee27e0b089045de43cc88e4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/t32.decode
Log Message:
-----------
target/arm: Make the t32 insn[25:23]=111 group non-overlapping
The t32 decode has a group which represents a set of insns
which overlap with B_cond_thumb because they have [25:23]=111
(which is an invalid condition code field for the branch insn).
This group is currently defined using the {} overlap-OK syntax,
but it is almost entirely non-overlapping patterns. Switch
it over to use a non-overlapping group.
For this to be valid syntactically, CPS must move into the same
overlapping-group as the hint insns (CPS vs hints was the
only actual use of the overlap facility for the group).
The non-overlapping subgroup for CLREX/DSB/DMB/ISB/SB is no longer
necessary and so we can remove it (promoting those insns to
be members of the parent group).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-5-peter.maydell@linaro.org
Commit: 920f04fa3ea789f8f85a52cee5395b8887b56cf7
https://github.com/qemu/qemu/commit/920f04fa3ea789f8f85a52cee5395b8887b56cf7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Don't allow BLX imm for M-profile
The BLX immediate insn in the Thumb encoding always performs
a switch from Thumb to Arm state. This would be totally useless
in M-profile which has no Arm decoder, and so the instruction
does not exist at all there. Make the encoding UNDEF for M-profile.
(This part of the encoding space is used for the branch-future
and low-overhead-loop insns in v8.1M.)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-6-peter.maydell@linaro.org
Commit: 05903f036edba8e3ed940cc215b8e27fb49265b9
https://github.com/qemu/qemu/commit/05903f036edba8e3ed940cc215b8e27fb49265b9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/t32.decode
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement v8.1M branch-future insns (as NOPs)
v8.1M implements a new 'branch future' feature, which is a
set of instructions that request the CPU to perform a branch
"in the future", when it reaches a particular execution address.
In hardware, the expected implementation is that the information
about the branch location and destination is cached and then
acted upon when execution reaches the specified address.
However the architecture permits an implementation to discard
this cached information at any point, and so guest code must
always include a normal branch insn at the branch point as
a fallback. In particular, an implementation is specifically
permitted to treat all BF insns as NOPs (which is equivalent
to discarding the cached information immediately).
For QEMU, implementing this caching of branch information
would be complicated and would not improve the speed of
execution at all, so we make the IMPDEF choice to implement
all BF insns as NOPs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-7-peter.maydell@linaro.org
Commit: b7226369721896ab9ef71544e4fe95b40710e05a
https://github.com/qemu/qemu/commit/b7226369721896ab9ef71544e4fe95b40710e05a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/t32.decode
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement v8.1M low-overhead-loop instructions
v8.1M's "low-overhead-loop" extension has three instructions
for looping:
* DLS (start of a do-loop)
* WLS (start of a while-loop)
* LE (end of a loop)
The loop-start instructions are both simple operations to start a
loop whose iteration count (if any) is in LR. The loop-end
instruction handles "decrement iteration count and jump back to loop
start"; it also caches the information about the branch back to the
start of the loop to improve performance of the branch on subsequent
iterations.
As with the branch-future instructions, the architecture permits an
implementation to discard the LO_BRANCH_INFO cache at any time, and
QEMU takes the IMPDEF option to never set it in the first place
(equivalent to discarding it immediately), because for us a "real"
implementation would be unnecessary complexity.
(This implementation only provides the simple looping constructs; the
vector extension MVE (Helium) adds some extra variants to handle
looping across vectors. We'll add those later when we implement
MVE.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201019151301.2046-8-peter.maydell@linaro.org
Commit: 532a3af5fbd348bca371b4a56b45f8f97c7c5519
https://github.com/qemu/qemu/commit/532a3af5fbd348bca371b4a56b45f8f97c7c5519
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
In arm_cpu_realizefn(), if the CPU has VFP or Neon disabled then we
squash the ID register fields so that we don't advertise it to the
guest. This code was written for A-profile and needs some tweaks to
work correctly on M-profile:
* A-profile only fields should not be zeroed on M-profile:
- MVFR0.FPSHVEC,FPTRAP
- MVFR1.SIMDLS,SIMDINT,SIMDSP,SIMDHP
- MVFR2.SIMDMISC
* M-profile only fields should be zeroed on M-profile:
- MVFR1.FP16
In particular, because MVFR1.SIMDHP on A-profile is the same field as
MVFR1.FP16 on M-profile this code was incorrectly disabling FP16
support on an M-profile CPU (where has_neon is always false). This
isn't a visible bug yet because we don't have any M-profile CPUs with
FP16 support, but the change is necessary before we introduce any.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-9-peter.maydell@linaro.org
Commit: d31e2ce68d56f5bcc83831497e5fe4b8a7e18e85
https://github.com/qemu/qemu/commit/d31e2ce68d56f5bcc83831497e5fe4b8a7e18e85
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
M-profile CPUs with half-precision floating point support should
be able to write to FPSCR.FZ16, but an M-profile specific masking
of the value at the top of vfp_set_fpscr() currently prevents that.
This is not yet an active bug because we have no M-profile
FP16 CPUs, but needs to be fixed before we can add any.
The bits that the masking is effectively preventing from being
set are the A-profile only short-vector Len and Stride fields,
plus the Neon QC bit. Rearrange the order of the function so
that those fields are handled earlier and only under a suitable
guard; this allows us to drop the M-profile specific masking,
making FZ16 writeable.
This change also makes the QC bit correctly RAZ/WI for older
no-Neon A-profile cores.
This refactoring also paves the way for the low-overhead-branch
LTPSIZE field, which uses some of the bits that are used for
A-profile Stride and Len.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201019151301.2046-10-peter.maydell@linaro.org
Commit: 8128c8e8cc9489a8387c74075974f86dc0222e7f
https://github.com/qemu/qemu/commit/8128c8e8cc9489a8387c74075974f86dc0222e7f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
If the M-profile low-overhead-branch extension is implemented, FPSCR
bits [18:16] are a new field LTPSIZE. If MVE is not implemented
(currently always true for us) then this field always reads as 4 and
ignores writes.
These bits used to be the vector-length field for the old
short-vector extension, so we need to take care that they are not
misinterpreted as setting vec_len. We do this with a rearrangement
of the vfp_set_fpscr() code that deals with vec_len, vec_stride
and also the QC bit; this obviates the need for the M-profile
only masking step that we used to have at the start of the function.
We provide a new field in CPUState for LTPSIZE, even though this
will always be 4, in preparation for MVE, so we don't have to
come back later and split it out of the vfp.xregs[FPSCR] value.
(This state struct field will be saved and restored as part of
the FPSCR value via the vmstate_fpscr in machine.c.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201019151301.2046-11-peter.maydell@linaro.org
Commit: ac793156f650ae2d77834932d72224175ee69086
https://github.com/qemu/qemu/commit/ac793156f650ae2d77834932d72224175ee69086
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-20 (Tue, 20 Oct 2020)
Changed paths:
M accel/tcg/cputlb.c
M default-configs/devices/arm-softmmu.mak
M docs/devel/loads-stores.rst
M hw/arm/Kconfig
M hw/arm/bcm2835_peripherals.c
M hw/arm/nseries.c
M hw/arm/strongarm.c
M hw/i2c/microbit_i2c.c
M hw/intc/bcm2835_ic.c
M hw/intc/bcm2836_control.c
M hw/intc/trace-events
M hw/timer/bcm2835_systmr.c
M hw/timer/trace-events
M include/exec/exec-all.h
M include/hw/timer/bcm2835_systmr.h
M scripts/decodetree.py
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/internals.h
M target/arm/m-nocp.decode
M target/arm/mte_helper.c
M target/arm/t32.decode
M target/arm/translate-vfp.c.inc
M target/arm/translate.c
M target/arm/vfp_helper.c
M tests/qtest/meson.build
A tests/qtest/npcm7xx_timer-test.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20201020-1' into staging
target-arm queue:
* Fix AArch32 SMLAD incorrect setting of Q bit
* AArch32 VCVT fixed-point to float is always round-to-nearest
* strongarm: Fix 'time to transmit a char' unit comment
* Restrict APEI tables generation to the 'virt' machine
* bcm2835: minor code cleanups
* bcm2835: connect all IRQs from SYS_timer device
* correctly flush TLBs when TBI is enabled
* tests/qtest: Add npcm7xx timer test
* loads-stores.rst: add footnote that clarifies GETPC usage
* Fix reported EL for mte_check_fail
* Ignore HCR_EL2.ATA when {E2H,TGE} != 11
* microbit_i2c: Fix coredump when dump-vmstate
* nseries: Fix loading kernel image on n8x0 machines
* Implement v8.1M low-overhead-loops
# gpg: Signature made Tue 20 Oct 2020 21:10:35 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20201020-1: (29 commits)
target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
target/arm: Implement v8.1M low-overhead-loop instructions
target/arm: Implement v8.1M branch-future insns (as NOPs)
target/arm: Don't allow BLX imm for M-profile
target/arm: Make the t32 insn[25:23]=111 group non-overlapping
target/arm: Implement v8.1M conditional-select insns
target/arm: Implement v8.1M NOCP handling
decodetree: Fix codegen for non-overlapping group inside overlapping group
hw/arm/nseries: Fix loading kernel image on n8x0 machines
microbit_i2c: Fix coredump when dump-vmstate
target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11
target/arm: Fix reported EL for mte_check_fail
target/arm: Remove redundant mmu_idx lookup
hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
loads-stores.rst: add footnote that clarifies GETPC usage
tests/qtest: Add npcm7xx timer test
target/arm: Use tlb_flush_page_bits_by_mmuidx*
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/782d7b30dd8e...ac793156f650