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[Qemu-commits] [qemu/qemu] e2e716: tcg: Adjust simd_desc size encoding
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] e2e716: tcg: Adjust simd_desc size encoding |
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Date: |
Thu, 08 Oct 2020 11:15:31 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: e2e7168a214b0ed98dc357bba96816486a289762
https://github.com/qemu/qemu/commit/e2e7168a214b0ed98dc357bba96816486a289762
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M include/tcg/tcg-gvec-desc.h
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Adjust simd_desc size encoding
With larger vector sizes, it turns out oprsz == maxsz, and we only
need to represent mismatch for oprsz <= 32. We do, however, need
to represent larger oprsz and do so without reducing SIMD_DATA_BITS.
Reduce the size of the oprsz field and increase the maxsz field.
Steal the oprsz value of 24 to indicate equality with maxsz.
Tested-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9be0d08019465b38e2f1a605960961a491430c21
https://github.com/qemu/qemu/commit/9be0d08019465b38e2f1a605960961a491430c21
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390/tcg-target.c.inc
M tcg/sparc/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Drop union from TCGArgConstraint
The union is unused; let "regs" appear in the main structure
without the "u.regs" wrapping.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 66792f90f14fef18b25a168922877a367ecdca05
https://github.com/qemu/qemu/commit/66792f90f14fef18b25a168922877a367ecdca05
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg.c
Log Message:
-----------
tcg: Move sorted_args into TCGArgConstraint.sort_index
This uses an existing hole in the TCGArgConstraint structure
and will be convenient for keeping the data in one place.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 74a117906b87ff9220e4baae5a7431d6f4eadd45
https://github.com/qemu/qemu/commit/74a117906b87ff9220e4baae5a7431d6f4eadd45
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390/tcg-target.c.inc
M tcg/sparc/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Remove TCG_CT_REG
This wasn't actually used for anything, really. All variable
operands must accept registers, and which are indicated by the
set in TCGArgConstraint.regs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: bc2b17e6ea582ef3ade2bdca750de269c674c915
https://github.com/qemu/qemu/commit/bc2b17e6ea582ef3ade2bdca750de269c674c915
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg.c
Log Message:
-----------
tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
These are easier to set and test when they have their own fields.
Reduce the size of alias_index and sort_index to 4 bits, which is
sufficient for TCG_MAX_OP_ARGS. This leaves only the bits indicating
constants within the ct field.
Move all initialization to allocation time, rather than init
individual fields in process_op_defs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 70cad3c400bce4e1d364b81c09ac656e6166a573
https://github.com/qemu/qemu/commit/70cad3c400bce4e1d364b81c09ac656e6166a573
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M include/tcg/tcg.h
Log Message:
-----------
tcg: Remove TCGOpDef.used
The last user of this field disappeared in f69d277ece4.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f80d09b599a5e0fd7f44653f23b04104cb703f7a
https://github.com/qemu/qemu/commit/f80d09b599a5e0fd7f44653f23b04104cb703f7a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Fix dupi for avx2 32-bit hosts
The previous change wrongly stated that 32-bit avx2 should have
used VPBROADCASTW. But that's a 16-bit broadcast and we want a
32-bit broadcast.
Fixes: 7b60ef3264e
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a5b30d950c42b14bc9da24d1e68add6538d23336
https://github.com/qemu/qemu/commit/a5b30d950c42b14bc9da24d1e68add6538d23336
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M tcg/tcg-op-vec.c
Log Message:
-----------
tcg: Fix generation of dupi_vec for 32-bit host
The definition of INDEX_op_dupi_vec is that it operates on
units of tcg_target_ulong -- in this case 32 bits. It does
not work to use this for a uint64_t value that happens to be
small enough to fit in tcg_target_ulong.
Fixes: d2fd745fe8b
Fixes: db432672dc5
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1dc4fe70128db05237a00eda6eb15e2b44deb31f
https://github.com/qemu/qemu/commit/1dc4fe70128db05237a00eda6eb15e2b44deb31f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Fold dup2_vec
When the two arguments are identical, this can be reduced to
dup_vec or to mov_vec from a tcg_constant_vec.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: cae5d53b9e72d7a1e43cebeb36471d77a16c6e43
https://github.com/qemu/qemu/commit/cae5d53b9e72d7a1e43cebeb36471d77a16c6e43
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M tcg/aarch64/tcg-target.h
M tcg/i386/tcg-target.h
M tcg/ppc/tcg-target.h
Log Message:
-----------
tcg: Remove TCG_TARGET_HAS_cmp_vec
The cmp_vec opcode is mandatory; this symbol is unused.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 62475e9d007d83db4d0a6ccebcda8914f392e9c9
https://github.com/qemu/qemu/commit/62475e9d007d83db4d0a6ccebcda8914f392e9c9
Author: Kele Huang <kele.hwang@gmail.com>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M accel/tcg/user-exec.c
Log Message:
-----------
accel/tcg: Fix computing of is_write for MIPS
Detect all MIPS store instructions in cpu_signal_handler for all available
MIPS versions, and set is_write if encountering such store instructions.
This fixed the error while dealing with self-modified code for MIPS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Kele Huang <kele.hwang@gmail.com>
Signed-off-by: Xu Zou <iwatchnima@gmail.com>
Message-Id: <20201002081420.10814-1-kele.hwang@gmail.com>
[rth: Use uintptr_t for pc to fix n32 build error.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e64cf4d569f6461d6b9072e00d6e78d0ab8bd4a7
https://github.com/qemu/qemu/commit/e64cf4d569f6461d6b9072e00d6e78d0ab8bd4a7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-10-08 (Thu, 08 Oct 2020)
Changed paths:
M accel/tcg/user-exec.c
M include/tcg/tcg-gvec-desc.h
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
M tcg/mips/tcg-target.c.inc
M tcg/optimize.c
M tcg/ppc/tcg-target.c.inc
M tcg/ppc/tcg-target.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390/tcg-target.c.inc
M tcg/sparc/tcg-target.c.inc
M tcg/tcg-op-gvec.c
M tcg/tcg-op-vec.c
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20201008' into staging
Extend maximum gvec vector size
Fix i386 avx2 dupi
Fix mips host user-only write detection
Misc cleanups.
# gpg: Signature made Thu 08 Oct 2020 13:55:22 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20201008:
accel/tcg: Fix computing of is_write for MIPS
tcg: Remove TCG_TARGET_HAS_cmp_vec
tcg/optimize: Fold dup2_vec
tcg: Fix generation of dupi_vec for 32-bit host
tcg/i386: Fix dupi for avx2 32-bit hosts
tcg: Remove TCGOpDef.used
tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
tcg: Remove TCG_CT_REG
tcg: Move sorted_args into TCGArgConstraint.sort_index
tcg: Drop union from TCGArgConstraint
tcg: Adjust simd_desc size encoding
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/a1d22c668a76...e64cf4d569f6
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