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[Qemu-commits] [qemu/qemu] 0ae032: target/arm: Replace ARM_FEATURE_PXN w


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 0ae032: target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0....
Date: Thu, 01 Oct 2020 11:45:42 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0ae0326b984e77a55c224b7863071bd3d8951231
      
https://github.com/qemu/qemu/commit/0ae0326b984e77a55c224b7863071bd3d8951231
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check

The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN
bit in short-descriptor translation table format descriptors.  This
is indicated by ID_MMFR0.VMSA being at least 0b0100.  Replace the
feature bit with an ID register check, in line with our preference
for ID register checks over feature bits.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-2-peter.maydell@linaro.org


  Commit: 8a130a7be6e222965641e1fd9469fd3ee752c7d4
      
https://github.com/qemu/qemu/commit/8a130a7be6e222965641e1fd9469fd3ee752c7d4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c
    M target/arm/helper.c
    M target/arm/kvm64.c

  Log Message:
  -----------
  target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters

Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters
sub-struct. We're going to want id_pfr1 for an isar_features
check, and moving both at the same time avoids an odd
inconsistency.

Changes other than the ones to cpu.h and kvm64.c made
automatically with:
  perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c 
hw/intc/armv7m_nvic.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-3-peter.maydell@linaro.org


  Commit: d20c3ebda2972255e67c0a07368ac37f37a16c04
      
https://github.com/qemu/qemu/commit/d20c3ebda2972255e67c0a07368ac37f37a16c04
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs

M-profile CPUs only implement the ID registers as guest-visible if
the CPU implements the Main Extension (all our current CPUs except
the Cortex-M0 do).

Currently we handle this by having the Cortex-M0 leave the ID
register values in the ARMCPU struct as zero, but this conflicts with
our design decision to make QEMU behaviour be keyed off ID register
fields wherever possible.

Explicitly code the ID registers in the NVIC to return 0 if the Main
Extension is not implemented, so we can make the M0 model set the
ARMCPU struct fields to obtain the correct behaviour without those
values becoming guest-visible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-4-peter.maydell@linaro.org


  Commit: 51cb228a1d1c0e325b4e7dea0bfb3140d6d11422
      
https://github.com/qemu/qemu/commit/51cb228a1d1c0e325b4e7dea0bfb3140d6d11422
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M target/arm/cpu_tcg.c

  Log Message:
  -----------
  target/arm: Add ID register values for Cortex-M0

Give the Cortex-M0 ID register values corresponding to its
implemented behaviour.  These will not be guest-visible but will be
used to govern the behaviour of QEMU's emulation.  We use the same
values that the Cortex-M3 does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org


  Commit: dfc523a84b06b6a4b583ed4c29d24fd980dd37a0
      
https://github.com/qemu/qemu/commit/dfc523a84b06b6a4b583ed4c29d24fd980dd37a0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile

The M-profile definition of the MVFR1 ID register differs slightly
from the A-profile one, and in particular the check for "does the CPU
support fp16 arithmetic" is not the same.

We don't currently implement any M-profile CPUs with fp16 arithmetic,
so this is not yet a visible bug, but correcting the logic now
disarms this beartrap for when we eventually do.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-6-peter.maydell@linaro.org


  Commit: d8227b098301935ea8e0e032e7d41e5dc3e97590
      
https://github.com/qemu/qemu/commit/d8227b098301935ea8e0e032e7d41e5dc3e97590
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Fix sve ldr/str

The mte update missed a bit when producing clean addresses.

Fixes: b2aa8879b88
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200916014102.2446323-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dd701fafe55a78e655d4823d29226d92250a6b56
      
https://github.com/qemu/qemu/commit/dd701fafe55a78e655d4823d29226d92250a6b56
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Fix SVE splice

While converting to gen_gvec_ool_zzzp, we lost passing
a->esz as the data argument to the function.

Fixes: 36cbb7a8e71
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200918000500.2690937-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d8e53d7b2d22eb1e8c9fd0a5deb4268a6a8198f4
      
https://github.com/qemu/qemu/commit/d8e53d7b2d22eb1e8c9fd0a5deb4268a6a8198f4
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M include/hw/arm/raspi_platform.h

  Log Message:
  -----------
  hw/arm/raspi: Define various blocks base addresses

The Raspberry firmware is closed-source. While running it, it
accesses various I/O registers. Logging these accesses as UNIMP
(unimplemented) help to understand what the firmware is doing
(ideally we want it able to boot a Linux kernel).

Document various blocks we might use later.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200921034729.432931-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8c1e9927907fd74497f315a7b99ca3a8e2ff39ff
      
https://github.com/qemu/qemu/commit/8c1e9927907fd74497f315a7b99ca3a8e2ff39ff
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/arm/bcm2835_peripherals.c
    M include/hw/arm/bcm2835_peripherals.h

  Log Message:
  -----------
  hw/arm/bcm2835: Add more unimplemented peripherals

The bcm2835-v3d is used since Linux 4.7, see commit
49ac67e0c39c ("ARM: bcm2835: Add VC4 to the device tree"),
and the bcm2835-txp since Linux 4.19, see commit
b7dd29b401f5 ("ARM: dts: bcm283x: Add Transposer block").

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200921034729.432931-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e79f01f3ae65aae1baf01486d800f8b04a939d4e
      
https://github.com/qemu/qemu/commit/e79f01f3ae65aae1baf01486d800f8b04a939d4e
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/arm/raspi.c

  Log Message:
  -----------
  hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2

Commit 1c3db49d39 added the raspi3, which uses the same peripherals
than the raspi2 (but with different ARM cores). The raspi3 was
introduced without the ignore_memory_transaction_failures flag.
Almost 2 years later, the machine is usable running U-Boot and
Linux.
In commit 00cbd5bd74 we mapped a lot of unimplemented devices,
commit d442d95f added thermal block and commit 0e5bbd7406 the
system timer.
As we are happy with the raspi3, let's remove this flag on the
raspi2.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200921034729.432931-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 62f06f71373f2c3123e9599e59c80fccea24c604
      
https://github.com/qemu/qemu/commit/62f06f71373f2c3123e9599e59c80fccea24c604
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/arm/raspi.c

  Log Message:
  -----------
  hw/arm/raspi: Display the board revision in the machine description

Display the board revision in the machine description.

Before:

  $ qemu-system-aarch64 -M help | fgrep raspi
  raspi2               Raspberry Pi 2B
  raspi3               Raspberry Pi 3B

After:

  raspi2               Raspberry Pi 2B (revision 1.1)
  raspi3               Raspberry Pi 3B (revision 1.2)

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 02058e4b40f4132be3dcfede3e414562ff358146
      
https://github.com/qemu/qemu/commit/02058e4b40f4132be3dcfede3e414562ff358146
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/arm/raspi.c

  Log Message:
  -----------
  hw/arm/raspi: Load the firmware on the first core

The 'first_cpu' is more a QEMU accelerator-related concept
than a variable the machine requires to use.
Since the machine is aware of its CPUs, directly use the
first one to load the firmware.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0f15c6e338f040ccea698d83aa51074264194ce5
      
https://github.com/qemu/qemu/commit/0f15c6e338f040ccea698d83aa51074264194ce5
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/arm/raspi.c

  Log Message:
  -----------
  hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState

The arm_boot_info structure belong to the machine,
move it to RaspiMachineState.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f0eeb4b6154a33950e0ea887a2678053234f7a5f
      
https://github.com/qemu/qemu/commit/f0eeb4b6154a33950e0ea887a2678053234f7a5f
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/arm/raspi.c

  Log Message:
  -----------
  hw/arm/raspi: Avoid using TypeInfo::class_data pointer

Using class_data pointer to create a MachineClass is not
the recommended way anymore. The correct way is to open-code
the MachineClass::fields in the class_init() method.

We can not use TYPE_RASPI_MACHINE::class_base_init() because
it is called *before* each machine class_init(), therefore the
board_rev field is not populated. We have to manually call
raspi_machine_class_common_init() for each machine.

This partly reverts commit a03bde3674e.

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: aa35ec2213b35d7542d17cd65f09f4e827403ce5
      
https://github.com/qemu/qemu/commit/aa35ec2213b35d7542d17cd65f09f4e827403ce5
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/arm/raspi.c

  Log Message:
  -----------
  hw/arm/raspi: Use more specific machine names

Now that we can instantiate different machines based on their
board_rev register value, we can have various raspi2 and raspi3.

In commit fc78a990ec103 we corrected the machine description.
Correct the machine names too. For backward compatibility, add
an alias to the previous generic name.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-6-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 696788d6a94e9da6acdcf48e5fd5ec190f1f748a
      
https://github.com/qemu/qemu/commit/696788d6a94e9da6acdcf48e5fd5ec190f1f748a
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/arm/raspi.c

  Log Message:
  -----------
  hw/arm/raspi: Introduce RaspiProcessorId enum

As we only support a reduced set of the REV_CODE_PROCESSOR id
encoded in the board revision, define the PROCESSOR_ID values
as an enum. We can simplify the board_soc_type and cores_count
methods.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-7-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1af702690e07f50d154e40a353f1e43ab2fbcaf1
      
https://github.com/qemu/qemu/commit/1af702690e07f50d154e40a353f1e43ab2fbcaf1
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/arm/raspi.c

  Log Message:
  -----------
  hw/arm/raspi: Use RaspiProcessorId to set the firmware load address

The firmware load address depends on the SoC ("processor id") used,
not on the version of the board.

Suggested-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-8-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cdfaa57dcb53ba012439765a1462247dfda8595d
      
https://github.com/qemu/qemu/commit/cdfaa57dcb53ba012439765a1462247dfda8595d
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/arm/raspi.c

  Log Message:
  -----------
  hw/arm/raspi: Remove use of the 'version' value in the board code

We expected the 'version' ID to match the board processor ID,
but this is not always true (for example boards with revision
id 0xa02042/0xa22042 are Raspberry Pi 2 with a BCM2837 SoC).
This was not important because we were not modelling them, but
since the recent refactor now allow to model these boards, it
is safer to check the processor id directly. Remove the version
check.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-9-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 625581c2602b5b43e115b779a9a782478e6f92e7
      
https://github.com/qemu/qemu/commit/625581c2602b5b43e115b779a9a782478e6f92e7
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-10-01 (Thu, 01 Oct 2020)

  Changed paths:
    M hw/arm/bcm2835_peripherals.c
    M hw/arm/raspi.c
    M hw/intc/armv7m_nvic.c
    M include/hw/arm/bcm2835_peripherals.h
    M include/hw/arm/raspi_platform.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c
    M target/arm/helper.c
    M target/arm/kvm64.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201001' 
into staging

target-arm queue:
 * Make isar_feature_aa32_fp16_arith() handle M-profile
 * Fix SVE splice
 * Fix SVE LDR/STR
 * Remove ignore_memory_transaction_failures on the raspi2
 * raspi: Various cleanup/refactoring

# gpg: Signature made Thu 01 Oct 2020 15:46:47 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20201001:
  hw/arm/raspi: Remove use of the 'version' value in the board code
  hw/arm/raspi: Use RaspiProcessorId to set the firmware load address
  hw/arm/raspi: Introduce RaspiProcessorId enum
  hw/arm/raspi: Use more specific machine names
  hw/arm/raspi: Avoid using TypeInfo::class_data pointer
  hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
  hw/arm/raspi: Load the firmware on the first core
  hw/arm/raspi: Display the board revision in the machine description
  hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2
  hw/arm/bcm2835: Add more unimplemented peripherals
  hw/arm/raspi: Define various blocks base addresses
  target/arm: Fix SVE splice
  target/arm: Fix sve ldr/str
  target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile
  target/arm: Add ID register values for Cortex-M0
  hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
  target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
  target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/b23317eec471...625581c2602b



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