[Qemu-commits] [qemu/qemu] 14a560: hw/misc/a9scu: Do not allow invalid CPU count

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 14a560359d24d0f30ced8a2613b83323e9302490
      
https://github.com/qemu/qemu/commit/14a560359d24d0f30ced8a2613b83323e9302490
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/misc/a9scu.c

  Log Message:
  -----------
  hw/misc/a9scu: Do not allow invalid CPU count

Per the datasheet (DDI0407 r2p0):

  "The SCU connects one to four Cortex-A9 processors to
   the memory system through the AXI interfaces."

Change the instance_init() handler to a device_realize()
one so we can verify the property is in range, and return
an error to the caller if not.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200901144100.116742-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7b56d1f4aebf25d81d7b73fe1e2aac2d66b8c0ce
      
https://github.com/qemu/qemu/commit/7b56d1f4aebf25d81d7b73fe1e2aac2d66b8c0ce
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/misc/a9scu.c

  Log Message:
  -----------
  hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields

Per the datasheet (DDI0407 r2p0):

  "All SCU registers are byte accessible" and are 32-bit aligned.

Set MemoryRegionOps::valid min/max fields and simplify the write()
handler.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200901144100.116742-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9d8e61918f2ecb67885d90ea5c6ad8e3d73e7db4
      
https://github.com/qemu/qemu/commit/9d8e61918f2ecb67885d90ea5c6ad8e3d73e7db4
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/misc/a9scu.c

  Log Message:
  -----------
  hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields

This model implementation is designed for 32-bit accesses.
We can simplify setting the MemoryRegionOps::impl min/max
fields to 32-bit (memory::access_with_adjusted_size() will
take care of the 8/16-bit accesses).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200901144100.116742-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ae689ad7a89eff2e6222bbe30710a30cc7625538
      
https://github.com/qemu/qemu/commit/ae689ad7a89eff2e6222bbe30710a30cc7625538
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/misc/a9scu.c

  Log Message:
  -----------
  hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)

Report unimplemented register accesses using qemu_log_mask(UNIMP).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200901144100.116742-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c9ebc8c207e997c01d459529fd83ffd85c66cf9d
      
https://github.com/qemu/qemu/commit/c9ebc8c207e997c01d459529fd83ffd85c66cf9d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/timer/armv7m_systick.c

  Log Message:
  -----------
  hw/timer/armv7m_systick: assert that board code set system_clock_scale

It is the responsibility of board code for an armv7m system to set
system_clock_scale appropriately for the CPU speed of the core.
If it forgets to do this, then QEMU will hang if the guest tries
to use the systick timer in the "tick at the CPU clock frequency" mode.

We forgot that in a couple of our boards (see commits ce4f70e81ed23c93f,
e7e5a9595ab1136). Add an assertion in the systick reset method so
we don't let any new boards in with the same bug.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200825160847.18091-1-peter.maydell@linaro.org


  Commit: acfdd2398dc929d4e87507b8acbdc19c88379e0e
      
https://github.com/qemu/qemu/commit/acfdd2398dc929d4e87507b8acbdc19c88379e0e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M scripts/decodetree.py
    A tests/decode/succ_ident1.decode

  Log Message:
  -----------
  decodetree: Improve identifier matching

Only argument set members have to be C identifiers, everything
else gets prefixed during conversion to C.  Some places just
checked the leading character, and some places matched a leading
character plus a C identifier.

Convert everything to match full identifiers, including the
[&%@&] prefix, and drop the full C identifier requirement.

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200903192334.1603773-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6cf0f240e0b980a877abed12d2995f740eae6515
      
https://github.com/qemu/qemu/commit/6cf0f240e0b980a877abed12d2995f740eae6515
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.c.inc

  Log Message:
  -----------
  target/arm: Convert Neon 3-same-fp size field to MO_* in decode

In the Neon instructions, some instruction formats have a 2-bit size
field which corresponds exactly to QEMU's MO_8/16/32/64.  However the
floating-point insns in the 3-same group have a 1-bit size field
which is "0 for 32-bit float and 1 for 16-bit float".  Currently we
pass these values directly through to trans_ functions, which means
that when reading a particular trans_ function you need to know if
that insn uses a 2-bit size or a 1-bit size.

Move the handling of the 1-bit size to the decodetree file, so that
all these insns consistently pass a size to the trans_ function which
is an MO_8/16/32/64 value.

In this commit we switch over the insns using the 3same_fp and
3same_fp_q0 formats.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200903133209.5141-2-peter.maydell@linaro.org


  Commit: 0ae715c658a02af1834b63563c56112a6d8842cb
      
https://github.com/qemu/qemu/commit/0ae715c658a02af1834b63563c56112a6d8842cb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.c.inc

  Log Message:
  -----------
  target/arm: Convert Neon VCVT fp size field to MO_* in decode

Convert the insns using the 2reg_vcvt and 2reg_vcvt_f16 formats
to pass the size through to the trans function as a MO_* value
rather than the '0==f32, 1==f16' used in the fp 3-same encodings.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200903133209.5141-3-peter.maydell@linaro.org


  Commit: d186a4854c04e9832907b0b4240a47731da20993
      
https://github.com/qemu/qemu/commit/d186a4854c04e9832907b0b4240a47731da20993
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.c.inc

  Log Message:
  -----------
  target/arm: Convert VCMLA, VCADD size field to MO_* in decode

The VCMLA and VCADD insns have a size field which is 0 for fp16
and 1 for fp32 (note that this is the reverse of the Neon 3-same
encoding!). Convert it to MO_* values in decode for consistency.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200903133209.5141-4-peter.maydell@linaro.org


  Commit: 82bf7ae84ce739e77bba4f9b628ae799c5f204f6
      
https://github.com/qemu/qemu/commit/82bf7ae84ce739e77bba4f9b628ae799c5f204f6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M configure
    M docs/system/deprecated.rst
    R target/arm/kvm32.c
    M target/arm/meson.build

  Log Message:
  -----------
  target/arm: Remove KVM support for 32-bit Arm hosts

We deprecated the support for KVM on 32-bit Arm hosts in time
for release 5.0, which means that our deprecation policy allows
us to drop it in release 5.2. Remove the code.

To repeat the rationale from the deprecation note: the Linux
kernel dropped support for 32-bit Arm KVM hosts in 5.7.

Running 32-bit guests on a 64-bit Arm host remains supported.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200904154156.31943-2-peter.maydell@linaro.org


  Commit: e9b2bfaa64139f959fb8fe0b653ddff3b1b93601
      
https://github.com/qemu/qemu/commit/e9b2bfaa64139f959fb8fe0b653ddff3b1b93601
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/kvm-consts.h
    M target/arm/kvm.c
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  target/arm: Remove no-longer-reachable 32-bit KVM code

Now that 32-bit KVM host support is gone, KVM can never
be enabled unless CONFIG_AARCH64 is true, and some code
paths are no longer reachable and can be deleted.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200904154156.31943-3-peter.maydell@linaro.org


  Commit: 897d27260a7eaccbf4ff01e49021205c5616c8ef
      
https://github.com/qemu/qemu/commit/897d27260a7eaccbf4ff01e49021205c5616c8ef
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M docs/system/arm/mps2.rst
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: New board model mps2-an386

Implement a model of the MPS2 with the AN386 firmware. This is
essentially identical to the AN385 firmware, but it has a
Cortex-M4 rather than a Cortex-M3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200903202048.15370-2-peter.maydell@linaro.org


  Commit: 6d4811c4b688de368748c8095250ba12c905a21c
      
https://github.com/qemu/qemu/commit/6d4811c4b688de368748c8095250ba12c905a21c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M docs/system/arm/mps2.rst
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: New board model mps2-an500

Implement a model of the MPS2 with the AN500 firmware. This is
similar to the AN385, with the following differences:
 * Cortex-M7 CPU
 * PSRAM is at 0x6000_0000
 * Ethernet is at 0xa000_0000
 * No zbt_boot_ctrl remapping of the low 16K
   (but QEMU doesn't implement this anyway)
 * no "block RAM" at 0x01000000

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200903202048.15370-3-peter.maydell@linaro.org


  Commit: 99dfb04a2e287106a1311429577b78b986a0dc07
      
https://github.com/qemu/qemu/commit/99dfb04a2e287106a1311429577b78b986a0dc07
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M docs/system/arm/mps2.rst

  Log Message:
  -----------
  docs/system/arm/mps2.rst: Make board list consistent

Make the list of MPS2 boards consistent in the phrasing of each
entry, use the correct casing of "Arm", and move the mps2-an511
entry so the list is in numeric order.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200903202048.15370-4-peter.maydell@linaro.org


  Commit: 8e4ff4a8d2ba98d6e3d13404500299880d6432b6
      
https://github.com/qemu/qemu/commit/8e4ff4a8d2ba98d6e3d13404500299880d6432b6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M docs/system/deprecated.rst

  Log Message:
  -----------
  Deprecate Unicore32 port

Deprecate our Unicore32 target support:
 * the Linux kernel dropped support for unicore32 in commit
   05119217a9bd199c for its 5.9 release (with rationale in the
   cover letter: https://lkml.org/lkml/2020/8/3/232 )
 * there is apparently no upstream toolchain that can create unicore32
   binaries
 * the maintainer doesn't seem to have made any contributions to
   QEMU since the port first landed in 2012
 * nobody else seems to have made changes to the unicore code except
   for generic cleanups either

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20200825172719.19422-1-peter.maydell@linaro.org


  Commit: d84980051229fa43c96b363f52b3ba9357e6815a
      
https://github.com/qemu/qemu/commit/d84980051229fa43c96b363f52b3ba9357e6815a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M docs/system/deprecated.rst

  Log Message:
  -----------
  Deprecate lm32 port

Deprecate our lm32 target support. Michael Walle (former lm32 maintainer)
suggested that we do this in 2019:
 https://www.mail-archive.com/qemu-devel@nongnu.org/msg605024.html
because the only public user of the architecture is the many-years-dead
milkymist project. (The Linux port to lm32 was never merged upstream.)

In commit 4b4d96c776f552e (March 2020) we marked it as 'orphan' in
the MAINTAINERS file, but didn't officially deprecate it. Mark it
deprecated now, with the intention of removing it from QEMU in
mid-2021 before the 6.1 release.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Michael Walle <michael@walle.cc>
Message-id: 20200827113259.25064-1-peter.maydell@linaro.org


  Commit: db1f3afb17269cf2bd86c222e1bced748487ef71
      
https://github.com/qemu/qemu/commit/db1f3afb17269cf2bd86c222e1bced748487ef71
  Author: Aaron Lindsay <aaron@os.amperecomputing.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Count PMU events when MDCR.SPME is set

This check was backwards when introduced in commit
033614c47de78409ad3fb39bb7bd1483b71c6789:

    target/arm: Filter cycle counter based on PMCCFILTR_EL0

Cc: qemu-stable@nongnu.org
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 07fe5bb537d14a867bc0ba7123808b29339a4522
      
https://github.com/qemu/qemu/commit/07fe5bb537d14a867bc0ba7123808b29339a4522
  Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c

  Log Message:
  -----------
  hw/arm: versal-virt: Correct the tx/rx GEM clocks

Correct the GEMs tx/rx clocks to use the 125Mhz fixed-clock.
This matches the setup with the fixed-link 100Mbit PHY.
It also avoids the following warnings from the Linux kernel
driver:

eth0: unable to generate target frequency: 125000000 Hz

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200909174647.662864-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e5a7ba8788056d0fb10b9ff587677ba78ca41ce9
      
https://github.com/qemu/qemu/commit/e5a7ba8788056d0fb10b9ff587677ba78ca41ce9
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M MAINTAINERS
    M hw/arm/Kconfig
    M hw/misc/meson.build
    A hw/misc/npcm7xx_gcr.c
    M hw/misc/trace-events
    A include/hw/misc/npcm7xx_gcr.h

  Log Message:
  -----------
  hw/misc: Add NPCM7xx System Global Control Registers device model

Implement a device model for the System Global Control Registers in the
NPCM730 and NPCM750 BMC SoCs.

This is primarily used to enable SMP boot (the boot ROM spins reading
the SCRPAD register) and DDR memory initialization; other registers are
best effort for now.

The reset values of the MDLR and PWRON registers are determined by the
SoC variant (730 vs 750) and board straps respectively.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-2-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e331f79eb8226d57e73c522b31a21e2a63e96f44
      
https://github.com/qemu/qemu/commit/e331f79eb8226d57e73c522b31a21e2a63e96f44
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/misc/meson.build
    A hw/misc/npcm7xx_clk.c
    M hw/misc/trace-events
    A include/hw/misc/npcm7xx_clk.h

  Log Message:
  -----------
  hw/misc: Add NPCM7xx Clock Controller device model

Enough functionality to boot the Linux kernel has been implemented. This
includes:

  - Correct power-on reset values so the various clock rates can be
    accurately calculated.
  - Clock enables stick around when written.

In addition, a best effort attempt to implement SECCNT and CNTR25M was
made even though I don't think the kernel needs them.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-3-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 85fdd74ff074bf59644131cea9e2ae1f2a8d5fd1
      
https://github.com/qemu/qemu/commit/85fdd74ff074bf59644131cea9e2ae1f2a8d5fd1
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/timer/meson.build
    A hw/timer/npcm7xx_timer.c
    M hw/timer/trace-events
    A include/hw/timer/npcm7xx_timer.h

  Log Message:
  -----------
  hw/timer: Add NPCM7xx Timer device model

The NPCM730 and NPCM750 SoCs have three timer modules each holding five
timers and some shared registers (e.g. interrupt status).

Each timer runs at 25 MHz divided by a prescaler, and counts down from a
configurable initial value to zero. When zero is reached, the interrupt
flag for the timer is set, and the timer is disabled (one-shot mode) or
reloaded from its initial value (periodic mode).

This implementation is sufficient to boot a Linux kernel configured for
NPCM750. Note that the kernel does not seem to actually turn on the
interrupts.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-4-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2d8f048c25ab2b701ea8e14ba5b02d3a8a5c9044
      
https://github.com/qemu/qemu/commit/2d8f048c25ab2b701ea8e14ba5b02d3a8a5c9044
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/arm/Kconfig
    M hw/arm/meson.build
    A hw/arm/npcm7xx.c
    A include/hw/arm/npcm7xx.h

  Log Message:
  -----------
  hw/arm: Add NPCM730 and NPCM750 SoC models

The Nuvoton NPCM7xx SoC family are used to implement Baseboard
Management Controllers in servers. While the family includes four SoCs,
this patch implements limited support for two of them: NPCM730 (targeted
for Data Center applications) and NPCM750 (targeted for Enterprise
applications).

This patch includes little more than the bare minimum needed to boot a
Linux kernel built with NPCM7xx support in direct-kernel mode:

  - Two Cortex-A9 CPU cores with built-in periperhals.
  - Global Configuration Registers.
  - Clock Management.
  - 3 Timer Modules with 5 timers each.
  - 4 serial ports.

The chips themselves have a lot more features, some of which will be
added to the model at a later stage.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-5-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b773acf4a6326c4e81ad91cce9376abdd81dff17
      
https://github.com/qemu/qemu/commit/b773acf4a6326c4e81ad91cce9376abdd81dff17
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/arm/meson.build
    A hw/arm/npcm7xx_boards.c
    M include/hw/arm/npcm7xx.h

  Log Message:
  -----------
  hw/arm: Add two NPCM7xx-based machines

This adds two new machines, both supported by OpenBMC:

  - npcm750-evb: Nuvoton NPCM750 Evaluation Board.
  - quanta-gsj: A board with a NPCM730 chip.

They rely on the NPCM7xx SoC device to do the heavy lifting. They are
almost completely identical at the moment, apart from the SoC type,
which currently only changes the reset contents of one register
(GCR.MDLR), but they might grow apart a bit more as more functionality
is added.

Both machines can boot the Linux kernel into /bin/sh.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-6-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d1cb5eda67a0a6188608bef6372fd046fc447bf1
      
https://github.com/qemu/qemu/commit/d1cb5eda67a0a6188608bef6372fd046fc447bf1
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M .gitmodules
    M MAINTAINERS
    M pc-bios/README
    M pc-bios/meson.build
    A pc-bios/npcm7xx_bootrom.bin
    M roms/Makefile
    A roms/vbootrom

  Log Message:
  -----------
  roms: Add virtual Boot ROM for NPCM7xx SoCs

This is a minimalistic boot ROM written specifically for use with QEMU.
It supports loading the second-stage loader from SPI flash into RAM, SMP
boot, and not much else.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-7-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4e89ccd685a381981c9b295888eb269b67c3320b
      
https://github.com/qemu/qemu/commit/4e89ccd685a381981c9b295888eb269b67c3320b
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/arm/npcm7xx_boards.c

  Log Message:
  -----------
  hw/arm: Load -bios image as a boot ROM for npcm7xx

If a -bios option is specified on the command line, load the image into
the internal ROM memory region, which contains the first instructions
run by the CPU after reset.

If -bios is not specified, the vbootrom included with qemu is loaded by
default.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-8-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c752bb079beb57a8527e55859ce4c416fb1663c3
      
https://github.com/qemu/qemu/commit/c752bb079beb57a8527e55859ce4c416fb1663c3
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/arm/npcm7xx.c
    M hw/nvram/meson.build
    A hw/nvram/npcm7xx_otp.c
    M include/hw/arm/npcm7xx.h
    A include/hw/nvram/npcm7xx_otp.h

  Log Message:
  -----------
  hw/nvram: NPCM7xx OTP device model

This supports reading and writing OTP fuses and keys. Only fuse reading
has been tested. Protection is not implemented.

Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-9-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1351f892467bd8d9655b43b8fbf10a8d08890612
      
https://github.com/qemu/qemu/commit/1351f892467bd8d9655b43b8fbf10a8d08890612
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/arm/npcm7xx.c
    M hw/mem/meson.build
    A hw/mem/npcm7xx_mc.c
    M include/hw/arm/npcm7xx.h
    A include/hw/mem/npcm7xx_mc.h

  Log Message:
  -----------
  hw/mem: Stubbed out NPCM7xx Memory Controller model

This just implements the bare minimum to cause the boot block to skip
memory initialization.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-10-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b821242c7b3b174bbf7c01a19c93c4e52fedab5d
      
https://github.com/qemu/qemu/commit/b821242c7b3b174bbf7c01a19c93c4e52fedab5d
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/arm/Kconfig
    M hw/arm/npcm7xx.c
    M hw/ssi/meson.build
    A hw/ssi/npcm7xx_fiu.c
    M hw/ssi/trace-events
    M include/hw/arm/npcm7xx.h
    A include/hw/ssi/npcm7xx_fiu.h

  Log Message:
  -----------
  hw/ssi: NPCM7xx Flash Interface Unit device model

This implements a device model for the NPCM7xx SPI flash controller.

Direct reads and writes, and user-mode transactions have been tested in
various modes. Protection features are not implemented yet.

All the FIU instances are available in the SoC's address space,
regardless of whether or not they're connected to actual flash chips.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-11-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0eb73f23461fb468667b66de61632be1c2462a3a
      
https://github.com/qemu/qemu/commit/0eb73f23461fb468667b66de61632be1c2462a3a
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/arm/npcm7xx_boards.c

  Log Message:
  -----------
  hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj

This allows these NPCM7xx-based boards to boot from a flash image, e.g.
one built with OpenBMC. For example like this:

IMAGE=${OPENBMC}/build/tmp/deploy/images/gsj/image-bmc
qemu-system-arm -machine quanta-gsj -nographic \
        -drive file=${IMAGE},if=mtd,bus=0,unit=0,format=raw,snapshot=on

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200911052101.2602693-12-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2ddae9cc042408f75c5d5fd3bfc3d927707700d2
      
https://github.com/qemu/qemu/commit/2ddae9cc042408f75c5d5fd3bfc3d927707700d2
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M hw/arm/npcm7xx.c
    M include/hw/arm/npcm7xx.h

  Log Message:
  -----------
  hw/arm/npcm7xx: add board setup stub for CPU and UART clocks

When booting directly into a kernel, bypassing the boot loader, the CPU and
UART clocks are not set up correctly. This makes the system appear very
slow, and causes the initrd boot test to fail when optimization is off.

The UART clock must run at 24 MHz. The default 25 MHz reference clock
cannot achieve this, so switch to PLL2/2 @ 480 MHz, which works
perfectly with the default /20 divider.

The CPU clock should run at 800 MHz, so switch it to PLL1/2. PLL1 runs
at 800 MHz by default, so we need to double the feedback divider as well
to make it run at 1600 MHz (so PLL1/2 runs at 800 MHz).

We don't bother checking for PLL lock because we know our emulated PLLs
lock instantly.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-13-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 82c703fea4a45dd509685030ae769fe25462f486
      
https://github.com/qemu/qemu/commit/82c703fea4a45dd509685030ae769fe25462f486
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    A docs/system/arm/nuvoton.rst
    M docs/system/target-arm.rst

  Log Message:
  -----------
  docs/system: Add Nuvoton machine documentation

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-14-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4fe986dd4480308ecf07200cfbd3c3d494a0f639
      
https://github.com/qemu/qemu/commit/4fe986dd4480308ecf07200cfbd3c3d494a0f639
  Author: Havard Skinnemoen <hskinnemoen@google.com>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M tests/acceptance/boot_linux_console.py

  Log Message:
  -----------
  tests/acceptance: console boot tests for quanta-gsj

This adds two acceptance tests for the quanta-gsj machine.

One test downloads a lightly patched openbmc flash image from github and
verifies that it boots all the way to the login prompt.

The other test downloads a kernel, initrd and dtb built from the same
openbmc source and verifies that the kernel detects all CPUs and boots
to the point where it can't find the root filesystem (because we have no
flash image in this case).

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-15-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2d2c73d0e3d504a61f868e46e6abd5643f38091b
      
https://github.com/qemu/qemu/commit/2d2c73d0e3d504a61f868e46e6abd5643f38091b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-14 (Mon, 14 Sep 2020)

  Changed paths:
    M .gitmodules
    M MAINTAINERS
    M configure
    M default-configs/arm-softmmu.mak
    M docs/system/arm/mps2.rst
    A docs/system/arm/nuvoton.rst
    M docs/system/deprecated.rst
    M docs/system/target-arm.rst
    M hw/arm/Kconfig
    M hw/arm/meson.build
    M hw/arm/mps2.c
    A hw/arm/npcm7xx.c
    A hw/arm/npcm7xx_boards.c
    M hw/arm/xlnx-versal-virt.c
    M hw/mem/meson.build
    A hw/mem/npcm7xx_mc.c
    M hw/misc/a9scu.c
    M hw/misc/meson.build
    A hw/misc/npcm7xx_clk.c
    A hw/misc/npcm7xx_gcr.c
    M hw/misc/trace-events
    M hw/nvram/meson.build
    A hw/nvram/npcm7xx_otp.c
    M hw/ssi/meson.build
    A hw/ssi/npcm7xx_fiu.c
    M hw/ssi/trace-events
    M hw/timer/armv7m_systick.c
    M hw/timer/meson.build
    A hw/timer/npcm7xx_timer.c
    M hw/timer/trace-events
    A include/hw/arm/npcm7xx.h
    A include/hw/mem/npcm7xx_mc.h
    A include/hw/misc/npcm7xx_clk.h
    A include/hw/misc/npcm7xx_gcr.h
    A include/hw/nvram/npcm7xx_otp.h
    A include/hw/ssi/npcm7xx_fiu.h
    A include/hw/timer/npcm7xx_timer.h
    M pc-bios/README
    M pc-bios/meson.build
    A pc-bios/npcm7xx_bootrom.bin
    M roms/Makefile
    A roms/vbootrom
    M scripts/decodetree.py
    M target/arm/cpu.c
    M target/arm/helper.c
    M target/arm/kvm-consts.h
    M target/arm/kvm.c
    R target/arm/kvm32.c
    M target/arm/kvm_arm.h
    M target/arm/meson.build
    M target/arm/neon-dp.decode
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.c.inc
    M tests/acceptance/boot_linux_console.py
    A tests/decode/succ_ident1.decode

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20200914-1' into staging

 * hw/misc/a9scu: Do not allow invalid CPU count
 * hw/misc/a9scu: Minor cleanups
 * hw/timer/armv7m_systick: assert that board code set system_clock_scale
 * decodetree: Improve identifier matching
 * target/arm: Clean up neon fp insn size field decode
 * target/arm: Remove KVM support for 32-bit Arm hosts
 * hw/arm/mps2: New board models mps2-an386, mps2-an500
 * Deprecate Unicore32 port
 * Deprecate lm32 port
 * target/arm: Count PMU events when MDCR.SPME is set
 * hw/arm: versal-virt: Correct the tx/rx GEM clocks
 * New Nuvoton iBMC board models npcm750-evb, quanta-gsj

# gpg: Signature made Mon 14 Sep 2020 16:02:06 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200914-1: (32 commits)
  tests/acceptance: console boot tests for quanta-gsj
  docs/system: Add Nuvoton machine documentation
  hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
  hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
  hw/ssi: NPCM7xx Flash Interface Unit device model
  hw/mem: Stubbed out NPCM7xx Memory Controller model
  hw/nvram: NPCM7xx OTP device model
  hw/arm: Load -bios image as a boot ROM for npcm7xx
  roms: Add virtual Boot ROM for NPCM7xx SoCs
  hw/arm: Add two NPCM7xx-based machines
  hw/arm: Add NPCM730 and NPCM750 SoC models
  hw/timer: Add NPCM7xx Timer device model
  hw/misc: Add NPCM7xx Clock Controller device model
  hw/misc: Add NPCM7xx System Global Control Registers device model
  hw/arm: versal-virt: Correct the tx/rx GEM clocks
  target/arm: Count PMU events when MDCR.SPME is set
  Deprecate lm32 port
  Deprecate Unicore32 port
  docs/system/arm/mps2.rst: Make board list consistent
  hw/arm/mps2: New board model mps2-an500
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/a68694cd1f3e...2d2c73d0e3d5