[Qemu-commits] [qemu/qemu] 6bbe03: m25p80: Return the JEDEC ID twice for

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[Qemu-commits] [qemu/qemu] 6bbe03: m25p80: Return the JEDEC ID twice for

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 6bbe03: m25p80: Return the JEDEC ID twice for mx25l25635e
Date:	Thu, 03 Sep 2020 09:00:40 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6bbe036f32dcde96c511e0ed93f4ada81342d98e
      
https://github.com/qemu/qemu/commit/6bbe036f32dcde96c511e0ed93f4ada81342d98e
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80: Return the JEDEC ID twice for mx25l25635e

The mx25l25635e returns the JEDEC ID twice when issuing a RDID command :

  [    2.512027] aspeed-smc 1e630000.spi: reading JEDEC ID C2:20:19:C2:20:19

This can break some firmware testing for this condition on the
supermicrox11-bmc machine.

Reported-by: Erik Smit <erik.lucas.smit@gmail.com>
Message-Id: <20200819100956.2216690-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 31fc566f5e9cbe36d4fa12d429eff4c634d681b4
      
https://github.com/qemu/qemu/commit/31fc566f5e9cbe36d4fa12d429eff4c634d681b4
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80: Add support for n25q512ax3

Datasheet available here :

https://www.micron.com/-/media/client/global/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_512mb_1ce_3v_65nm.pdf

Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 740bc3a7e610a2a0daea9af9fd7f45d5e9ed78cc
      
https://github.com/qemu/qemu/commit/740bc3a7e610a2a0daea9af9fd7f45d5e9ed78cc
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/misc/aspeed_scu.c

  Log Message:
  -----------
  aspeed/scu: Fix valid access size on AST2400

The read access size of the SCU registers can be 1/2/4 bytes and write
is 4 bytes and all Aspeed models would need a .valid.accepts() handler.

For the moment, set the min access size to 1 byte to cover both read
and write operations on the AST2400 but keep the min access size of
the other SoCs to 4 bytes as this is an unusual access size.

This fixes support for some old firmware doing 2 bytes reads on the
AST2400 SoC.

Reported-by: Erik Smit <erik.lucas.smit@gmail.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 40a38df55e07cfc5929ea36c73affcedd5b9e726
      
https://github.com/qemu/qemu/commit/40a38df55e07cfc5929ea36c73affcedd5b9e726
  Author: Erik Smit <erik.lucas.smit@gmail.com>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  hw/arm/aspeed: Add board model for Supermicro X11 BMC

The BMC Firmware can be downloaded from :

  https://www.supermicro.com/en/products/motherboard/X11SSL-F

Signed-off-by: Erik Smit <erik.lucas.smit@gmail.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: Prettified Erik's name in email
       Modified commit log ]
Message-Id: <20200715173418.186-1-erik.lucas.smit@gmail.com>
Message-Id: <20200819100956.2216690-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 0d3119edd026adde74aeddbb67c20a7822dea86d
      
https://github.com/qemu/qemu/commit/0d3119edd026adde74aeddbb67c20a7822dea86d
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: Fix MemoryRegionOps definition

Unaligned access support is a leftover from the initial commit. There
is no such need on this device register mapping. Remove it.

Cc: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 9b9624714c979e05bb99065966c362b0315b490a
      
https://github.com/qemu/qemu/commit/9b9624714c979e05bb99065966c362b0315b490a
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: Fix max_slaves of the legacy SMC device

The legacy controller only has one slave.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: f31e8f1318384a680db7280f999c01ae3ef9591c
      
https://github.com/qemu/qemu/commit/f31e8f1318384a680db7280f999c01ae3ef9591c
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/sd/aspeed_sdhci.c

  Log Message:
  -----------
  aspeed/sdhci: Fix reset sequence

BIT(0) of the ASPEED_SDHCI_INFO register is set by SW and polled until
the bit is cleared by HW.

Use the number of supported slots to define the default value of this
register (The AST2600 eMMC Controller only has one). Fix the reset
sequence by clearing automatically the RESET bit.

Cc: Eddie James <eajames@linux.ibm.com>
Fixes: 2bea128c3d0b ("hw/sd/aspeed_sdhci: New device")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 39161476abaa8913299df811b171735a81360bb2
      
https://github.com/qemu/qemu/commit/39161476abaa8913299df811b171735a81360bb2
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/net/ftgmac100.c

  Log Message:
  -----------
  ftgmac100: Fix registers that can be read

Receive Ring Base Address Register (RXR_BADR) and the Normal Priority
Transmit Receive Ring Base Address Register (NPTXR_BADR) can also be
read.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: dcf5137696b25fd71a9377a66a7bee0fe338a42d
      
https://github.com/qemu/qemu/commit/dcf5137696b25fd71a9377a66a7bee0fe338a42d
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/net/ftgmac100.c

  Log Message:
  -----------
  ftgmac100: Fix interrupt status "Packet transmitted on ethernet"

The second field of the TX descriptor has a set of flags to choose
when the transmit interrupt is raised : after the packet has been sent
on the ethernet or after it has been moved into the TX FIFO. But we
don't model that today.

Simply raise the "Packet transmitted on ethernet" interrupt status bit
as soon as the packet is sent by QEMU.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: cf9f48d323cee4f3fc93ea8c292ecea8115b0eef
      
https://github.com/qemu/qemu/commit/cf9f48d323cee4f3fc93ea8c292ecea8115b0eef
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/net/ftgmac100.c

  Log Message:
  -----------
  ftgmac100: Fix interrupt status "Packet moved to RX FIFO"

As we don't model the RX or TX FIFO, raise the "Packet moved to RX
FIFO" interrupt status bit as soon as we are handling a RX packet.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-12-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 9c30f092a0e2a05aa37a4f22d3109b9913a6caea
      
https://github.com/qemu/qemu/commit/9c30f092a0e2a05aa37a4f22d3109b9913a6caea
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/net/ftgmac100.c

  Log Message:
  -----------
  ftgmac100: Change interrupt status when a DMA error occurs

The model uses today the "Normal priority transmit buffer unavailable"
interrupt status which it is not appropriate. According to the Aspeed
specs, no interrupts are raised in that case. An "AHB error" status
seems like a better modeling choice for all implementations since it
is covered by the Linux kernel.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-13-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: af6d66e23557a36491a06857a447d016f6cf9f33
      
https://github.com/qemu/qemu/commit/af6d66e23557a36491a06857a447d016f6cf9f33
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/net/ftgmac100.c

  Log Message:
  -----------
  ftgmac100: Check for invalid len and address before doing a DMA transfer

According to the Aspeed specs, no interrupts are raised in that case
but a "Tx-packets lost" status seems like a good modeling choice for
all implementations. It is covered by the Linux kernel.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-14-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: c2ab73fcbe79e0c751ab44cb6f42672f37a060e7
      
https://github.com/qemu/qemu/commit/c2ab73fcbe79e0c751ab44cb6f42672f37a060e7
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/net/ftgmac100.c

  Log Message:
  -----------
  ftgmac100: Fix integer overflow in ftgmac100_do_tx()

When inserting the VLAN tag in packets, memmove() can generate an
integer overflow for packets whose length is less than 12 bytes.

Move the VLAN insertion when the last segment of the frame is reached
and check length against the size of the ethernet header (14 bytes) to
avoid the crash. Return FTGMAC100_INT_XPKT_LOST status if the frame is
too small. This seems like a good modeling choice even if Aspeed does
not specify anything in that case.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>
Cc: Mauro Matteo Cascella <mcascell@redhat.com>
Reported-by: Ziming Zhang <ezrakiez@gmail.com>
Message-Id: <20200819100956.2216690-15-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: e0059c8883944605d1f5c4dc9c60a881c4b3be39
      
https://github.com/qemu/qemu/commit/e0059c8883944605d1f5c4dc9c60a881c4b3be39
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/net/ftgmac100.c

  Log Message:
  -----------
  ftgmac100: Improve software reset

The software reset of the MAC needs a finer granularity. Some settings
in MACCR are kept.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>
Fixes: bd44300d1afc ("net: add FTGMAC100 support")
Message-Id: <20200819100956.2216690-16-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 14c179541bbf083f4b215ddb389828ad8b9d0b28
      
https://github.com/qemu/qemu/commit/14c179541bbf083f4b215ddb389828ad8b9d0b28
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/misc/aspeed_scu.c
    M hw/misc/aspeed_sdmc.c
    M include/hw/misc/aspeed_sdmc.h

  Log Message:
  -----------
  aspeed/sdmc: Perform memory training

This allows qemu to run the "normal" power on reset boot path through
u-boot, where the DDR is trained.

An enhancement would be to have the SCU bit stick across qemu reboots,
but be unset on initial boot.

Proper modelling would be to discard all writes to the phy setting regs
at offset 0x100 - 0x400 and to model the phy status regs at offset
0x400.

The status regs model would only need to account for offets 0x00,
0x50, 0x68 and 0x7c.

Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: checkpatch fixes ]
Message-Id: <20200819100956.2216690-17-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 57de884d551dda5b58548168e6a88f428dd59524
      
https://github.com/qemu/qemu/commit/57de884d551dda5b58548168e6a88f428dd59524
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/misc/aspeed_sdmc.c

  Log Message:
  -----------
  aspeed/sdmc: Allow writes to unprotected registers

A subset of registers are not protected by the lock behaviour, so allow
unconditionally writing to those.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-18-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 9951133e467e1936180263907d51ef42237c7851
      
https://github.com/qemu/qemu/commit/9951133e467e1936180263907d51ef42237c7851
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/misc/aspeed_sdmc.c

  Log Message:
  -----------
  aspeed/sdmc: Simplify calculation of RAM bits

Changes in commit 533eb415df2e ("arm/aspeed: actually check RAM size")
introduced a 'valid_ram_sizes' array which can be used to compute the
associated bit field value encoding the RAM size. The field is simply
the index of the array.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-19-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 1f240ca1eb866749b884632483e53c9c04c835f5
      
https://github.com/qemu/qemu/commit/1f240ca1eb866749b884632483e53c9c04c835f5
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: Open AHB window of the second chip of the AST2600 FMC controller

This change works around the HW default values to be able to test the
Tacoma board with -kernel command line option. This was required when
we had both flash chips enabled in the device tree, otherwise Linux
would fail to probe the entire controller leaving it with no rootfs.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20200819100956.2216690-20-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: d98c48a19fe8f9e9627802b5b7de16189632d5c9
      
https://github.com/qemu/qemu/commit/d98c48a19fe8f9e9627802b5b7de16189632d5c9
  Author: Igor Kononenko <i.kononenko@yadro.com>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M include/hw/misc/aspeed_scu.h

  Log Message:
  -----------
  arm: aspeed: add strap define `25HZ` of AST2500

Provide a definition for the "25Hz reference clock input mode" strap

Signed-off-by: Igor Kononenko <i.kononenko@yadro.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200811203502.20382-1-i.kononenko@yadro.com>
Message-Id: <20200819100956.2216690-21-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: ddd8ab19749b8639fc08bfe4d0df0204eec049f0
      
https://github.com/qemu/qemu/commit/ddd8ab19749b8639fc08bfe4d0df0204eec049f0
  Author: Igor Kononenko <i.kononenko@yadro.com>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  hw: add a number of SPI-flash's of m25p80 family

Support a following SPI flashes:
* mx66l51235f
* mt25ql512ab

Signed-off-by: Igor Kononenko <i.kononenko@yadro.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200811203724.20699-1-i.kononenko@yadro.com>
Message-Id: <20200819100956.2216690-22-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 3dd23a4fb8fd72d2220a90a809f213999ffe7f3a
      
https://github.com/qemu/qemu/commit/3dd23a4fb8fd72d2220a90a809f213999ffe7f3a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-03 (Thu, 03 Sep 2020)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/block/m25p80.c
    M hw/misc/aspeed_scu.c
    M hw/misc/aspeed_sdmc.c
    M hw/net/ftgmac100.c
    M hw/sd/aspeed_sdhci.c
    M hw/ssi/aspeed_smc.c
    M include/hw/misc/aspeed_scu.h
    M include/hw/misc/aspeed_sdmc.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20200901' 
into staging

Various fixes of Aspeed machines :

* New Supermicro X11 BMC machine (Erik)
* Fixed valid access size on AST2400 SCU
* Improved robustness of the ftgmac100 model.
* New flash models in m25p80 (Igor)
* Fixed reset sequence of SDHCI/eMMC controllers
* Improved support of the AST2600 SDMC  (Joel)
* Couple of SMC cleanups

# gpg: Signature made Tue 01 Sep 2020 13:39:20 BST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* remotes/legoater/tags/pull-aspeed-20200901:
  hw: add a number of SPI-flash's of m25p80 family
  arm: aspeed: add strap define `25HZ` of AST2500
  aspeed/smc: Open AHB window of the second chip of the AST2600 FMC controller
  aspeed/sdmc: Simplify calculation of RAM bits
  aspeed/sdmc: Allow writes to unprotected registers
  aspeed/sdmc: Perform memory training
  ftgmac100: Improve software reset
  ftgmac100: Fix integer overflow in ftgmac100_do_tx()
  ftgmac100: Check for invalid len and address before doing a DMA transfer
  ftgmac100: Change interrupt status when a DMA error occurs
  ftgmac100: Fix interrupt status "Packet moved to RX FIFO"
  ftgmac100: Fix interrupt status "Packet transmitted on ethernet"
  ftgmac100: Fix registers that can be read
  aspeed/sdhci: Fix reset sequence
  aspeed/smc: Fix max_slaves of the legacy SMC device
  aspeed/smc: Fix MemoryRegionOps definition
  hw/arm/aspeed: Add board model for Supermicro X11 BMC
  aspeed/scu: Fix valid access size on AST2400
  m25p80: Add support for n25q512ax3
  m25p80: Return the JEDEC ID twice for mx25l25635e

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


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