[Qemu-commits] [qemu/qemu] b684e4: target/arm: Remove local definitions of float cons...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: b684e49a17da39539b0ac6e4c4c98b28b38feb76
      
https://github.com/qemu/qemu/commit/b684e49a17da39539b0ac6e4c4c98b28b38feb76
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/translate-sve.c
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Remove local definitions of float constants

In several places the target/arm code defines local float constants
for 2, 3 and 1.5, which are also provided by include/fpu/softfloat.h.
Remove the unnecessary local duplicate versions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-2-peter.maydell@linaro.org


  Commit: 02bc236d0131a666d4ac2bb7197bbad2897c336a
      
https://github.com/qemu/qemu/commit/02bc236d0131a666d4ac2bb7197bbad2897c336a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Use correct ID register check for aa32_fp16_arith

The aa32_fp16_arith feature check function currently looks at the
AArch64 ID_AA64PFR0 register. This is (as the comment notes) not
correct. The bogus check was put in mostly to allow testing of the
fp16 variants of the VCMLA instructions and it was something of
a mistake that we allowed them to exist in master.

Switch the feature check function to testing VMFR1.FPHP, which is
what it ought to be.

This will remove emulation of the VCMLA and VCADD insns from
AArch32 code running on an AArch64 '-cpu max' using system emulation.
(They were never enabled for aarch32 linux-user and system-emulation.)
Since we weren't advertising their existence via the AArch32 ID
register, well-behaved guests wouldn't have been using them anyway.

Once we have implemented all the AArch32 support for the FP16 extension
we will advertise it in the MVFR1 ID register field, which will reenable
these insns along with all the others.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-3-peter.maydell@linaro.org


  Commit: 120a0eb3ea23a5b06fae2f3daebd46a4035864cf
      
https://github.com/qemu/qemu/commit/120a0eb3ea23a5b06fae2f3daebd46a4035864cf
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp-uncond.decode
    M target/arm/vfp.decode
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Implement VFP fp16 for VFP_BINOP operations

Implmeent VFP fp16 support for simple binary-operator VFP insns VADD,
VSUB, VMUL, VDIV, VMINNM and VMAXNM:

 * make the VFP_BINOP() macro generate float16 helpers as well as
   float32 and float64
 * implement a do_vfp_3op_hp() function similar to the existing
   do_vfp_3op_sp()
 * add decode for the half-precision insn patterns

Note that the VFP_BINOP macro use creates a couple of unused helper
functions vfp_maxh and vfp_minh, but they're small so it's not worth
splitting the BINOP operations into "needs halfprec" and "no
halfprec" groups.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-4-peter.maydell@linaro.org


  Commit: e7cb0ded52c6d7b86585b09935fe7caeb9e38b69
      
https://github.com/qemu/qemu/commit/e7cb0ded52c6d7b86585b09935fe7caeb9e38b69
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp.decode
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL

Implement fp16 versions of the VFP VMLA, VMLS, VNMLS, VNMLA, VNMUL
instructions. (These are all the remaining ones which we implement
via do_vfp_3op_[hsd]p().)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-5-peter.maydell@linaro.org


  Commit: 2aa8dcfa14558fe2a63ed0496d60b02565c9a225
      
https://github.com/qemu/qemu/commit/2aa8dcfa14558fe2a63ed0496d60b02565c9a225
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc

  Log Message:
  -----------
  target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS

Macroify creation of the trans functions for single and double
precision VFMA, VFMS, VFNMA, VFNMS. The repetition was OK for
two sizes, but we're about to add halfprec and it will get a bit
more than seems reasonable.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-6-peter.maydell@linaro.org


  Commit: 9886fe2834b064a3cf0675a4659942ed547aed42
      
https://github.com/qemu/qemu/commit/9886fe2834b064a3cf0675a4659942ed547aed42
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp.decode
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Implement VFP fp16 for fused-multiply-add

Implement VFP fp16 support for fused multiply-add insns
VFNMA, VFNMS, VFMA, VFMS.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-7-peter.maydell@linaro.org


  Commit: 009a07335b8ff492d940e1eb229a1b0d302c2512
      
https://github.com/qemu/qemu/commit/009a07335b8ff492d940e1eb229a1b0d302c2512
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc

  Log Message:
  -----------
  target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp()

Macroify the uses of do_vfp_2op_sp() and do_vfp_2op_dp(); this will
make it easier to add the halfprec support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-8-peter.maydell@linaro.org


  Commit: ce2d65a5d191380756cdac7a1fd1ba76bd1621cf
      
https://github.com/qemu/qemu/commit/ce2d65a5d191380756cdac7a1fd1ba76bd1621cf
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp.decode
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT

Implement VFP fp16 for VABS, VNEG and VSQRT. This is all
the fp16 insns that use the DO_VFP_2OP macro, because there
is no fp16 version of VMOV_reg.

Notes:
 * the gen_helper_vfp_negh already exists as we needed to create
   it for the fp16 multiply-add insns
 * as usual we need to use the f16 version of the fp_status;
   this is only relevant for VSQRT

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-9-peter.maydell@linaro.org


  Commit: 28c28728e53c9f4c13a5cd50f313788c7ec2f9ad
      
https://github.com/qemu/qemu/commit/28c28728e53c9f4c13a5cd50f313788c7ec2f9ad
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp.decode

  Log Message:
  -----------
  target/arm: Implement VFP fp16 for VMOV immediate

Implement VFP fp16 support for the VMOV immediate insn.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-10-peter.maydell@linaro.org


  Commit: 1b88b054c5b201e8581114d29527c6a5a7e088c9
      
https://github.com/qemu/qemu/commit/1b88b054c5b201e8581114d29527c6a5a7e088c9
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp.decode
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Implement VFP fp16 VCMP

Implement fp16 version of VCMP.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-11-peter.maydell@linaro.org


  Commit: 274afbb121107b8aaeaa11b3e7904d5f8ae38a94
      
https://github.com/qemu/qemu/commit/274afbb121107b8aaeaa11b3e7904d5f8ae38a94
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp.decode

  Log Message:
  -----------
  target/arm: Implement VFP fp16 VLDR and VSTR

Implement the fp16 versions of the VFP VLDR/VSTR (immediate).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-12-peter.maydell@linaro.org


  Commit: 0094e9f475a5a742d10d2f1e1beceea82b69f982
      
https://github.com/qemu/qemu/commit/0094e9f475a5a742d10d2f1e1beceea82b69f982
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp.decode

  Log Message:
  -----------
  target/arm: Implement VFP fp16 VCVT between float and integer

Implement the fp16 versions of the VFP VCVT instruction forms which
convert between floating point and integer.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-13-peter.maydell@linaro.org


  Commit: 5366f6ad7da4f6def2733ec7ee24495430256839
      
https://github.com/qemu/qemu/commit/5366f6ad7da4f6def2733ec7ee24495430256839
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Make VFP_CONV_FIX macros take separate float type and float size

Currently the VFP_CONV_FIX macros take a single fsz argument for the
size of the float type, which is used both to select the name of
the functions to call (eg float32_is_any_nan()) and also for the
type to use for the float inputs and outputs (eg float32).

Separate these into fsz and ftype arguments, so that we can use them
for fp16, which uses 'float16' in the function names but is still
passing inputs and outputs in a 32-bit sized type.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-14-peter.maydell@linaro.org


  Commit: 414ba270c4fb758d987adf37ae9bfe531715c604
      
https://github.com/qemu/qemu/commit/414ba270c4fb758d987adf37ae9bfe531715c604
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Use macros instead of open-coding fp16 conversion helpers

Now the VFP_CONV_FIX macros can handle fp16's distinction between the
width of the operation and the width of the type used to pass operands,
use the macros rather than the open-coded functions.

This creates an extra six helper functions, all of which we are going
to need for the AArch32 VFP fp16 instructions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-15-peter.maydell@linaro.org


  Commit: a149e2de0b63e3906729ed1d3df7d9ecdb6de5e6
      
https://github.com/qemu/qemu/commit/a149e2de0b63e3906729ed1d3df7d9ecdb6de5e6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp.decode

  Log Message:
  -----------
  target/arm: Implement VFP fp16 VCVT between float and fixed-point

Implement the fp16 versions of the VFP VCVT instruction forms which
convert between floating point and fixed-point.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-16-peter.maydell@linaro.org


  Commit: c505bc6a9d50a48f9d89d6cf930e863838a5b367
      
https://github.com/qemu/qemu/commit/c505bc6a9d50a48f9d89d6cf930e863838a5b367
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp-uncond.decode

  Log Message:
  -----------
  target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode

Implement the fp16 versions of the VFP VCVT instruction forms
which convert between floating point and integer with a specified
rounding mode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-17-peter.maydell@linaro.org


  Commit: 11e78fecdf2d605cfed33aa09bbcf0cc4fb95886
      
https://github.com/qemu/qemu/commit/11e78fecdf2d605cfed33aa09bbcf0cc4fb95886
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp-uncond.decode

  Log Message:
  -----------
  target/arm: Implement VFP fp16 VSEL

Implement the fp16 versions of the VFP VSEL instruction.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-18-peter.maydell@linaro.org


  Commit: 0a6f4b4cb338665b81ad824d9a6868932461b7f7
      
https://github.com/qemu/qemu/commit/0a6f4b4cb338665b81ad824d9a6868932461b7f7
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp-uncond.decode
    M target/arm/vfp.decode
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Implement VFP fp16 VRINT*

Implement the fp16 version of the VFP VRINT* insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-19-peter.maydell@linaro.org


  Commit: e4875e3bcc3a9c54d7e074c8f51e04c2e6364e2e
      
https://github.com/qemu/qemu/commit/e4875e3bcc3a9c54d7e074c8f51e04c2e6364e2e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp-uncond.decode

  Log Message:
  -----------
  target/arm: Implement new VFP fp16 insn VINS

The fp16 extension includes a new instruction VINS, which copies the
lower 16 bits of a 32-bit source VFP register into the upper 16 bits
of the destination.  Implement it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-20-peter.maydell@linaro.org


  Commit: f61e5c43b86907dea17f431b528d806659d62bcb
      
https://github.com/qemu/qemu/commit/f61e5c43b86907dea17f431b528d806659d62bcb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp-uncond.decode

  Log Message:
  -----------
  target/arm: Implement new VFP fp16 insn VMOVX

The fp16 extension includes a new instruction VMOVX, which copies the
upper 16 bits of a 32-bit source VFP register into the lower 16
bits of the destination and zeroes the high half of the destination.
Implement it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-21-peter.maydell@linaro.org


  Commit: 46a4b854525cb9f34a611f6ada6cdff1eab0ac2d
      
https://github.com/qemu/qemu/commit/46a4b854525cb9f34a611f6ada6cdff1eab0ac2d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-vfp.c.inc
    M target/arm/vfp.decode

  Log Message:
  -----------
  target/arm: Implement VFP fp16 VMOV between gp and halfprec registers

Implement the VFP fp16 variant of VMOV that transfers a 16-bit
value between a general purpose register and a VFP register.

Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later
only we have no need to replicate the old "updates CPSR.NZCV"
behaviour that the singleprec version of this insn does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-22-peter.maydell@linaro.org


  Commit: e4a6d4a69e239becfd83bdcd996476e7b8e1138d
      
https://github.com/qemu/qemu/commit/e4a6d4a69e239becfd83bdcd996476e7b8e1138d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL

Implement FP16 support for the Neon insns which use the DO_3S_FP_GVEC
macro: VADD, VSUB, VABD, VMUL.

For VABD this requires us to implement a new gvec_fabd_h helper
using the machinery we have already for the other helpers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-24-peter.maydell@linaro.org


  Commit: 4a15d9a3b39d4d161d7e03dfcf52e9f214eef0b8
      
https://github.com/qemu/qemu/commit/4a15d9a3b39d4d161d7e03dfcf52e9f214eef0b8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-neon.c.inc

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec

We already have gvec helpers for floating point VRECPE and
VRQSRTE, so convert the Neon decoder to use them and
add the fp16 support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-25-peter.maydell@linaro.org


  Commit: 2b70d8cd09f5450c15788acd24f6f8bc4116c395
      
https://github.com/qemu/qemu/commit/2b70d8cd09f5450c15788acd24f6f8bc4116c395
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-neon.c.inc

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VABS, VNEG of floats

Rewrite Neon VABS/VNEG of floats to use gvec logical AND and XOR, so
that we can implement the fp16 version of the insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-26-peter.maydell@linaro.org


  Commit: ad505db233b89b7fd4b5a98b6f0e8ac8d05b11db
      
https://github.com/qemu/qemu/commit/ad505db233b89b7fd4b5a98b6f0e8ac8d05b11db
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons

Convert the Neon floating-point vector comparison ops VCEQ,
VCGE and VCGT over to using a gvec helper and use this to
implement the fp16 case.

(We put the float16_ceq() etc functions above the DO_2OP()
macro definition because later when we convert the
compare-against-zero instructions we'll want their
definitions to be visible at that point in the source file.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-27-peter.maydell@linaro.org


  Commit: bb2741da186ebaebc7d5189372be4401e1ff9972
      
https://github.com/qemu/qemu/commit/bb2741da186ebaebc7d5189372be4401e1ff9972
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for VACGE, VACGT

Convert the neon floating-point vector absolute comparison ops
VACGE and VACGT over to using a gvec hepler and use this to
implement the fp16 case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-28-peter.maydell@linaro.org


  Commit: e43268c54b6cbcb197d179409df7126e81f8cd52
      
https://github.com/qemu/qemu/commit/e43268c54b6cbcb197d179409df7126e81f8cd52
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VMAX, VMIN

Convert the Neon float-point VMAX and VMIN insns over to using
a gvec helper, and use this to implement the fp16 case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-29-peter.maydell@linaro.org


  Commit: e22705bb941d82d6c2a09e8b2031084326902be3
      
https://github.com/qemu/qemu/commit/e22705bb941d82d6c2a09e8b2031084326902be3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VMAXNM, VMINNM

Convert the Neon floating point VMAXNM and VMINNM insns to
using a gvec helper and use this to implement the fp16 case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-30-peter.maydell@linaro.org


  Commit: e5adc70665ecaf4009c2fb8d66775ea718a85abd
      
https://github.com/qemu/qemu/commit/e5adc70665ecaf4009c2fb8d66775ea718a85abd
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VMLA, VMLS operations

Convert the Neon floating-point VMLA and VMLS insns over to using a
gvec helper, and use this to implement the fp16 case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-31-peter.maydell@linaro.org


  Commit: cf722d75b329ef3f86b869e7e68cbfb1607b3bde
      
https://github.com/qemu/qemu/commit/cf722d75b329ef3f86b869e7e68cbfb1607b3bde
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VFMA, VMFS

Convert the neon floating-point vector operations VFMA and VFMS
to use a gvec helper, and use this to implement the fp16 case.

This is the last use of do_3same_fp() so we can now delete
that function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-32-peter.maydell@linaro.org


  Commit: 635187aaa92f21ab001e2868e803b3c5460261ca
      
https://github.com/qemu/qemu/commit/635187aaa92f21ab001e2868e803b3c5460261ca
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon fp compare-vs-0

Convert the neon floating-point vector compare-vs-0 insns VCEQ0,
VCGT0, VCLE0, VCGE0 and VCLT0 to use a gvec helper, and use this to
implement the fp16 case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-33-peter.maydell@linaro.org


  Commit: ac8c62c4e5a3f24e6d47f52ec1bfb20994caefa5
      
https://github.com/qemu/qemu/commit/ac8c62c4e5a3f24e6d47f52ec1bfb20994caefa5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VRECPS

Convert the Neon VRECPS insn to using a gvec helper, and
use this to implement the fp16 case.

The phrasing of the new float32_recps_nf() is slightly different from
the old recps_f32() so that it parallels the f16 version; for f16 we
can't assume that flush-to-zero is always enabled.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-34-peter.maydell@linaro.org


  Commit: 40fde72dda2da8d55b820fa6c5efd85814be2023
      
https://github.com/qemu/qemu/commit/40fde72dda2da8d55b820fa6c5efd85814be2023
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VRSQRTS

Convert the Neon VRSQRTS insn to using a gvec helper,
and use this to implement the fp16 case.

As with VRECPS, we adjust the phrasing of the new implementation
slightly so that the fp32 version parallels the fp16 one.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-35-peter.maydell@linaro.org


  Commit: 1dc587ee9bfe804406eb3e0bacf47a80644d8abc
      
https://github.com/qemu/qemu/commit/1dc587ee9bfe804406eb3e0bacf47a80644d8abc
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon pairwise fp ops

Convert the Neon pairwise fp ops to use a single gvic-style
helper to do the full operation instead of one helper call
for each 32-bit part. This allows us to use the same
framework to implement the fp16.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-36-peter.maydell@linaro.org


  Commit: 7782a9afec81d1efe23572135c1ed777691ccde5
      
https://github.com/qemu/qemu/commit/7782a9afec81d1efe23572135c1ed777691ccde5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon float-integer VCVT

Convert the Neon float-integer VCVT insns to gvec, and use this
to implement fp16 support for them.

Note that unlike the VFP int<->fp16 VCVT insns we converted
earlier and which convert to/from a 32-bit integer, these
Neon insns convert to/from 16-bit integers. So we can use
the existing vfp conversion helpers for the f32<->u32/i32
case but need to provide our own for f16<->u16/i16.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-37-peter.maydell@linaro.org


  Commit: 7b959c5890deb9a6d71bc6800006a0eae0a84c60
      
https://github.com/qemu/qemu/commit/7b959c5890deb9a6d71bc6800006a0eae0a84c60
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Convert Neon VCVT fixed-point to gvec

Convert the Neon VCVT float<->fixed-point insns to a
gvec style, in preparation for adding fp16 support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-38-peter.maydell@linaro.org


  Commit: 24018cf3990b692b51e50183c5fbd98d17b3fa40
      
https://github.com/qemu/qemu/commit/24018cf3990b692b51e50183c5fbd98d17b3fa40
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VCVT fixed-point

Implement fp16 for the Neon VCVT insns which convert between
float and fixed-point.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-39-peter.maydell@linaro.org


  Commit: ca88a6efdf4ce96b646a896059f9bd324c2cebc4
      
https://github.com/qemu/qemu/commit/ca88a6efdf4ce96b646a896059f9bd324c2cebc4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VCVT with rounding modes

Convert the Neon VCVT with-specified-rounding-mode instructions
to gvec, and use this to implement fp16 support for them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-40-peter.maydell@linaro.org


  Commit: 18725916b1438b54d6d6533980833d2251a20b7c
      
https://github.com/qemu/qemu/commit/18725916b1438b54d6d6533980833d2251a20b7c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode

Convert the Neon VRINT-with-specified-rounding-mode insns to gvec,
and use this to implement the fp16 versions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-41-peter.maydell@linaro.org


  Commit: 23afcdd2511f2a3dc05bed650d27bd25cf9b2a3c
      
https://github.com/qemu/qemu/commit/23afcdd2511f2a3dc05bed650d27bd25cf9b2a3c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-neon.c.inc
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VRINTX

Convert the Neon VRINTX insn to use gvec, and use this to implement
fp16 support for it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-42-peter.maydell@linaro.org


  Commit: d7ce81e553e6789bf27657105b32575668d60b1c
      
https://github.com/qemu/qemu/commit/d7ce81e553e6789bf27657105b32575668d60b1c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations

In the gvec helper functions for indexed operations, for AArch32
Neon the oprsz (total size of the vector) can be less than 16 bytes
if the operation is on a D reg. Since the inner loop in these
helpers always goes from 0 to segment, we must clamp it based
on oprsz to avoid processing a full 16 byte segment when asked to
handle an 8 byte wide vector.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-43-peter.maydell@linaro.org


  Commit: c50d8d144098a8261233ca31b47e3bc487e112fe
      
https://github.com/qemu/qemu/commit/c50d8d144098a8261233ca31b47e3bc487e112fe
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations

Add gvec helpers for doing Neon-style indexed non-fused fp
multiply-and-accumulate operations.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200828183354.27913-44-peter.maydell@linaro.org


  Commit: fc8ae790311882afa3c7816df004daf978c40e9a
      
https://github.com/qemu/qemu/commit/fc8ae790311882afa3c7816df004daf978c40e9a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/translate-neon.c.inc

  Log Message:
  -----------
  target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS

Convert the Neon floating-point VMUL, VMLA and VMLS to use gvec,
and use this to implement fp16 support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-45-peter.maydell@linaro.org


  Commit: 5f07817eb94542e39a419baafa3026b15e8d33f7
      
https://github.com/qemu/qemu/commit/5f07817eb94542e39a419baafa3026b15e8d33f7
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Enable FP16 in '-cpu max'

Set the MVFR1 ID register FPHP and SIMDHP fields to indicate
that our "-cpu max" has v8.2-FP16.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-46-peter.maydell@linaro.org


  Commit: 999f6ebde5d3ee30b03270bc05095bed737b7dab
      
https://github.com/qemu/qemu/commit/999f6ebde5d3ee30b03270bc05095bed737b7dab
  Author: Leif Lindholm <leif@nuviainc.com>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  hw/arm/sbsa-ref: add "reg" property to DT cpu nodes

The sbsa-ref platform uses a minimal device tree to pass amount of memory
as well as number of cpus to the firmware. However, when dumping that
minimal dtb (with -M sbsa-virt,dumpdtb=<file>), the resulting blob
generates a warning when decompiled by dtc due to lack of reg property.

Add a simple reg property per cpu, representing a 64-bit MPIDR_EL1.

This also ends up being cleaner than having the firmware calculating its
own IDs for generating APCI.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200827124335.30586-1-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dccb92b5caee973cb10f3f429741efe5cf747feb
      
https://github.com/qemu/qemu/commit/dccb92b5caee973cb10f3f429741efe5cf747feb
  Author: Graeme Gregory <graeme@nuviainc.com>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/misc/meson.build
    A hw/misc/sbsa_ec.c

  Log Message:
  -----------
  hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref

A difference between sbsa platform and the virt platform is PSCI is
handled by ARM-TF in the sbsa platform. This means that the PSCI code
there needs to communicate some of the platform power changes down
to the qemu code for things like shutdown/reset control.

Space has been left to extend the EC if we find other use cases in
future where ARM-TF and qemu need to communicate.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Tested-by: Leif Lindholm <leif@nuviainc.com>
Message-id: 20200826141952.136164-2-graeme@nuviainc.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3f462bf0f6ea6382dd1502d4eb1fcd33c8e774f5
      
https://github.com/qemu/qemu/commit/3f462bf0f6ea6382dd1502d4eb1fcd33c8e774f5
  Author: Graeme Gregory <graeme@nuviainc.com>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  hw/arm/sbsa-ref : Add embedded controller in secure memory

Add the previously created sbsa-ec device to the sbsa-ref machine in
secure memory so the PSCI implementation in ARM-TF can access it, but
not expose it to non secure firmware or OS except by via ARM-TF.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Tested-by: Leif Lindholm <leif@nuviainc.com>
Message-id: 20200826141952.136164-3-graeme@nuviainc.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8d90bfc5c31ad60f6049dd39be636b06bc00b652
      
https://github.com/qemu/qemu/commit/8d90bfc5c31ad60f6049dd39be636b06bc00b652
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-09-01 (Tue, 01 Sep 2020)

  Changed paths:
    M hw/arm/sbsa-ref.c
    M hw/misc/meson.build
    A hw/misc/sbsa_ec.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper-a64.c
    M target/arm/helper.h
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.c.inc
    M target/arm/translate-sve.c
    M target/arm/translate-vfp.c.inc
    M target/arm/vec_helper.c
    M target/arm/vfp-uncond.decode
    M target/arm/vfp.decode
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200901' 
into staging

target-arm queue:
 * Implement fp16 support for AArch32 VFP and Neon
 * hw/arm/sbsa-ref: add "reg" property to DT cpu nodes
 * hw/arm/sbsa-ref : Add embedded controller in secure memory

# gpg: Signature made Tue 01 Sep 2020 16:17:23 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200901: (47 commits)
  hw/arm/sbsa-ref : Add embedded controller in secure memory
  hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref
  hw/arm/sbsa-ref: add "reg" property to DT cpu nodes
  target/arm: Enable FP16 in '-cpu max'
  target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS
  target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations
  target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations
  target/arm: Implement fp16 for Neon VRINTX
  target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode
  target/arm: Implement fp16 for Neon VCVT with rounding modes
  target/arm: Implement fp16 for Neon VCVT fixed-point
  target/arm: Convert Neon VCVT fixed-point to gvec
  target/arm: Implement fp16 for Neon float-integer VCVT
  target/arm: Implement fp16 for Neon pairwise fp ops
  target/arm: Implement fp16 for Neon VRSQRTS
  target/arm: Implement fp16 for Neon VRECPS
  target/arm: Implement fp16 for Neon fp compare-vs-0
  target/arm: Implement fp16 for Neon VFMA, VMFS
  target/arm: Implement fp16 for Neon VMLA, VMLS operations
  target/arm: Implement fp16 for Neon VMAXNM, VMINNM
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/071a6dba7d4d...8d90bfc5c31a