[Qemu-commits] [qemu/qemu] 870f00: hw/arm/sbsa-ref: fix typo breaking PC

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[Qemu-commits] [qemu/qemu] 870f00: hw/arm/sbsa-ref: fix typo breaking PC

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 870f00: hw/arm/sbsa-ref: fix typo breaking PCIe IRQs
Date:	Fri, 28 Aug 2020 10:46:48 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 870f0051b4ada9a361f7454f833432ae8c06c095
      
https://github.com/qemu/qemu/commit/870f0051b4ada9a361f7454f833432ae8c06c095
  Author: Graeme Gregory <graeme@nuviainc.com>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  hw/arm/sbsa-ref: fix typo breaking PCIe IRQs

Fixing a typo in a previous patch that translated an "i" to a 1
and therefore breaking the allocation of PCIe interrupts. This was
discovered when virtio-net-pci devices ceased to function correctly.

Cc: qemu-stable@nongnu.org
Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the 
machine state")
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200821083853.356490-1-graeme@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bb80ae077ebcc7e0cdc0f7e2ec663896b6103da1
      
https://github.com/qemu/qemu/commit/bb80ae077ebcc7e0cdc0f7e2ec663896b6103da1
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M include/hw/clock.h

  Log Message:
  -----------
  hw/clock: Remove unused clock_init*() functions

clock_init*() inlined funtions are simple wrappers around
clock_set*() and are not used. Remove them in favor of clock_set*().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200806123858.30058-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 15aa2876d9c7181c58305430f726461a2f24cb00
      
https://github.com/qemu/qemu/commit/15aa2876d9c7181c58305430f726461a2f24cb00
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/core/clock.c
    M include/hw/clock.h

  Log Message:
  -----------
  hw/clock: Let clock_set() return boolean value

Let clock_set() return a boolean value whether the clock
has been updated or not.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200806123858.30058-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 96250eab904261b31d9d1ac3abbdb36737635ffa
      
https://github.com/qemu/qemu/commit/96250eab904261b31d9d1ac3abbdb36737635ffa
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M include/hw/clock.h

  Log Message:
  -----------
  hw/clock: Only propagate clock changes if the clock is changed

Avoid propagating the clock change when the clock does not change.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200806123858.30058-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 79ed6fd65026fbdc71c5f2a7a42a80aac0063d94
      
https://github.com/qemu/qemu/commit/79ed6fd65026fbdc71c5f2a7a42a80aac0063d94
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/arm/musicpal.c

  Log Message:
  -----------
  hw/arm/musicpal: Use AddressSpace for DMA transfers

Allow the device to execute the DMA transfers in a different
AddressSpace.

We keep using the system_memory address space, but via the
proper dma_memory_access() API.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200814125533.4047-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0e5aac18bc31dbdfab51f9784240d0c31a4c5579
      
https://github.com/qemu/qemu/commit/0e5aac18bc31dbdfab51f9784240d0c31a4c5579
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Clarify HCR_EL2 ARMCPRegInfo type

In commit ce4afed839 ("target/arm: Implement AArch32 HCR and HCR2")
the HCR_EL2 register has been changed from type NO_RAW (no underlying
state and does not support raw access for state saving/loading) to
type CONST (TCG can assume the value to be constant), removing the
read/write accessors.
We forgot to remove the previous type ARM_CP_NO_RAW. This is not
really a problem since the field is overwritten. However it makes
code review confuse, so remove it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200812111223.7787-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dbf8c32178291169e111a6a9fd7ae17af4a3039d
      
https://github.com/qemu/qemu/commit/dbf8c32178291169e111a6a9fd7ae17af4a3039d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/mte_helper.c

  Log Message:
  -----------
  target/arm: Pass the entire mte descriptor to mte_check_fail

We need more information than just the mmu_idx in order
to create the proper exception syndrome.  Only change the
function signature so far.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200813200816.3037186-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9a4670be7f0734d27bf4058db3becf83cd0cc9d5
      
https://github.com/qemu/qemu/commit/9a4670be7f0734d27bf4058db3becf83cd0cc9d5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/mte_helper.c

  Log Message:
  -----------
  target/arm: Fill in the WnR syndrome bit in mte_check_fail

According to AArch64.TagCheckFault, none of the other ISS values are
provided, so we do not need to go so far as merge_syn_data_abort.
But we were missing the WnR bit.

Tested-by: Andrey Konovalov <andreyknvl@google.com>
Reported-by: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200813200816.3037186-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b3aec952bf11ef54376db96dd673c6a34753b697
      
https://github.com/qemu/qemu/commit/b3aec952bf11ef54376db96dd673c6a34753b697
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/arm/allwinner-a10.c
    M hw/arm/allwinner-h3.c
    M hw/sd/allwinner-sdhost.c
    M include/hw/sd/allwinner-sdhost.h

  Log Message:
  -----------
  hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers

Allow the device to execute the DMA transfers in a different
AddressSpace.

The A10 and H3 SoC keep using the system_memory address space,
but via the proper dma_memory_access() API.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20200814110057.307-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4757cb857934a5e2dcafe1f41e95233f5c0a878d
      
https://github.com/qemu/qemu/commit/4757cb857934a5e2dcafe1f41e95233f5c0a878d
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/arm/allwinner-h3.c
    M hw/net/allwinner-sun8i-emac.c
    M include/hw/net/allwinner-sun8i-emac.h

  Log Message:
  -----------
  hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers

Allow the device to execute the DMA transfers in a different
AddressSpace.

The H3 SoC keeps using the system_memory address space,
but via the proper dma_memory_access() API.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20200814122907.27732-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 31a171cc8bc9d8524469c286c744dabe70f0c924
      
https://github.com/qemu/qemu/commit/31a171cc8bc9d8524469c286c744dabe70f0c924
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/arm/xilinx_zynq.c
    M include/hw/char/cadence_uart.h

  Log Message:
  -----------
  hw/arm/xilinx_zynq: Uninline cadence_uart_create()

As we want to call qdev_connect_clock_in() before the device
is realized, we need to uninline cadence_uart_create() first.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200803105647.22223-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3ab928789537b8eaf4102ca4602fcd1630b1ec5e
      
https://github.com/qemu/qemu/commit/3ab928789537b8eaf4102ca4602fcd1630b1ec5e
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/arm/xilinx_zynq.c

  Log Message:
  -----------
  hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize

Clock canonical name is set in device_set_realized (see the block
added to hw/core/qdev.c in commit 0e6934f264).
If we connect a clock after the device is realized, this code is
not executed. This is currently not a problem as this name is only
used for trace events, however this disrupt tracing.

Fix by calling qdev_connect_clock_in() before realizing.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200803105647.22223-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f129360ca15723e43a8c44d1a2f025c0df1270cc
      
https://github.com/qemu/qemu/commit/f129360ca15723e43a8c44d1a2f025c0df1270cc
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/core/qdev-clock.c
    M include/hw/qdev-clock.h

  Log Message:
  -----------
  hw/qdev-clock: Uninline qdev_connect_clock_in()

We want to assert the device is not realized. To avoid overloading
this header including "hw/qdev-core.h", uninline the function first.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200803105647.22223-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 739fa3255492f1c7541db1c7a9795fcf4b472c91
      
https://github.com/qemu/qemu/commit/739fa3255492f1c7541db1c7a9795fcf4b472c91
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/core/qdev-clock.c
    M include/hw/qdev-clock.h

  Log Message:
  -----------
  hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize

Clock canonical name is set in device_set_realized (see the block
added to hw/core/qdev.c in commit 0e6934f264).
If we connect a clock after the device is realized, this code is
not executed. This is currently not a problem as this name is only
used for trace events, however this disrupt tracing.

Add a comment to document qdev_connect_clock_in() must be called
before the device is realized, and assert this condition.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200803105647.22223-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 68274b945e9ab4369e97baa010a700f8056c8113
      
https://github.com/qemu/qemu/commit/68274b945e9ab4369e97baa010a700f8056c8113
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/misc/unimp.c

  Log Message:
  -----------
  hw/misc/unimp: Display value after offset

To better align the read/write accesses, display the value after
the offset (read accesses only display the offset).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200812190206.31595-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a12b4c53cbf4d5e75f0e88d624c196d8b71256f4
      
https://github.com/qemu/qemu/commit/a12b4c53cbf4d5e75f0e88d624c196d8b71256f4
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/misc/unimp.c

  Log Message:
  -----------
  hw/misc/unimp: Display the value with width of the access size

To quickly notice the access size, display the value with the
width of the access (i.e. 16-bit access is displayed 0x0000,
while 8-bit access 0x00).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200812190206.31595-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 55d35c881924ce5a8ce410210865e47553762847
      
https://github.com/qemu/qemu/commit/55d35c881924ce5a8ce410210865e47553762847
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/misc/unimp.c
    M include/hw/misc/unimp.h

  Log Message:
  -----------
  hw/misc/unimp: Display the offset with width of the region size

To have a better idea of how big is the region where the offset
belongs, display the value with the width of the region size
(i.e. a region of 0x1000 bytes uses 0x000 format).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200812190206.31595-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 512c65e62e9e1ae9863ae5a8493e9fad9dbf00e7
      
https://github.com/qemu/qemu/commit/512c65e62e9e1ae9863ae5a8493e9fad9dbf00e7
  Author: Eduardo Habkost <ehabkost@redhat.com>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  armsse: Define ARMSSEClass correctly

TYPE_ARM_SSE is a TYPE_SYS_BUS_DEVICE subclass, but
ARMSSEClass::parent_class is declared as DeviceClass.

It never caused any problems by pure luck:

We were not setting class_size for TYPE_ARM_SSE, so class_size of
TYPE_SYS_BUS_DEVICE was being used (sizeof(SysBusDeviceClass)).
This made the system allocate enough memory for TYPE_ARM_SSE
devices even though ARMSSEClass was too small for a sysbus
device.

Additionally, the ARMSSEClass::info field ended up at the same
offset as SysBusDeviceClass::explicit_ofw_unit_address.  This
would make sysbus_get_fw_dev_path() crash for the device.
Luckily, sysbus_get_fw_dev_path() never gets called for
TYPE_ARM_SSE devices, because qdev_get_fw_dev_path() is only used
by the boot device code, and TYPE_ARM_SSE devices don't appear at
the fw_boot_order list.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-id: 20200826181006.4097163-1-ehabkost@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5be4dd043f5beb5e7587d1ef8dd4e3716ec05639
      
https://github.com/qemu/qemu/commit/5be4dd043f5beb5e7587d1ef8dd4e3716ec05639
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M include/qemu/int128.h

  Log Message:
  -----------
  qemu/int128: Add int128_lshift

Add left-shift to match the existing right-shift.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f7d79c41fa4bd0f0d27dcd14babab8575fbed39f
      
https://github.com/qemu/qemu/commit/f7d79c41fa4bd0f0d27dcd14babab8575fbed39f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Split out gen_gvec_fn_zz

Model the new function on gen_gvec_fn2 in translate-a64.c, but
indicating which kind of register and in which order.  Since there
is only one user of do_vector2_z, fold it into do_mov_z.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 28c4da31be6a5e501b60b77bac17652dd3211378
      
https://github.com/qemu/qemu/commit/28c4da31be6a5e501b60b77bac17652dd3211378
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn

Model gen_gvec_fn_zzz on gen_gvec_fn3 in translate-a64.c, but
indicating which kind of register and in which order.

Model do_zzz_fn on the other do_foo functions that take an
argument set and verify sve enabled.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8a40fe5f1bf3837ae3f9961efe1d51e7214f2664
      
https://github.com/qemu/qemu/commit/8a40fe5f1bf3837ae3f9961efe1d51e7214f2664
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Rearrange {sve,fp}_check_access assert

We want to ensure that access is checked by the time we ask
for a specific fp/vector register.  We want to ensure that
we do not emit two lots of code to raise an exception.

But sometimes it's difficult to cleanly organize the code
such that we never pass through sve_check_access exactly once.
Allow multiple calls so long as the result is true, that is,
no exception to be raised.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d0b2df5a01eeccbac71d4d883158b91e7f9a6a29
      
https://github.com/qemu/qemu/commit/d0b2df5a01eeccbac71d4d883158b91e7f9a6a29
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Merge do_vector2_p into do_mov_p

This is the only user of the function.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dd81a8d7cf5c90963603806e58a217bbe759f75e
      
https://github.com/qemu/qemu/commit/dd81a8d7cf5c90963603806e58a217bbe759f75e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Clean up 4-operand predicate expansion

Move the check for !S into do_pppp_flags, which allows to merge in
do_vecop4_p.  Split out gen_gvec_fn_ppp without sve_access_check,
to mirror gen_gvec_fn_zzz.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d4bc623254b55e2f9613c9450216fa7e50c03929
      
https://github.com/qemu/qemu/commit/d4bc623254b55e2f9613c9450216fa7e50c03929
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp

The gvec operation was added after the initial implementation
of the SEL instruction and was missed in the conversion.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 36cbb7a8e7100864c488a1153cecba90b1c33a4c
      
https://github.com/qemu/qemu/commit/36cbb7a8e7100864c488a1153cecba90b1c33a4c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Split out gen_gvec_ool_zzzp

Model after gen_gvec_fn_zzz et al.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 602459969c3b5a96ac970bd4698f60e6edb23bb0
      
https://github.com/qemu/qemu/commit/602459969c3b5a96ac970bd4698f60e6edb23bb0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Merge helper_sve_clr_* and helper_sve_movz_*

The existing clr functions have only one vector argument, and so
can only clear in place.  The existing movz functions have two
vector arguments, and so can clear while moving.  Merge them, with
a flag that controls the sense of active vs inactive elements
being cleared.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 96a461f7c12587d3a64a71e4d90cda5c09ca3eb4
      
https://github.com/qemu/qemu/commit/96a461f7c12587d3a64a71e4d90cda5c09ca3eb4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Split out gen_gvec_ool_zzp

Model after gen_gvec_fn_zzz et al.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e645d1a17a359156c6047006d760ca176d493edb
      
https://github.com/qemu/qemu/commit/e645d1a17a359156c6047006d760ca176d493edb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Split out gen_gvec_ool_zzz

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 40e32e5a8a379baf6e0d49d83cf19950cfbaf96b
      
https://github.com/qemu/qemu/commit/40e32e5a8a379baf6e0d49d83cf19950cfbaf96b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Split out gen_gvec_ool_zz

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 830d1a5a05619b0d407040ab8418018076765249
      
https://github.com/qemu/qemu/commit/830d1a5a05619b0d407040ab8418018076765249
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/sve.decode

  Log Message:
  -----------
  target/arm: Tidy SVE tszimm shift formats

Rather than require the user to fill in the immediate (shl or shr),
create full formats that include the immediate.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d21798856b227a20a0a41640236af445f4f4aeb0
      
https://github.com/qemu/qemu/commit/d21798856b227a20a0a41640236af445f4f4aeb0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Generalize inl_qrdmlah_* helper functions

Unify add/sub helpers and add a parameter for rounding.
This will allow saturating non-rounding to reuse this code.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: fixed accidental use of '=' rather than '+=' in do_sqrdmlah_s]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2e5a265e6a9e7169c4a3e87db261b2fa92582590
      
https://github.com/qemu/qemu/commit/2e5a265e6a9e7169c4a3e87db261b2fa92582590
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3607440c4df6498585a570cfc1041e4972b41b56
      
https://github.com/qemu/qemu/commit/3607440c4df6498585a570cfc1041e4972b41b56
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ed78849d9711805bda37ee026018d6ee7a606d0e
      
https://github.com/qemu/qemu/commit/ed78849d9711805bda37ee026018d6ee7a606d0e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ea1bb830cb021cca2e361091cf728aaabc8c0654
      
https://github.com/qemu/qemu/commit/ea1bb830cb021cca2e361091cf728aaabc8c0654
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-08-28 (Fri, 28 Aug 2020)

  Changed paths:
    M hw/arm/allwinner-a10.c
    M hw/arm/allwinner-h3.c
    M hw/arm/armsse.c
    M hw/arm/musicpal.c
    M hw/arm/sbsa-ref.c
    M hw/arm/xilinx_zynq.c
    M hw/core/clock.c
    M hw/core/qdev-clock.c
    M hw/misc/unimp.c
    M hw/net/allwinner-sun8i-emac.c
    M hw/sd/allwinner-sdhost.c
    M include/hw/arm/armsse.h
    M include/hw/char/cadence_uart.h
    M include/hw/clock.h
    M include/hw/misc/unimp.h
    M include/hw/net/allwinner-sun8i-emac.h
    M include/hw/qdev-clock.h
    M include/hw/sd/allwinner-sdhost.h
    M include/qemu/int128.h
    M target/arm/helper-sve.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/mte_helper.c
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-sve.c
    M target/arm/translate.h
    M target/arm/vec_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200828' 
into staging

target-arm queue:
 * target/arm: Cleanup and refactoring preparatory to SVE2
 * armsse: Define ARMSSEClass correctly
 * hw/misc/unimp: Improve information provided in log messages
 * hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
 * hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
 * hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
 * hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
 * target/arm: Fill in the WnR syndrome bit in mte_check_fail
 * target/arm: Clarify HCR_EL2 ARMCPRegInfo type
 * hw/arm/musicpal: Use AddressSpace for DMA transfers
 * hw/clock: Minor cleanups
 * hw/arm/sbsa-ref: fix typo breaking PCIe IRQs

# gpg: Signature made Fri 28 Aug 2020 10:23:02 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200828: (35 commits)
  target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd
  target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd
  target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd
  target/arm: Generalize inl_qrdmlah_* helper functions
  target/arm: Tidy SVE tszimm shift formats
  target/arm: Split out gen_gvec_ool_zz
  target/arm: Split out gen_gvec_ool_zzz
  target/arm: Split out gen_gvec_ool_zzp
  target/arm: Merge helper_sve_clr_* and helper_sve_movz_*
  target/arm: Split out gen_gvec_ool_zzzp
  target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
  target/arm: Clean up 4-operand predicate expansion
  target/arm: Merge do_vector2_p into do_mov_p
  target/arm: Rearrange {sve,fp}_check_access assert
  target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
  target/arm: Split out gen_gvec_fn_zz
  qemu/int128: Add int128_lshift
  armsse: Define ARMSSEClass correctly
  hw/misc/unimp: Display the offset with width of the region size
  hw/misc/unimp: Display the value with width of the access size
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/3e39dac0354c...ea1bb830cb02
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