[Qemu-commits] [qemu/qemu] 3bf03f: hw/riscv: Allow creating multiple ins

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[Qemu-commits] [qemu/qemu] 3bf03f: hw/riscv: Allow creating multiple ins

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 3bf03f: hw/riscv: Allow creating multiple instances of CLINT
Date:	Wed, 26 Aug 2020 02:30:32 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 3bf03f08999b9a469a61279a04041bcbfadad6a8
      
https://github.com/qemu/qemu/commit/3bf03f08999b9a469a61279a04041bcbfadad6a8
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M hw/riscv/sifive_clint.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_clint.h

  Log Message:
  -----------
  hw/riscv: Allow creating multiple instances of CLINT

We extend CLINT emulation to allow multiple instances of CLINT in
a QEMU RISC-V machine. To achieve this, we remove first HART id
zero assumption from CLINT emulation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-Id: <20200616032229.766089-2-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c9270e10a5e3aa18a55bb5c115ae7838c8c43e41
      
https://github.com/qemu/qemu/commit/c9270e10a5e3aa18a55bb5c115ae7838c8c43e41
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_plic.c
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_plic.h

  Log Message:
  -----------
  hw/riscv: Allow creating multiple instances of PLIC

We extend PLIC emulation to allow multiple instances of PLIC in
a QEMU RISC-V machine. To achieve this, we remove first HART id
zero assumption from PLIC emulation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200616032229.766089-3-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 83fcaefd9d52670d71e1705b13d3df02d8ee4566
      
https://github.com/qemu/qemu/commit/83fcaefd9d52670d71e1705b13d3df02d8ee4566
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M hw/riscv/meson.build
    A hw/riscv/numa.c
    A include/hw/riscv/numa.h

  Log Message:
  -----------
  hw/riscv: Add helpers for RISC-V multi-socket NUMA machines

We add common helper routines which can be shared by RISC-V
multi-socket NUMA machines.

We have two types of helpers:
1. riscv_socket_xyz() - These helper assist managing multiple
   sockets irrespective whether QEMU NUMA is enabled/disabled
2. riscv_numa_xyz() - These helpers assist in providing
   necessary QEMU machine callbacks for QEMU NUMA emulation

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-4-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a7172791e356a16c60ed321a8b3a463b0f0724d3
      
https://github.com/qemu/qemu/commit/a7172791e356a16c60ed321a8b3a463b0f0724d3
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M hw/riscv/spike.c
    M include/hw/riscv/spike.h

  Log Message:
  -----------
  hw/riscv: spike: Allow creating multiple NUMA sockets

We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.

By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.

Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"

Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"

The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 18df0b4695c06103f513dd6b0fb9d44482462bd5
      
https://github.com/qemu/qemu/commit/18df0b4695c06103f513dd6b0fb9d44482462bd5
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  hw/riscv: virt: Allow creating multiple NUMA sockets

We extend RISC-V virt machine to allow creating a multi-socket
machine. Each RISC-V virt machine socket is a NUMA node having
a set of HARTs, a memory instance, a CLINT instance, and a PLIC
instance. Other devices are shared between all sockets. We also
update the generated device tree accordingly.

By default, NUMA multi-socket support is disabled for RISC-V virt
machine. To enable it, users can use "-numa" command-line options
of QEMU.

Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"

Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"

The maximum number of sockets in a RISC-V virt machine is 8
but this limit can be changed in future.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-6-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5a894dd7709f3b6a9f3e861dec71f78098bb3373
      
https://github.com/qemu/qemu/commit/5a894dd7709f3b6a9f3e861dec71f78098bb3373
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Allow setting a two-stage lookup in the virt status

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com>


  Commit: 8c5362acb573b8b1913238a5ddefdeef12f513a8
      
https://github.com/qemu/qemu/commit/8c5362acb573b8b1913238a5ddefdeef12f513a8
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/helper.h
    M target/riscv/insn32-64.decode
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Allow generating hlv/hlvx/hsv instructions

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com>


  Commit: 29b3361b14987af0f5fb1e4f98e9e8abbf3dd9f1
      
https://github.com/qemu/qemu/commit/29b3361b14987af0f5fb1e4f98e9e8abbf3dd9f1
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com>


  Commit: e2eb5ca8f66c239f6194afda88cad455e42725ef
      
https://github.com/qemu/qemu/commit/e2eb5ca8f66c239f6194afda88cad455e42725ef
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Don't allow guest to write to htinst

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
ca5359fec6b2aff851eef3b3bc4b53cb5d4ad194.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<ca5359fec6b2aff851eef3b3bc4b53cb5d4ad194.1597259519.git.alistair.francis@wdc.com>


  Commit: 9034e90ad9959b89da32978e3b6d71b7069050a5
      
https://github.com/qemu/qemu/commit/9034e90ad9959b89da32978e3b6d71b7069050a5
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Convert MSTATUS MTL to GVA

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com>


  Commit: 84b1c04bbaf48798a535b38410a0bf839f4a1943
      
https://github.com/qemu/qemu/commit/84b1c04bbaf48798a535b38410a0bf839f4a1943
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Fix the interrupt cause code

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com>


  Commit: f2d5850f71f3e41b240f328c2bc844a4e44e66c9
      
https://github.com/qemu/qemu/commit/f2d5850f71f3e41b240f328c2bc844a4e44e66c9
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/op_helper.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Update the Hypervisor trap return/entry

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com>


  Commit: 543ba53157f9003eaa9b802d44c577c5814e232c
      
https://github.com/qemu/qemu/commit/543ba53157f9003eaa9b802d44c577c5814e232c
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Update the CSRs to the v0.6 Hyp extension

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com>


  Commit: f8dc878efc45691be7e6c2019a19c271fb9aebbb
      
https://github.com/qemu/qemu/commit/f8dc878efc45691be7e6c2019a19c271fb9aebbb
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Only support a single VSXL length

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com>


  Commit: 30f663b16f81d862256c7c71bc909d4588924d8c
      
https://github.com/qemu/qemu/commit/30f663b16f81d862256c7c71bc909d4588924d8c
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Only support little endian guests

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com>


  Commit: 83028098f45a08da209799aeea4801c362d0afeb
      
https://github.com/qemu/qemu/commit/83028098f45a08da209799aeea4801c362d0afeb
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Support the v0.6 Hypervisor extension CRSs

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com>


  Commit: 57cb2083e638bb28616c059cbf067d99552a04bb
      
https://github.com/qemu/qemu/commit/57cb2083e638bb28616c059cbf067d99552a04bb
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/csr.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Return the exception from invalid CSR accesses

When performing a CSR access let's return a negative exception value on
an error instead of -1. This will allow us to specify the exception in
future patches.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com>


  Commit: e39a8320b088dd5efc9ebaafe387e52b3d962665
      
https://github.com/qemu/qemu/commit/e39a8320b088dd5efc9ebaafe387e52b3d962665
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c
    M target/riscv/helper.h
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Support the Virtual Instruction fault

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com
Message-Id: 
<4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com>


  Commit: 78dca230c97ed0d6e16ae0c96d5407644d991994
      
https://github.com/qemu/qemu/commit/78dca230c97ed0d6e16ae0c96d5407644d991994
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-08-25 (Tue, 25 Aug 2020)

  Changed paths:
    M hw/riscv/meson.build
    A hw/riscv/numa.c
    M hw/riscv/sifive_clint.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_plic.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    A include/hw/riscv/numa.h
    M include/hw/riscv/sifive_clint.h
    M include/hw/riscv/sifive_plic.h
    M include/hw/riscv/spike.h
    M include/hw/riscv/virt.h
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/helper.h
    M target/riscv/insn32-64.decode
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/op_helper.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20200825' into staging

This pull request first adds support for multi-socket NUMA RISC-V
machines. The Spike and Virt machines both support NUMA sockets.

This PR also updates the current experimental Hypervisor support to the
v0.6.1 spec.

# gpg: Signature made Tue 25 Aug 2020 19:47:41 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200825:
  target/riscv: Support the Virtual Instruction fault
  target/riscv: Return the exception from invalid CSR accesses
  target/riscv: Support the v0.6 Hypervisor extension CRSs
  target/riscv: Only support little endian guests
  target/riscv: Only support a single VSXL length
  target/riscv: Update the CSRs to the v0.6 Hyp extension
  target/riscv: Update the Hypervisor trap return/entry
  target/riscv: Fix the interrupt cause code
  target/riscv: Convert MSTATUS MTL to GVA
  target/riscv: Don't allow guest to write to htinst
  target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
  target/riscv: Allow generating hlv/hlvx/hsv instructions
  target/riscv: Allow setting a two-stage lookup in the virt status
  hw/riscv: virt: Allow creating multiple NUMA sockets
  hw/riscv: spike: Allow creating multiple NUMA sockets
  hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
  hw/riscv: Allow creating multiple instances of PLIC
  hw/riscv: Allow creating multiple instances of CLINT

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/d1a2b51f868d...78dca230c97e
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