[Qemu-commits] [qemu/qemu] 91dc2b: target/xtensa: make opcode properties

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[Qemu-commits] [qemu/qemu] 91dc2b: target/xtensa: make opcode properties

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 91dc2b: target/xtensa: make opcode properties more dynamic
Date:	Tue, 25 Aug 2020 02:45:30 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 91dc2b2d12a0343f37a3ab425f2912ae0ce18187
      
https://github.com/qemu/qemu/commit/91dc2b2d12a0343f37a3ab425f2912ae0ce18187
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: make opcode properties more dynamic

There's XtensaOpcodeOps::test_ill that is used to check whether opcode
generates illegal opcode exception or not. The illegal opcode exception
is not special and so this callback can be generalized to provide any
XTENSA_OP_* flags that are not completely static.
Introduce XtensaOpcodeOps::test_exceptions and convert all test_ill
users to test_exceptions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: a7d479ee51c5911c93ee931efe4c2413b54c8756
      
https://github.com/qemu/qemu/commit/a7d479ee51c5911c93ee931efe4c2413b54c8756
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M hw/xtensa/pic_cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/exc_helper.c
    M target/xtensa/overlay_tool.h

  Log Message:
  -----------
  target/xtensa: implement NMI support

When NMI is configured it is taken regardless of INTENABLE SR contents,
PS.INTLEVEL or PS.EXCM. It is cleared automatically once it's taken.

Add nmi_level to XtensaConfig, puth there NMI level from the overlay or
XCHAL_NUM_INTLEVELS + 1 when NMI is not configured. Add NMI mask to
INTENABLE SR and limit CINTLEVEL to nmi_level - 1 when determining
pending IRQ level in check_interrupt(). Always take and clear pending
interrupt at nmi_level in the handle_interrupt().

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: cc43c6925113c5bc8f1a0205375931d2e4807c99
      
https://github.com/qemu/qemu/commit/cc43c6925113c5bc8f1a0205375931d2e4807c99
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M fpu/softfloat-specialize.c.inc
    M include/fpu/softfloat-helpers.h
    M include/fpu/softfloat-types.h

  Log Message:
  -----------
  softfloat: make NO_SIGNALING_NANS runtime property

target/xtensa, the only user of NO_SIGNALING_NANS macro has FPU
implementations with and without the corresponding property. With
NO_SIGNALING_NANS being a macro they cannot be a part of the same QEMU
executable.
Replace macro with new property in float_status to allow cores with
different FPU implementations coexist.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: "Alex Bennée" <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: 913602e3ffe6bf50b869a14028a55cb267645ba3
      
https://github.com/qemu/qemu/commit/913602e3ffe6bf50b869a14028a55cb267645ba3
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M fpu/softfloat-specialize.c.inc
    M fpu/softfloat.c
    M include/fpu/softfloat-helpers.h
    M include/fpu/softfloat-types.h

  Log Message:
  -----------
  softfloat: pass float_status pointer to pickNaN

Pass float_status structure pointer to the pickNaN so that
machine-specific settings are available to NaN selection code.
Add use_first_nan property to float_status and use it in Xtensa-specific
pickNaN.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: "Alex Bennée" <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: fbcc38e4cb1b539b8615ec9b0adc285351d77628
      
https://github.com/qemu/qemu/commit/fbcc38e4cb1b539b8615ec9b0adc285351d77628
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M fpu/softfloat-specialize.c.inc

  Log Message:
  -----------
  softfloat: add xtensa specialization for pickNaNMulAdd

pickNaNMulAdd logic on Xtensa is to apply pickNaN to the inputs of the
expression (a * b) + c. However if default NaN is produces as a result
of (a * b) calculation it is not considered when c is NaN.
So with two pickNaN variants there must be two pickNaNMulAdd variants.
In addition the invalid flag is always set when (a * b) produces NaN.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: "Alex Bennée" <alex.bennee@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: ee659da21af5707191ef35e8de549d028790e7f5
      
https://github.com/qemu/qemu/commit/ee659da21af5707191ef35e8de549d028790e7f5
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/helper.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: add geometry to xtensa_get_regfile_by_name

Register file name may not uniquely identify a register file in the set
of configurations. E.g. floating point registers may have different size
in different configurations. Use register file geometry as additional
identifier.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: ed07f685adcd2c3496dbbaefc07f7e1a996fce58
      
https://github.com/qemu/qemu/commit/ed07f685adcd2c3496dbbaefc07f7e1a996fce58
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: support copying registers up to 64 bits wide

FLIX dependency breaking code assumes that all registers are 32 bit
wide. This may not always be correct.
Extract actual register width from the associated register file and use
it to create temporaries of correct width and generate correct data
movement instructions.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: 5680f20756fa21ca7bd72b6d9bbc8598f5b7a240
      
https://github.com/qemu/qemu/commit/5680f20756fa21ca7bd72b6d9bbc8598f5b7a240
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/xtensa/fpu_helper.c
    M target/xtensa/helper.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: rename FPU2000 translators and helpers

Add _s suffix to all FPU2000 opcode translators and helpers that also
have double-precision variant to unify naming and allow adding DFPU
implementations. Add _fpu2k_ to the names of helpers that will have
different implementation for the DFPU .

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: ff35a7d1a1027bb867ee6f23935100dd105331fe
      
https://github.com/qemu/qemu/commit/ff35a7d1a1027bb867ee6f23935100dd105331fe
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: move FSR/FCR register accessors

Move FSR/FCR register accessors from core opcodes to FPU2000 opcodes as
they are FPU2000-specific.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: 5dbb4c96d50c6ef74d4fd71a5a0fd9763d5a3662
      
https://github.com/qemu/qemu/commit/5dbb4c96d50c6ef74d4fd71a5a0fd9763d5a3662
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/xtensa/fpu_helper.c
    M target/xtensa/helper.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: don't access BR regfile directly

BR registers used in FPU comparison opcodes are available as opcode
arguments for translators. Use them. This simplifies comparison helpers
interface and makes them usable in FLIX bundles.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: de6b55cbda2a26fb8889c8a8b44c139d7e106dce
      
https://github.com/qemu/qemu/commit/de6b55cbda2a26fb8889c8a8b44c139d7e106dce
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/overlay_tool.h

  Log Message:
  -----------
  target/xtensa: add DFPU option

Double precision floating point unit is a FPU implementation different
from the FPU2000 in the following ways:
- it may be configured with only single or with both single and double
  precision operations support;
- it may be configured with division and square root opcodes;
- FSR register accumulates inValid, division by Zero, Overflow,
  Underflow and Inexact result flags of operations;
- QNaNs and SNaNs are handled properly;
- NaN propagation rules are different.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: cfa9f0518144c0ea30f51fd2f203a09dd0a40cd9
      
https://github.com/qemu/qemu/commit/cfa9f0518144c0ea30f51fd2f203a09dd0a40cd9
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/fpu_helper.c
    M target/xtensa/helper.h
    M target/xtensa/overlay_tool.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: add DFPU registers and opcodes

DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA
does not specify how single-precision values are stored in 64-bit
registers. Existing implementations store them in the low half of the
registers.
Add value extraction and write back to single-precision opcodes.
Add new double precision opcodes. Add 64-bit register file.
Add 64-bit values dumping to the xtensa_cpu_dump_state.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: f8c613701637ebfbf75570153715af3ac7aeca9d
      
https://github.com/qemu/qemu/commit/f8c613701637ebfbf75570153715af3ac7aeca9d
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/xtensa/fpu_helper.c
    M target/xtensa/helper.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: implement FPU division and square root

This does not implement all opcodes related to div/sqrt as specified in
the xtensa ISA, partly because the official specification is not
complete and partly because precise implementation is unnecessarily
complex. Instead instructions specific to the div/sqrt sequences are
implemented differently, most of them as nops, but the results of
div/sqrt sequences is preserved.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: 6ac269c33cd50679ed37b0bafcef0a95b76b1543
      
https://github.com/qemu/qemu/commit/6ac269c33cd50679ed37b0bafcef0a95b76b1543
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M tests/tcg/xtensa/macros.inc

  Log Message:
  -----------
  tests/tcg/xtensa: fix test execution on ISS

Space for test results may be allocated in IRAM which is only
word-accessible. Use full 32-bit words to access test results.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: e95ef43181b49a401d163729d0d96f304525dfe7
      
https://github.com/qemu/qemu/commit/e95ef43181b49a401d163729d0d96f304525dfe7
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    A tests/tcg/xtensa/fpu.h
    M tests/tcg/xtensa/test_fp0_arith.S

  Log Message:
  -----------
  tests/tcg/xtensa: update test_fp0_arith for DFPU

DFPU arithmetic opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the arithmetic tests.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: ac81ff227d264b29b8b75068a75d047e2d736d6f
      
https://github.com/qemu/qemu/commit/ac81ff227d264b29b8b75068a75d047e2d736d6f
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M tests/tcg/xtensa/test_fp0_arith.S

  Log Message:
  -----------
  tests/tcg/xtensa: expand madd tests

Test that madd doesn't do rounding after multiplication.
Test NaN propagation rules for FPU2000 and DFPU madd opcode.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: 5c10f488ea42dcdd63c8b37792c1e04d69208197
      
https://github.com/qemu/qemu/commit/5c10f488ea42dcdd63c8b37792c1e04d69208197
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M tests/tcg/xtensa/test_fp0_conv.S

  Log Message:
  -----------
  tests/tcg/xtensa: update test_fp0_conv for DFPU

DFPU conversion opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the conversion tests.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: 7f4faa2185f7ef3fbbee564d1c89edb229c421a3
      
https://github.com/qemu/qemu/commit/7f4faa2185f7ef3fbbee564d1c89edb229c421a3
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M tests/tcg/xtensa/test_fp1.S

  Log Message:
  -----------
  tests/tcg/xtensa: update test_fp1 for DFPU

DFPU sets Invalid flag in FSR when at least one argument of FP
comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole.
Add checks for FSR and expected FSR values.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: adbb3df08e8cef46d8a9a77eab097125efeb1968
      
https://github.com/qemu/qemu/commit/adbb3df08e8cef46d8a9a77eab097125efeb1968
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M tests/tcg/xtensa/test_lsc.S

  Log Message:
  -----------
  tests/tcg/xtensa: update test_lsc for DFPU

DFPU doesn't have pre-increment FP load/store opcodes, it has
post-increment opcodes instead. Test increment opcodes present in the
current config.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: 11029e949fcb8b8bd3dbac975db17a38fa817453
      
https://github.com/qemu/qemu/commit/11029e949fcb8b8bd3dbac975db17a38fa817453
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    A tests/tcg/xtensa/test_fp0_div.S
    A tests/tcg/xtensa/test_fp0_sqrt.S

  Log Message:
  -----------
  tests/tcg/xtensa: add fp0 div and sqrt tests

Test exact division/sqrt DFPU sequences.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: b2d84da9b8d7502800027dd222a5e8d1ee5b3c02
      
https://github.com/qemu/qemu/commit/b2d84da9b8d7502800027dd222a5e8d1ee5b3c02
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M tests/tcg/xtensa/test_lsc.S

  Log Message:
  -----------
  tests/tcg/xtensa: test double precision load/store

Add ldi[p]/sdi[p]/ldx[p]/sdx[p] opcode tests to test_lsc.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: 6aa29c07ee77b5c4833c76038a534a4040f030cc
      
https://github.com/qemu/qemu/commit/6aa29c07ee77b5c4833c76038a534a4040f030cc
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    A tests/tcg/xtensa/test_dfp0_arith.S

  Log Message:
  -----------
  tests/tcg/xtensa: add DFP0 arithmetic tests

Add test for basic double precision opcode properties.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: 79bc0fb5f15dd9afde5302e0919d249029adcac3
      
https://github.com/qemu/qemu/commit/79bc0fb5f15dd9afde5302e0919d249029adcac3
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    A target/xtensa/core-de233_fpu.c
    A target/xtensa/core-de233_fpu/core-isa.h
    A target/xtensa/core-de233_fpu/core-matmap.h
    A target/xtensa/core-de233_fpu/gdb-config.c.inc
    A target/xtensa/core-de233_fpu/xtensa-modules.c.inc
    M target/xtensa/meson.build

  Log Message:
  -----------
  target/xtensa: import de233_fpu core

de233_fpu is a variant of 233L core with double precision FPU.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: c621b4142bf1ff8c663811c10bd1628481e494a6
      
https://github.com/qemu/qemu/commit/c621b4142bf1ff8c663811c10bd1628481e494a6
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    A target/xtensa/core-dsp3400.c
    A target/xtensa/core-dsp3400/core-isa.h
    A target/xtensa/core-dsp3400/core-matmap.h
    A target/xtensa/core-dsp3400/gdb-config.c.inc
    A target/xtensa/core-dsp3400/xtensa-modules.c.inc
    M target/xtensa/meson.build

  Log Message:
  -----------
  target/xtensa: import DSP3400 core

DSP3400 is a DSP core with FPU2000 option.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>


  Commit: 44423107e7b5731ef40c5c8632a5bad8b49d0838
      
https://github.com/qemu/qemu/commit/44423107e7b5731ef40c5c8632a5bad8b49d0838
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-08-24 (Mon, 24 Aug 2020)

  Changed paths:
    M fpu/softfloat-specialize.c.inc
    M fpu/softfloat.c
    M hw/xtensa/pic_cpu.c
    M include/fpu/softfloat-helpers.h
    M include/fpu/softfloat-types.h
    A target/xtensa/core-de233_fpu.c
    A target/xtensa/core-de233_fpu/core-isa.h
    A target/xtensa/core-de233_fpu/core-matmap.h
    A target/xtensa/core-de233_fpu/gdb-config.c.inc
    A target/xtensa/core-de233_fpu/xtensa-modules.c.inc
    A target/xtensa/core-dsp3400.c
    A target/xtensa/core-dsp3400/core-isa.h
    A target/xtensa/core-dsp3400/core-matmap.h
    A target/xtensa/core-dsp3400/gdb-config.c.inc
    A target/xtensa/core-dsp3400/xtensa-modules.c.inc
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/exc_helper.c
    M target/xtensa/fpu_helper.c
    M target/xtensa/helper.c
    M target/xtensa/helper.h
    M target/xtensa/meson.build
    M target/xtensa/overlay_tool.h
    M target/xtensa/translate.c
    A tests/tcg/xtensa/fpu.h
    M tests/tcg/xtensa/macros.inc
    A tests/tcg/xtensa/test_dfp0_arith.S
    M tests/tcg/xtensa/test_fp0_arith.S
    M tests/tcg/xtensa/test_fp0_conv.S
    A tests/tcg/xtensa/test_fp0_div.S
    A tests/tcg/xtensa/test_fp0_sqrt.S
    M tests/tcg/xtensa/test_fp1.S
    M tests/tcg/xtensa/test_lsc.S

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into 
staging

target/xtensa updates for 5.2:

- add NMI support;
- add DFPU option implementation;
- update FPU tests to support both FPU2000 and DFPU;
- add example cores with FPU2000 and DFPU.

# gpg: Signature made Fri 21 Aug 2020 21:09:37 BST
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" 
[full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20200821-xtensa: (24 commits)
  target/xtensa: import DSP3400 core
  target/xtensa: import de233_fpu core
  tests/tcg/xtensa: add DFP0 arithmetic tests
  tests/tcg/xtensa: test double precision load/store
  tests/tcg/xtensa: add fp0 div and sqrt tests
  tests/tcg/xtensa: update test_lsc for DFPU
  tests/tcg/xtensa: update test_fp1 for DFPU
  tests/tcg/xtensa: update test_fp0_conv for DFPU
  tests/tcg/xtensa: expand madd tests
  tests/tcg/xtensa: update test_fp0_arith for DFPU
  tests/tcg/xtensa: fix test execution on ISS
  target/xtensa: implement FPU division and square root
  target/xtensa: add DFPU registers and opcodes
  target/xtensa: add DFPU option
  target/xtensa: don't access BR regfile directly
  target/xtensa: move FSR/FCR register accessors
  target/xtensa: rename FPU2000 translators and helpers
  target/xtensa: support copying registers up to 64 bits wide
  target/xtensa: add geometry to xtensa_get_regfile_by_name
  softfloat: add xtensa specialization for pickNaNMulAdd
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/30aa19446d82...44423107e7b5
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