[Qemu-commits] [qemu/qemu] 9921e3: target/riscv: Generate nanboxed results from fp he...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9921e3d3306c344aceeabe074d5bcaafcc6acafb
      
https://github.com/qemu/qemu/commit/9921e3d3306c344aceeabe074d5bcaafcc6acafb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/internals.h

  Log Message:
  -----------
  target/riscv: Generate nanboxed results from fp helpers

Make sure that all results from single-precision scalar helpers
are properly nan-boxed to 64-bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d36a86d01e67792c51dd2a82360cda012bde9442
      
https://github.com/qemu/qemu/commit/d36a86d01e67792c51dd2a82360cda012bde9442
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s

Do not depend on the RVD extension, take input and output via
TCGv_i64 instead of fpu regno.  Move the function to translate.c
so that it can be used in multiple trans_*.inc.c files.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 40eaa473611936445ae9c63841445cfa6e36840b
      
https://github.com/qemu/qemu/commit/40eaa473611936445ae9c63841445cfa6e36840b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvf.c.inc

  Log Message:
  -----------
  target/riscv: Generate nanboxed results from trans_rvf.inc.c

Make sure that all results from inline single-precision scalar
operations are properly nan-boxed to 64-bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 00e925c56074f8c4923a087e2eecea8a3315ea40
      
https://github.com/qemu/qemu/commit/00e925c56074f8c4923a087e2eecea8a3315ea40
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/internals.h

  Log Message:
  -----------
  target/riscv: Check nanboxed inputs to fp helpers

If a 32-bit input is not properly nanboxed, then the input is
replaced with the default qnan.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-5-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ffe70e4dfc9cf2a6934e674b81b69c847b403c4b
      
https://github.com/qemu/qemu/commit/ffe70e4dfc9cf2a6934e674b81b69c847b403c4b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Check nanboxed inputs in trans_rvf.inc.c

If a 32-bit input is not properly nanboxed, then the input is replaced
with the default qnan.  The only inline expansion is for the sign-changing
set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-6-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6e0229e63868b8b5bfcc54959cea227ed19f7bd3
      
https://github.com/qemu/qemu/commit/6e0229e63868b8b5bfcc54959cea227ed19f7bd3
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvf.c.inc

  Log Message:
  -----------
  target/riscv: Clean up fmv.w.x

Use tcg_gen_extu_tl_i64 to avoid the ifdef.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200626205917.4545-7-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200724002807.441147-7-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ec80f8745931f0c8f8f2251e16bcc69170cf6f27
      
https://github.com/qemu/qemu/commit/ec80f8745931f0c8f8f2251e16bcc69170cf6f27
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc

  Log Message:
  -----------
  target/riscv: check before allocating TCG temps

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200724002807.441147-8-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6eaf9cf56f0f6e3faf73273f93cfe3e2e9fd0786
      
https://github.com/qemu/qemu/commit/6eaf9cf56f0f6e3faf73273f93cfe3e2e9fd0786
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv: sifive_u: Add a dummy L2 cache controller device

It is enough to simply map the SiFive FU540 L2 cache controller
into the MMIO space using create_unimplemented_device(), with an
FDT fragment generated, to make the latest upstream U-Boot happy.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: fdd33b86b20d153b131fc6259aea7a0084ab14b8
      
https://github.com/qemu/qemu/commit/fdd33b86b20d153b131fc6259aea7a0084ab14b8
  Author: Hou Weiying <weiying_hou@outlook.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  riscv: Fix bug in setting pmpcfg CSR for RISCV64

First, sizeof(target_ulong) equals to 4 on riscv32, so this change
does not change the function on riscv32. Second, sizeof(target_ulong)
equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal
pmp_index (we will explain later), which should be 'reg_index * 4 + i'.

If the parameter reg_index equals to 2 (means that we will change the
value of pmpcfg2, or the second pmpcfg on riscv64), then
pmpcfg_csr_write(env, 2, val) will map write tasks to
pmp_write_cfg(env, 2 * 8 + [0...7], val). However, no cfg csr is indexed
by value 16 or 23 on riscv64, so we consider it as a bug.

We are looking for constant (e.g., define a new constant named
RISCV_WORD_SIZE) in QEMU to help others understand code better,
but none was found. A possible good explanation of this literal is it is
the minimum word length on riscv is 4 bytes (32 bit).

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<SG2PR02MB263420036254AC8841F66CE393460@SG2PR02MB2634.apcprd02.prod.outlook.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3a631b8e7f36448cac4ffae1df4526bf079406ea
      
https://github.com/qemu/qemu/commit/3a631b8e7f36448cac4ffae1df4526bf079406ea
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M configure

  Log Message:
  -----------
  configure: Create symbolic links for pc-bios/*.elf files

Now we need to ship the OpenSBI fw_dynamic.elf image for the
RISC-V Spike machine, it requires us to create symbolic links
for pc-bios/*.elf files.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8ebde78620938990039c7ad000c9c19f67ba4950
      
https://github.com/qemu/qemu/commit/8ebde78620938990039c7ad000c9c19f67ba4950
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M roms/opensbi

  Log Message:
  -----------
  roms/opensbi: Upgrade from v0.7 to v0.8

Upgrade OpenSBI from v0.7 to v0.8.

The v0.8 release includes the following commits:

1bb00ab lib: No need to provide default PMP region using platform callbacks
a9eac67 include: sbi_platform: Combine reboot and shutdown into one callback
6585fab lib: utils: Add SiFive test device
4781545 platform: Add Nuclei UX600 platform
3a326af scripts: adapt binary archive script for Nuclei UX600
5bdf022 firmware: fw_base: Remove CSR_MTVEC update check
e6c1345 lib: utils/serial: Skip baudrate config if input frequency is zero
01a8c8e lib: utils: Improve fdt_parse_uart8250() API
0a0093b lib: utils: Add fdt_parse_uart8250_node() function
243b0d0 lib: utils: Remove redundant clint_ipi_sync() declaration
e3ad7c1 lib: utils: Rename fdt_parse_clint() to fdt_parse_compat_addr()
a39cd6f lib: utils: Add FDT match table based node lookup
dd33b9e lib: utils: Make fdt_get_node_addr_size() public function
66185b3 lib: utils: Add fdt_parse_sifive_uart_node() function
19e966b lib: utils: Add fdt_parse_hart_id() function
44dd7be lib: utils: Add fdt_parse_max_hart_id() API
f0eb503 lib: utils: Add fdt_parse_plic_node() function
1ac794c include: Add array_size() macro
8ff2b94 lib: utils: Add simple FDT timer framework
76f0f81 lib: utils: Add simple FDT ipi framework
75322a6 lib: utils: Add simple FDT irqchip framework
76a8940 lib: utils: Add simple FDT serial framework
7cc6fa4 lib: utils: Add simple FDT reset framework
4d06353 firmware: fw_base: Introduce optional fw_platform_init()
f1aa9e5 platform: Add generic FDT based platform support
1f21b99 lib: sbi: Print platform hart count at boot time
2ba7087 scripts: Add generic platform to create-binary-archive.sh
4f18c6e platform: generic: Add Sifive FU540 TLB flush range limit override
13717a8 platform: Remove qemu/virt directory
65c06b0 platform: Remove spike directory
d626037 docs: Add missing links in platform.md
7993ca2 include: sbi: Remove redundant page table related defines
5338679 lib: sbi_tlb: Fix remote TLB HFENCE VVMA implementation
dc38929 lib: sbi: Improve misa_string() implementation
433bac7 docs: platform/generic: Add details about stdout-path DT property
b4efa70 docs: platform/generic: Add details about IPI and timer expectations
dfd9dd6 docs: Add platform requirements document
c2286b6 docs: Fix ordering of pages in table of contents
7be75f5 docs: Don't use italic text in page title
63a513e lib: Rename unprivileged trap handler
aef9a60 lib: Add csr detect support
13ca20d lib: Create a separate math helper function file
79d0fad lib: utils: Update reserved memory fdt node even if PMP is not present
6a053f6 lib: Add support for hart specific features
b2df751 platform: Move platform features to hart
4938024 platform: fpga: Remove redundant platform specific features
ec0d2a7 lib: timer: Provide a hart based timer feature
1f235ec lib: Add platform features in boot time print
22c4334 lib: Add hart features in boot time print
36833ab lib: Optimize inline assembly for unprivilege access functions
38a4b54 firmware: Correct spelling mistakes
28b4052 lib: sbi: detect features before everything else in sbi_hart_init()
4984183 lib: sbi: Improve get_feature_str() implementation and usage
3aa1036 lib: sbi: Remove extra spaces from boot time prints
3a8fc81 lib: sbi: Print platform HART count just before boot HART id
63b0f5f include: sbi: Use scratch pointer as parmeter in HART feature APIs
2966510 lib: sbi: Few cosmetic improvements to HART feature detection
a38bea9 lib: sbi_hart: Detect number of supported PMP regions
89ba634 include: sbi: Add firmware extension constants
73d6ef3 lib: utils: Remove redundant parameters from PLIC init functions
446a9c6 lib: utils: Allow PLIC functions to be used for multiple PLICs
2c685c2 lib: utils: Extend fdt_find_match() Implementation
d30bb68 lib: utils/irqchip: Initialize all matching irqchip DT nodes
a9a9751 lib: utils: Allow CLINT functions to be used for multiple CLINTs
569dd64 lib: utils: Add fdt_parse_clint_node() function
6956e83 lib: utils/ipi: Initialize all matching ipi DT nodes
a63f05f lib: utils/timer: Initialize all matching timer DT nodes
30b6040 Makefile: Fix builtin DTB compilation for out-of-tree platforms
64f1408 firmware: fw_base: Make builtin DTB available to fw_platform_init()
4ce6b7a firmware: fw_base: Don't OR forced FW_OPTIONS
86ec534 firmware: Allow fw_platform_init() to return updated FDT location
c6c65ee Makefile: Preprocess builtin DTS
4e3876d Makefile: Add mechanism for platforms to have multiple builtin DTBs
72019ee platform: kendryte/k210: Use new mechanism of builtin DTB
51f0e4a firmware: Remove FW_PAYLOAD_FDT and related documentation
1b8c012 lib: Add RISC-V hypervisor v0.6.1 support
79bfd67 docs: Use doxygen config to mark the main page
106b888 docs: Remove redundant documentation about combined payload use case
9802906 platform: Add AE350 platform specific SBI handler
32f87e5 platform: Add AE350 cache control SBIs
e2c3f01 lib: Fix __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va()
6966ad0 platform/lib: Allow the OS to map the regions that are protected by PMP
518e85c platform: Update Nuclei ux600 platform support
d5725c2 lib: Don't print delegation CSRs if there is no S-Mode
637b348 lib: Fix the SBI_HART_HAS_MCOUNTEREN feature check
db56ef3 platform: Add support for Shakti C-class SoC from IIT-M
9bd5f8f lib: sbi: Fix 32/64 bits variable compatibility
2314101 lib: Don't return any invalid error from SBI ecall
a98258d include: Bump-up version to 0.8

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 00db05fbedf60f6722e881cfa7f01320e579c321
      
https://github.com/qemu/qemu/commit/00db05fbedf60f6722e881cfa7f01320e579c321
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M roms/Makefile

  Log Message:
  -----------
  roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware

The RISC-V generic platform is a flattened device tree (FDT) based
platform where all platform specific functionality is provided based
on FDT passed by previous booting stage. The support was added in
the upstream OpenSBI v0.8 release recently.

Update our Makefile to build the generic platform instead of building
virt and sifive_u separately for RISC-V OpenSBI firmware, and change
to use fw_dynamic type images as well.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2cacd8414daf6a0643926392f05fd397ed1e9b66
      
https://github.com/qemu/qemu/commit/2cacd8414daf6a0643926392f05fd397ed1e9b66
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M Makefile
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c
    A pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
    R pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
    R pc-bios/opensbi-riscv32-virt-fw_jump.bin
    A pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
    R pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
    R pc-bios/opensbi-riscv64-virt-fw_jump.bin

  Log Message:
  -----------
  hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u

Update virt and sifive_u machines to use the opensbi fw_dynamic bios
image built for the generic FDT platform.

Remove the out-of-date no longer used bios images.

Note:

1. To test 32-bit Linux kernel on QEMU 'sifive_u' 32-bit machine,
   the following patch is needed:
   http://lists.infradead.org/pipermail/linux-riscv/2020-July/001213.html

2. To test 64-bit Linux 5.3 kernel on QEMU 'virt' or 'sifive_u' 64-bit
   machines, the following commit should be cherry-picked to 5.3:

   commit 922b0375fc93fb1a20c5617e37c389c26bbccb70
   Author: Albert Ou <aou@eecs.berkeley.edu>
   Date:   Fri Sep 27 16:14:18 2019 -0700

       riscv: Fix memblock reservation for device tree blob

   Linux 5.4 or above already contains this commit/fix.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: fad144392af50c0174becde83771fd2ff289bd1f
      
https://github.com/qemu/qemu/commit/fad144392af50c0174becde83771fd2ff289bd1f
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M Makefile
    M hw/riscv/spike.c
    A pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
    A pc-bios/opensbi-riscv64-generic-fw_dynamic.elf

  Log Message:
  -----------
  hw/riscv: spike: Change the default bios to use generic platform image

To keep sync with other RISC-V machines, change the default bios to
use generic platform fw_dynamic.elf image.

While we are here, add some comments to mention that using ELF files
for the Spike machine was intentional.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a52ea3e7d2a498e36a399b6ae39b5623e3864fce
      
https://github.com/qemu/qemu/commit/a52ea3e7d2a498e36a399b6ae39b5623e3864fce
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M .gitlab-ci.d/opensbi.yml

  Log Message:
  -----------
  gitlab-ci/opensbi: Update GitLab CI to build generic platform

This updates the GitLab CI opensbi job to build opensbi bios images
for the generic platform.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9ef82119b10d996cef63af679af5c1a7a85e6c19
      
https://github.com/qemu/qemu/commit/9ef82119b10d996cef63af679af5c1a7a85e6c19
  Author: Zong Li <zong.li@sifive.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Fix the translation of physical address

The real physical address should add the 12 bits page offset. It also
causes the PMP wrong checking due to the minimum granularity of PMP is
4 byte, but we always get the physical address which is 4KB alignment,
that means, we always use the start address of the page to check PMP for
all addresses which in the same page.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<370a983d0f9e8a9a927b9bb8af5e7bc84b1bf9b1.1595924470.git.zong.li@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: af3fc195e3c8e98b62eca3e4ee927f1965381dc3
      
https://github.com/qemu/qemu/commit/af3fc195e3c8e98b62eca3e4ee927f1965381dc3
  Author: Zong Li <zong.li@sifive.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M target/riscv/cpu_helper.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h

  Log Message:
  -----------
  target/riscv: Change the TLB page size depends on PMP entries.

The minimum granularity of PMP is 4 bytes, it is small than 4KB page
size, therefore, the pmp checking would be ignored if its range doesn't
start from the alignment of one page. This patch detects the pmp entries
and sets the small page size to TLB if there is a PMP entry which cover
the page size.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<6b0bf48662ef26ab4c15381a08e78a74ebd7ca79.1595924470.git.zong.li@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c43388bbfd0999edacc269e7d06eeaaf19b9d320
      
https://github.com/qemu/qemu/commit/c43388bbfd0999edacc269e7d06eeaaf19b9d320
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M hw/intc/ibex_plic.c

  Log Message:
  -----------
  hw/intc: ibex_plic: Update the pending irqs

After a claim or a priority change we need to update the pending
interrupts. This is based on the same patch for the SiFive PLIC:
55765822804f5a58594e "riscv: plic: Add a couple of mising
sifive_plic_update calls"

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: 
<0693aa700a4c67c49b3f1c973a82b257fdb7198d.1595655188.git.alistair.francis@wdc.com>


  Commit: 224914069d49cd186231000070d99ca04ee0550e
      
https://github.com/qemu/qemu/commit/224914069d49cd186231000070d99ca04ee0550e
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M hw/intc/ibex_plic.c
    M include/hw/intc/ibex_plic.h

  Log Message:
  -----------
  hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines

Once an interrupt has been claimed, but before it has been compelted we
shouldn't receive any more pending interrupts. This patche keeps track
of this to ensure that we don't see any more interrupts until it is
completed.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 
<394c3f070615ff2b4fab61a1cf9cb48c122913b7.1595655188.git.alistair.francis@wdc.com>


  Commit: 01c41d15de13104774d08e951db24815c8cffc79
      
https://github.com/qemu/qemu/commit/01c41d15de13104774d08e951db24815c8cffc79
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-08-21 (Fri, 21 Aug 2020)

  Changed paths:
    M hw/intc/ibex_plic.c

  Log Message:
  -----------
  hw/intc: ibex_plic: Honour source priorities

This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source
priorities" does and ensures that the highest priority interrupt will be
serviced first.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: 
<a697ca8a31eff8eb18a88e09a28206063cf85d48.1595655188.git.alistair.francis@wdc.com>


  Commit: 152be6de9100e58b5d896272e951d4c910bd735a
      
https://github.com/qemu/qemu/commit/152be6de9100e58b5d896272e951d4c910bd735a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-08-23 (Sun, 23 Aug 2020)

  Changed paths:
    M .gitlab-ci.d/opensbi.yml
    M Makefile
    M configure
    M hw/intc/ibex_plic.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/intc/ibex_plic.h
    M include/hw/riscv/sifive_u.h
    A pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
    A pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
    R pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
    R pc-bios/opensbi-riscv32-virt-fw_jump.bin
    A pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
    A pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
    R pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
    R pc-bios/opensbi-riscv64-virt-fw_jump.bin
    M roms/Makefile
    M roms/opensbi
    M target/riscv/cpu_helper.c
    M target/riscv/fpu_helper.c
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/internals.h
    M target/riscv/pmp.c
    M target/riscv/pmp.h
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20200821-1' into staging

The first RISC-V PR for the 5.2 window.

This includes:
 - NaNBox fixes
 - Vector extension improvements
 - a L2 cache controller
 - PMP fixes
 - Upgrade to OpenSBI v0.8 and the generic platform
 - Fixes for the Ibex PLIC

# gpg: Signature made Sat 22 Aug 2020 06:38:18 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200821-1:
  hw/intc: ibex_plic: Honour source priorities
  hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines
  hw/intc: ibex_plic: Update the pending irqs
  target/riscv: Change the TLB page size depends on PMP entries.
  target/riscv: Fix the translation of physical address
  gitlab-ci/opensbi: Update GitLab CI to build generic platform
  hw/riscv: spike: Change the default bios to use generic platform image
  hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
  roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware
  roms/opensbi: Upgrade from v0.7 to v0.8
  configure: Create symbolic links for pc-bios/*.elf files
  riscv: Fix bug in setting pmpcfg CSR for RISCV64
  hw/riscv: sifive_u: Add a dummy L2 cache controller device
  target/riscv: check before allocating TCG temps
  target/riscv: Clean up fmv.w.x
  target/riscv: Check nanboxed inputs in trans_rvf.inc.c
  target/riscv: Check nanboxed inputs to fp helpers
  target/riscv: Generate nanboxed results from trans_rvf.inc.c
  target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
  target/riscv: Generate nanboxed results from fp helpers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/d7df0ceee0fd...152be6de9100