[Qemu-commits] [qemu/qemu] e7e5a9: hw/arm/netduino2, netduinoplus2: Set system_clock_...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: e7e5a9595ab1136845c444141830fca0d2746a73
      
https://github.com/qemu/qemu/commit/e7e5a9595ab1136845c444141830fca0d2746a73
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-08-03 (Mon, 03 Aug 2020)

  Changed paths:
    M hw/arm/netduino2.c
    M hw/arm/netduinoplus2.c

  Log Message:
  -----------
  hw/arm/netduino2, netduinoplus2: Set system_clock_scale

The netduino2 and netduinoplus2 boards forgot to set the system_clock_scale
global, which meant that if guest code used the systick timer in "use
the processor clock" mode it would hang because time never advances.

Set the global to match the documented CPU clock speed of these boards.
Judging by the data sheet this is slightly simplistic because the
SoC allows configuration of the SYSCLK source and frequency via the
RCC (reset and clock control) module, but we don't model that.

Fixes: https://bugs.launchpad.net/qemu/+bug/1876187
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200727162617.26227-1-peter.maydell@linaro.org


  Commit: faf7c6de34fb8eaa566726cc658ba5ad81fb32af
      
https://github.com/qemu/qemu/commit/faf7c6de34fb8eaa566726cc658ba5ad81fb32af
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-08-03 (Mon, 03 Aug 2020)

  Changed paths:
    M include/hw/irq.h

  Log Message:
  -----------
  include/hw/irq.h: New function qemu_irq_is_connected()

Mostly devices don't need to care whether one of their output
qemu_irq lines is connected, because functions like qemu_set_irq()
silently do nothing if there is nothing on the other end.  However
sometimes a device might want to implement default behaviour for the
case where the machine hasn't wired the line up to anywhere.

Provide a function qemu_irq_is_connected() that devices can use for
this purpose.  (The test is trivial but encapsulating it in a
function makes it easier to see where we're doing it in case we need
to change the implementation later.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200728103744.6909-2-peter.maydell@linaro.org


  Commit: 9e60d759d38d1faae1d85de2c53411e635be3cf2
      
https://github.com/qemu/qemu/commit/9e60d759d38d1faae1d85de2c53411e635be3cf2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-08-03 (Mon, 03 Aug 2020)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M include/hw/arm/armv7m.h

  Log Message:
  -----------
  hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for 
SYSRESETREQ

The NVIC provides an outbound qemu_irq "SYSRESETREQ" which it signals
when the guest sets the SYSRESETREQ bit in the AIRCR register.  This
matches the hardware design (where the CPU has a signal of this name
and it is up to the SoC to connect that up to an actual reset
mechanism), but in QEMU it mostly results in duplicated code in SoC
objects and bugs where SoC model implementors forget to wire up the
SYSRESETREQ line.

Provide a default behaviour for the case where SYSRESETREQ is not
actually connected to anything: use qemu_system_reset_request() to
perform a system reset.  This will allow us to remove the
implementations of SYSRESETREQ handling from the boards where that's
exactly what it does, and also fixes the bugs in the board models
which forgot to wire up the signal:

 * microbit
 * mps2-an385
 * mps2-an505
 * mps2-an511
 * mps2-an521
 * musca-a
 * musca-b1
 * netduino
 * netduinoplus2

We still allow the board to wire up the signal if it needs to, in case
we need to model more complicated reset controller logic or to model
buggy SoC hardware which forgot to wire up the line itself. But
defaulting to "reset the system" is more often going to be correct
than defaulting to "do nothing".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200728103744.6909-3-peter.maydell@linaro.org


  Commit: fc6bb6e67e2f2b81de765a1c1ad5956de625ab19
      
https://github.com/qemu/qemu/commit/fc6bb6e67e2f2b81de765a1c1ad5956de625ab19
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-08-03 (Mon, 03 Aug 2020)

  Changed paths:
    M hw/arm/msf2-soc.c
    M hw/arm/stellaris.c

  Log Message:
  -----------
  msf2-soc, stellaris: Don't wire up SYSRESETREQ

The MSF2 SoC model and the Stellaris board code both wire
SYSRESETREQ up to a function that just invokes
    qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
This is now the default action that the NVIC does if the line is
not connected, so we can delete the handling code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200728103744.6909-4-peter.maydell@linaro.org


  Commit: 8796fe40dd30cd9ffd3c958906471715c923b341
      
https://github.com/qemu/qemu/commit/8796fe40dd30cd9ffd3c958906471715c923b341
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-08-03 (Mon, 03 Aug 2020)

  Changed paths:
    M target/arm/pauth_helper.c
    M tests/tcg/aarch64/Makefile.target
    A tests/tcg/aarch64/pauth-5.c

  Log Message:
  -----------
  target/arm: Fix AddPAC error indication

The definition of top_bit used in this function is one higher
than that used in the Arm ARM psuedo-code, which put the error
indication at top_bit - 1 at the wrong place, which meant that
it wasn't visible to Auth.

Fixing the definition of top_bit requires more changes, because
its most common use is for the count of bits in top_bit:bot_bit,
which would then need to be computed as top_bit - bot_bit + 1.

For now, prefer the minimal fix to the error indication alone.

Fixes: 63ff0ca94cb
Reported-by: Derrick McKee <derrick.mckee@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200728195706.11087-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: added comment about the divergence from the pseudocode]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 88a90e3de6ae99cbcfcc04c862c51f241fdf685f
      
https://github.com/qemu/qemu/commit/88a90e3de6ae99cbcfcc04c862c51f241fdf685f
  Author: Kaige Li <likaige@loongson.cn>
  Date:   2020-08-03 (Mon, 03 Aug 2020)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Avoid maybe-uninitialized warning with gcc 4.9

GCC version 4.9.4 isn't clever enough to figure out that all
execution paths in disas_ldst() that use 'fn' will have initialized
it first, and so it warns:

/home/LiKaige/qemu/target/arm/translate-a64.c: In function ‘disas_ldst’:
/home/LiKaige/qemu/target/arm/translate-a64.c:3392:5: error: ‘fn’ may be used 
uninitialized in this function [-Werror=maybe-uninitialized]
     fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s),
     ^
/home/LiKaige/qemu/target/arm/translate-a64.c:3318:22: note: ‘fn’ was declared 
here
     AtomicThreeOpFn *fn;
                      ^

Make it happy by initializing the variable to NULL.

Signed-off-by: Kaige Li <likaige@loongson.cn>
Message-id: 1596110248-7366-2-git-send-email-likaige@loongson.cn
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Clean up commit message and note which gcc version this was]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ce4f70e81ed23c93ff39234672aff33114532640
      
https://github.com/qemu/qemu/commit/ce4f70e81ed23c93ff39234672aff33114532640
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-08-03 (Mon, 03 Aug 2020)

  Changed paths:
    M hw/arm/nrf51_soc.c

  Log Message:
  -----------
  hw/arm/nrf51_soc: Set system_clock_scale

The nrf51 SoC model wasn't setting the system_clock_scale
global.which meant that if guest code used the systick timer in "use
the processor clock" mode it would hang because time never advances.

Set the global to match the documented CPU clock speed for this SoC.

This SoC in fact doesn't have a SysTick timer (which is the only thing
currently that cares about the system_clock_scale), because it's
a configurable option in the Cortex-M0. However our Cortex-M0 and
thus our nrf51 and our micro:bit board do provide a SysTick, so
we ought to provide a functional one rather than a broken one.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200727193458.31250-1-peter.maydell@linaro.org


  Commit: 13557fd392890cbd985bceba7f717e01efd674b8
      
https://github.com/qemu/qemu/commit/13557fd392890cbd985bceba7f717e01efd674b8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-08-03 (Mon, 03 Aug 2020)

  Changed paths:
    M hw/timer/imx_epit.c

  Log Message:
  -----------
  hw/timer/imx_epit: Avoid assertion when CR.SWR is written

The imx_epit device has a software-controllable reset triggered by
setting the SWR bit in the CR register. An error in commit cc2722ec83ad9
means that we will end up assert()ing if the guest does this, because
the code in imx_epit_write() starts ptimer transactions, and then
imx_epit_reset() also starts ptimer transactions, triggering
"ptimer_transaction_begin: Assertion `!s->in_transaction' failed".

The cleanest way to avoid this double-transaction is to move the
start-transaction for the CR write handling down below the check of
the SWR bit.

Fixes: https://bugs.launchpad.net/qemu/+bug/1880424
Fixes: cc2722ec83ad944505fe
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200727154550.3409-1-peter.maydell@linaro.org


  Commit: 5c1c3e4f02e458cf280c677c817ae4fd1ed9bf10
      
https://github.com/qemu/qemu/commit/5c1c3e4f02e458cf280c677c817ae4fd1ed9bf10
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-08-03 (Mon, 03 Aug 2020)

  Changed paths:
    M hw/arm/msf2-soc.c
    M hw/arm/netduino2.c
    M hw/arm/netduinoplus2.c
    M hw/arm/nrf51_soc.c
    M hw/arm/stellaris.c
    M hw/intc/armv7m_nvic.c
    M hw/timer/imx_epit.c
    M include/hw/arm/armv7m.h
    M include/hw/irq.h
    M target/arm/pauth_helper.c
    M target/arm/translate-a64.c
    M tests/tcg/aarch64/Makefile.target
    A tests/tcg/aarch64/pauth-5.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200803' 
into staging

target-arm queue:
 * hw/timer/imx_epit: Avoid assertion when CR.SWR is written
 * netduino2, netduinoplus2, microbit: set system_clock_scale so that
   SysTick running on the CPU clock works
 * target/arm: Avoid maybe-uninitialized warning with gcc 4.9
 * target/arm: Fix AddPAC error indication
 * Make AIRCR.SYSRESETREQ actually reset the system for the
   microbit, mps2-*, musca-*, netduino* boards

# gpg: Signature made Mon 03 Aug 2020 20:29:17 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200803:
  hw/timer/imx_epit: Avoid assertion when CR.SWR is written
  hw/arm/nrf51_soc: Set system_clock_scale
  target/arm: Avoid maybe-uninitialized warning with gcc 4.9
  target/arm: Fix AddPAC error indication
  msf2-soc, stellaris: Don't wire up SYSRESETREQ
  hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for 
SYSRESETREQ
  include/hw/irq.h: New function qemu_irq_is_connected()
  hw/arm/netduino2, netduinoplus2: Set system_clock_scale

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/45a150aa2b34...5c1c3e4f02e4