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[Qemu-commits] [qemu/qemu] 4bf7c0: ACPI: Assert that we don't run out of
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] 4bf7c0: ACPI: Assert that we don't run out of the prealloc... |
Date: |
Tue, 28 Jul 2020 11:45:30 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 4bf7c0cb09a59314aca261291e3a20a24c7dd3b3
https://github.com/qemu/qemu/commit/4bf7c0cb09a59314aca261291e3a20a24c7dd3b3
Author: Dongjiu Geng <gengdongjiu@huawei.com>
Date: 2020-07-27 (Mon, 27 Jul 2020)
Changed paths:
M hw/acpi/ghes.c
Log Message:
-----------
ACPI: Assert that we don't run out of the preallocated memory
data_length is a constant value, so we use assert instead of
condition check.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Message-id: 20200622113146.33421-1-gengdongjiu@huawei.com
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ca05a240d4fa2ce880c630058b635482d3d472f8
https://github.com/qemu/qemu/commit/ca05a240d4fa2ce880c630058b635482d3d472f8
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-07-27 (Mon, 27 Jul 2020)
Changed paths:
M hw/misc/aspeed_sdmc.c
Log Message:
-----------
hw/misc/aspeed_sdmc: Fix incorrect memory size
The SDRAM Memory Controller has a 32-bit address bus, thus
supports up to 4 GiB of DRAM. There is a signed to unsigned
conversion error with the AST2600 maximum memory size:
(uint64_t)(2048 << 20) = (uint64_t)(-2147483648)
= 0xffffffff40000000
= 16 EiB - 2 GiB
Fix by using the IEC suffixes which are usually safer, and add
an assertion check to verify the memory is valid. This would have
caught this bug:
$ qemu-system-arm -M ast2600-evb
qemu-system-arm: hw/misc/aspeed_sdmc.c:258: aspeed_sdmc_realize: Assertion
`asc->max_ram_size < 4 * GiB' failed.
Aborted (core dumped)
Fixes: 1550d72679 ("aspeed/sdmc: Add AST2600 support")
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a6d6f37aed4b171d121cd4a9363fbb41e90dcb53
https://github.com/qemu/qemu/commit/a6d6f37aed4b171d121cd4a9363fbb41e90dcb53
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-07-27 (Mon, 27 Jul 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Always pass cacheattr in S1_ptw_translate
When we changed the interface of get_phys_addr_lpae to require
the cacheattr parameter, this spot was missed. The compiler is
unable to detect the use of NULL vs the nonnull attribute here.
Fixes: 7e98e21c098
Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Jan Kiszka <jan.kiskza@siemens.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 222f45b75970452b864f80cc4c0d3eb8f4862f64
https://github.com/qemu/qemu/commit/222f45b75970452b864f80cc4c0d3eb8f4862f64
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-07-27 (Mon, 27 Jul 2020)
Changed paths:
M docs/system/arm/virt.rst
Log Message:
-----------
docs/system/arm/virt: Document 'mte' machine option
Commit 6a0b7505f1fd6769c which added documentation of the virt board
crossed in the post with commit 6f4e1405b91da0d0 which added a new
'mte' machine option. Update the docs to include the new option.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 24ac0d309ab379cd0347f198c2db5b2b48b02887
https://github.com/qemu/qemu/commit/24ac0d309ab379cd0347f198c2db5b2b48b02887
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-07-27 (Mon, 27 Jul 2020)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: Fix PAUTH for EL3 direct kernel boot
When booting an EL3 cpu with -kernel, we set up EL3 and then
drop down to EL2. We need to enable access to v8.3-PAuth
keys and instructions at EL3 before doing so.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200724163853.504655-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7ad01d78a9f2e80d1be41226d98f34059f7fff90
https://github.com/qemu/qemu/commit/7ad01d78a9f2e80d1be41226d98f34059f7fff90
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-07-27 (Mon, 27 Jul 2020)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: Fix MTE for EL3 direct kernel boot
When booting an EL3 cpu with -kernel, we set up EL3 and then
drop down to EL2. We need to enable access to v8.5-MemTag
tag allocation at EL3 before doing so.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200724163853.504655-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d4f6dda182e19afa75706936805e18397cb95f07
https://github.com/qemu/qemu/commit/d4f6dda182e19afa75706936805e18397cb95f07
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-07-27 (Mon, 27 Jul 2020)
Changed paths:
M target/arm/mte_helper.c
Log Message:
-----------
target/arm: Improve IMPDEF algorithm for IRG
When GCR_EL1.RRND==1, the choosing of the random value is IMPDEF,
and the kernel is not expected to have set RGSR_EL1. Force a
non-zero value into SEED, so that we do not continually return
the same tag.
Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200724163853.504655-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3461487523b897d324e8d91f3fd20ed55f849544
https://github.com/qemu/qemu/commit/3461487523b897d324e8d91f3fd20ed55f849544
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-07-28 (Tue, 28 Jul 2020)
Changed paths:
M docs/system/arm/virt.rst
M hw/acpi/ghes.c
M hw/arm/boot.c
M hw/misc/aspeed_sdmc.c
M target/arm/helper.c
M target/arm/mte_helper.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200727'
into staging
target-arm queue:
* ACPI: Assert that we don't run out of the preallocated memory
* hw/misc/aspeed_sdmc: Fix incorrect memory size
* target/arm: Always pass cacheattr in S1_ptw_translate
* docs/system/arm/virt: Document 'mte' machine option
* hw/arm/boot: Fix PAUTH, MTE for EL3 direct kernel boot
* target/arm: Improve IMPDEF algorithm for IRG
# gpg: Signature made Mon 27 Jul 2020 16:18:38 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200727:
target/arm: Improve IMPDEF algorithm for IRG
hw/arm/boot: Fix MTE for EL3 direct kernel boot
hw/arm/boot: Fix PAUTH for EL3 direct kernel boot
docs/system/arm/virt: Document 'mte' machine option
target/arm: Always pass cacheattr in S1_ptw_translate
hw/misc/aspeed_sdmc: Fix incorrect memory size
ACPI: Assert that we don't run out of the preallocated memory
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/0c4fa5bc1aa4...3461487523b8
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