[Qemu-commits] [qemu/qemu] 8380b3: goldfish_rtc: Fix non-atomic read behaviour of TIM...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8380b3a453c38f040e7ca2105418802344cc23d0
      
https://github.com/qemu/qemu/commit/8380b3a453c38f040e7ca2105418802344cc23d0
  Author: Jessica Clarke <jrtc27@jrtc27.com>
  Date:   2020-07-22 (Wed, 22 Jul 2020)

  Changed paths:
    M hw/rtc/goldfish_rtc.c
    M include/hw/rtc/goldfish_rtc.h

  Log Message:
  -----------
  goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH

The specification says:

   0x00  TIME_LOW   R: Get current time, then return low-order 32-bits.
   0x04  TIME_HIGH  R: Return high 32-bits from previous TIME_LOW read.

   ...

   To read the value, the kernel must perform an IO_READ(TIME_LOW),
   which returns an unsigned 32-bit value, before an IO_READ(TIME_HIGH),
   which returns a signed 32-bit value, corresponding to the higher half
   of the full value.

However, we were just returning the current time for both. If the guest
is unlucky enough to read TIME_LOW and TIME_HIGH either side of an
overflow of the lower half, it will see time be in the future, before
jumping backwards on the next read, and Linux currently relies on the
atomicity guaranteed by the spec so is affected by this. Fix this
violation of the spec by caching the correct value for TIME_HIGH
whenever TIME_LOW is read, and returning that value for any TIME_HIGH
read.

Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200718004934.83174-1-jrtc27@jrtc27.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: eabfeb0cb9e054108b3e29a3a85363b3d80d9c38
      
https://github.com/qemu/qemu/commit/eabfeb0cb9e054108b3e29a3a85363b3d80d9c38
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-22 (Wed, 22 Jul 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.inc.c

  Log Message:
  -----------
  target/riscv: Quiet Coverity complains about vamo*

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200721133742.2298-1-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3e09396e36dff4234afd6f6fd51861949be383e1
      
https://github.com/qemu/qemu/commit/3e09396e36dff4234afd6f6fd51861949be383e1
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2020-07-22 (Wed, 22 Jul 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.inc.c

  Log Message:
  -----------
  target/riscv: fix vector index load/store constraints

Although not explicitly specified that the the destination
vector register groups cannot overlap the source vector register group,
it is still necessary.

And this constraint has been added to the v0.8 spec.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e79d27cb322b60b460b709d2c74ff7d77cde0565
      
https://github.com/qemu/qemu/commit/e79d27cb322b60b460b709d2c74ff7d77cde0565
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2020-07-22 (Wed, 22 Jul 2020)

  Changed paths:
    M hw/riscv/sifive_e.c

  Log Message:
  -----------
  hw/riscv: sifive_e: Correct debug block size

Currently the debug region size is set to 0x100, but according to
FE310-G000 and FE310-G002 manuals:

  FE310-G000: 0x100 - 0xFFF
  FE310-G002: 0x0   - 0xFFF

Change the size to 0x1000 that applies to both.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1594891856-15474-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d
      
https://github.com/qemu/qemu/commit/8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d
  Author: Zong Li <zong.li@sifive.com>
  Date:   2020-07-22 (Wed, 22 Jul 2020)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix the range of pmpcfg of CSR funcion table

The range of Physical Memory Protection should be from CSR_PMPCFG0
to CSR_PMPCFG3, not to CSR_PMPADDR9.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-Id: 
<eae49e9252c9596e4f3bdb471772f79235141a87.1595335112.git.zong.li@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 09e0cd773723219d21655587954da2769f64ba01
      
https://github.com/qemu/qemu/commit/09e0cd773723219d21655587954da2769f64ba01
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-07-23 (Thu, 23 Jul 2020)

  Changed paths:
    M hw/riscv/sifive_e.c
    M hw/rtc/goldfish_rtc.c
    M include/hw/rtc/goldfish_rtc.h
    M target/riscv/csr.c
    M target/riscv/insn_trans/trans_rvv.inc.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20200722-1' into staging

This PR contains a few RISC-V fixes.

The main fix is the correction of the goldfish RTC time. On top of that
some small fixes to the recently added vector extensions have been added
(including an assert that fixed a coverity report). There is a change in
the SiFive E debug memory size to match hardware. Finally there is a fix
for PMP accesses.

# gpg: Signature made Wed 22 Jul 2020 17:43:59 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200722-1:
  target/riscv: Fix the range of pmpcfg of CSR funcion table
  hw/riscv: sifive_e: Correct debug block size
  target/riscv: fix vector index load/store constraints
  target/riscv: Quiet Coverity complains about vamo*
  goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/8ffa52c20d56...09e0cd773723