[Qemu-commits] [qemu/qemu] e92fb0: MAINTAINERS: Add an entry for OpenSBI firmware

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: e92fb01639cadbeb9c6fc5d5189e35ef3e45836f
      
https://github.com/qemu/qemu/commit/e92fb01639cadbeb9c6fc5d5189e35ef3e45836f
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add an entry for OpenSBI firmware

List me as the maintainer for OpenSBI firmware related files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <1593177220-28143-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2c44bbf32cda5fbf85b697e3a12127f59d2c2e80
      
https://github.com/qemu/qemu/commit/2c44bbf32cda5fbf85b697e3a12127f59d2c2e80
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Sort the SoC memmap table entries

Adjust the PCIe memory maps to follow the order.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1593746511-19517-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 43cf723adca9a5e188c664c3b606a585192a599c
      
https://github.com/qemu/qemu/commit/43cf723adca9a5e188c664c3b606a585192a599c
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  riscv: Unify Qemu's reset vector code path

Currently, all riscv machines except sifive_u have identical reset vector
code implementations with memory addresses being different for all machines.
They can be easily combined into a single function in common code.

Move it to common function and let all the machines use the common function.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-2-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 66b1205bc5ab8bb3f5e12fa4155bbeb56e6724e9
      
https://github.com/qemu/qemu/commit/66b1205bc5ab8bb3f5e12fa4155bbeb56e6724e9
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  RISC-V: Copy the fdt in dram instead of ROM

Currently, the fdt is copied to the ROM after the reset vector. The firmware
has to copy it to DRAM. Instead of this, directly copy the device tree to a
pre-computed dram address. The device tree load address should be as far as
possible from kernel and initrd images. That's why it is kept at the end of
the DRAM or 4GB whichever is lesser.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-3-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: dc144fe13d336caac2f03b57f1df738e84f984ec
      
https://github.com/qemu/qemu/commit/dc144fe13d336caac2f03b57f1df738e84f984ec
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h
    A include/hw/riscv/boot_opensbi.h

  Log Message:
  -----------
  riscv: Add opensbi firmware dynamic support

OpenSBI is the default firmware in Qemu and has various firmware loading
options. Currently, qemu loader uses fw_jump which has a compile time
pre-defined address where fdt & kernel image must reside. This puts a
constraint on image size of the Linux kernel depending on the fdt location
and available memory. However, fw_dynamic allows the loader to specify
the next stage location (i.e. Linux kernel/U-Boot) in memory and other
configurable boot options available in OpenSBI.

Add support for OpenSBI dynamic firmware loading support. This doesn't
break existing setup and fw_jump will continue to work as it is. Any
other firmware will continue to work without any issues as long as it
doesn't expect anything specific from loader in "a2" register.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-4-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8590f53661ec678fd3aa97b4da212b0c00056c2e
      
https://github.com/qemu/qemu/commit/8590f53661ec678fd3aa97b4da212b0c00056c2e
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  RISC-V: Support 64 bit start address

Even though the start address in ROM code is declared as a 64 bit address
for RV64, it can't be used as upper bits are set to zero in ROM code.

Update the ROM code correctly to reflect the 64bit value.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-5-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9eb8b14a70e57bc1449afc08aa4bf3131ee680d8
      
https://github.com/qemu/qemu/commit/9eb8b14a70e57bc1449afc08aa4bf3131ee680d8
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: Modify MROM size to end at 0x10000

At present the size of Mask ROM for sifive_u / spike / virt machines
is set to 0x11000, which ends at an unusual address. This changes the
size to 0xf000 so that it ends at 0x10000.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7acafcfa844fd93f5ff073077007627338bd6739
      
https://github.com/qemu/qemu/commit/7acafcfa844fd93f5ff073077007627338bd6739
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.inc.c

  Log Message:
  -----------
  target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion

gvec should provide vecop_list to avoid:
"tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1989205c4e973bc7f9fac0ce0700993f30582538
      
https://github.com/qemu/qemu/commit/1989205c4e973bc7f9fac0ce0700993f30582538
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.inc.c

  Log Message:
  -----------
  target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a69f97c1110205bc173657c77ce2d16877cad683
      
https://github.com/qemu/qemu/commit/a69f97c1110205bc173657c77ce2d16877cad683
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.inc.c

  Log Message:
  -----------
  target/riscv: fix return value of do_opivx_widen()

do_opivx_widen() should return false if check function returns false.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-4-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: fbcbafa2c1c33ae6630e7717f7f4141befb5b31a
      
https://github.com/qemu/qemu/commit/fbcbafa2c1c33ae6630e7717f7f4141befb5b31a
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: fix vill bit index in vtype register

vill bit is at vtype[XLEN-1].

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-5-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 940aabb9f47712da87182fee7163f1d3f7def36d
      
https://github.com/qemu/qemu/commit/940aabb9f47712da87182fee7163f1d3f7def36d
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M hw/char/ibex_uart.c
    M include/hw/char/ibex_uart.h

  Log Message:
  -----------
  hw/char: Convert the Ibex UART to use the qdev Clock model

Conver the Ibex UART to use the recently added qdev-clock functions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 
b0136fad870a29049959ec161c1217b967d7e19d.1594332223.git.alistair.francis@wdc.com
Message-Id: 
<b0136fad870a29049959ec161c1217b967d7e19d.1594332223.git.alistair.francis@wdc.com>


  Commit: 59093cc407cb044c72aa786006a07bd404eb36b9
      
https://github.com/qemu/qemu/commit/59093cc407cb044c72aa786006a07bd404eb36b9
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M hw/char/ibex_uart.c
    M include/hw/char/ibex_uart.h

  Log Message:
  -----------
  hw/char: Convert the Ibex UART to use the registerfields API

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 
06372c9cdeec715077899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com
Message-Id: 
<06372c9cdeec715077899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com>


  Commit: 895bfa84fec27899bf8e8c17f46358d31df2ab4f
      
https://github.com/qemu/qemu/commit/895bfa84fec27899bf8e8c17f46358d31df2ab4f
  Author: Liao Pingfang <liao.pingfang@zte.com.cn>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  tcg/riscv: Remove superfluous breaks

Remove superfluous breaks, as there is a "return" before them.

Signed-off-by: Liao Pingfang <liao.pingfang@zte.com.cn>
Signed-off-by: Yi Wang <wang.yi59@zte.com.cn>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1594600421-22942-1-git-send-email-wang.yi59@zte.com.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cfad709bceb629a4ebeb5d8a3acd1871b9a6436b
      
https://github.com/qemu/qemu/commit/cfad709bceb629a4ebeb5d8a3acd1871b9a6436b
  Author: Alexandre Mergnat <amergnat@baylibre.com>
  Date:   2020-07-13 (Mon, 13 Jul 2020)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: Fix pmp NA4 implementation

The end address calculation for NA4 mode is wrong because the address
used isn't shifted.

It doesn't watch 4 bytes but a huge range because the end address
calculation is wrong.

The solution is to use the shifted address calculated for start address
variable.

Modifications are tested on Zephyr OS userspace test suite which works
for other RISC-V boards (E31 and E34 core).

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200706084550.24117-1-amergnat@baylibre.com
Message-Id: <20200706084550.24117-1-amergnat@baylibre.com>
[ Changes by AF:
 - Improve the commit title and message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: aeb07b5f6e69ce93afea71027325e3e7a22d2149
      
https://github.com/qemu/qemu/commit/aeb07b5f6e69ce93afea71027325e3e7a22d2149
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-07-14 (Tue, 14 Jul 2020)

  Changed paths:
    M MAINTAINERS
    M hw/char/ibex_uart.c
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/char/ibex_uart.h
    M include/hw/riscv/boot.h
    A include/hw/riscv/boot_opensbi.h
    M target/riscv/cpu.h
    M target/riscv/insn_trans/trans_rvv.inc.c
    M target/riscv/pmp.c
    M tcg/riscv/tcg-target.inc.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20200713' into staging

This is a colection of bug fixes and small imrprovements for RISC-V.

This includes some vector extensions fixes, a PMP bug fix, OpenTitan
UART bug fix and support for OpenSBI dynamic firmware.

# gpg: Signature made Tue 14 Jul 2020 01:29:44 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200713:
  target/riscv: Fix pmp NA4 implementation
  tcg/riscv: Remove superfluous breaks
  hw/char: Convert the Ibex UART to use the registerfields API
  hw/char: Convert the Ibex UART to use the qdev Clock model
  target/riscv: fix vill bit index in vtype register
  target/riscv: fix return value of do_opivx_widen()
  target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
  target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
  hw/riscv: Modify MROM size to end at 0x10000
  RISC-V: Support 64 bit start address
  riscv: Add opensbi firmware dynamic support
  RISC-V: Copy the fdt in dram instead of ROM
  riscv: Unify Qemu's reset vector code path
  hw/riscv: virt: Sort the SoC memmap table entries
  MAINTAINERS: Add an entry for OpenSBI firmware

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/beff47a2f6a8...aeb07b5f6e69