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[Qemu-commits] [qemu/qemu] 9c49c8: hw/ssi/imx_spi: changed while stateme
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 9c49c8: hw/ssi/imx_spi: changed while statement to prevent... |
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Date: |
Mon, 08 Jun 2020 03:15:28 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 9c49c83e4b23d31676633a1189faa6e70b489c01
https://github.com/qemu/qemu/commit/9c49c83e4b23d31676633a1189faa6e70b489c01
Author: Eden Mikitas <e.mikitas@gmail.com>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M hw/ssi/imx_spi.c
Log Message:
-----------
hw/ssi/imx_spi: changed while statement to prevent underflow
The while statement in question only checked if tx_burst is not 0.
tx_burst is a signed int, which is assigned the value put by the
guest driver in ECSPI_CONREG. The burst length can be anywhere
between 1 and 4096, and since tx_burst is always decremented by 8
it could possibly underflow, causing an infinite loop.
Signed-off-by: Eden Mikitas <e.mikitas@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6d686145c86c9712db1547f66bebb7131979c61b
https://github.com/qemu/qemu/commit/6d686145c86c9712db1547f66bebb7131979c61b
Author: Eden Mikitas <e.mikitas@gmail.com>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M hw/ssi/imx_spi.c
Log Message:
-----------
hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave
When inserting the value retrieved (rx) from the spi slave, rx is pushed to
rx_fifo after being cast to uint8_t. rx_fifo is a fifo32, and the rx
register the driver uses is also 32 bit. This zeroes the 24 most
significant bits of rx. This proved problematic with devices that expect to
use the whole 32 bits of the rx register.
Signed-off-by: Eden Mikitas <e.mikitas@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3a37f23979ac8179dd297b45cd23020a610002ef
https://github.com/qemu/qemu/commit/3a37f23979ac8179dd297b45cd23020a610002ef
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M hw/input/pxa2xx_keypad.c
Log Message:
-----------
hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
hw_error() calls exit(). This a bit overkill when we can log
the accesses as unimplemented or guest error.
When fuzzing the devices, we don't want the whole process to
exit. Replace some hw_error() calls by qemu_log_mask()
(missed in commit 5a0001ec7e).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200525114123.21317-2-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fc417e5b5784eec92163ad36140ab029c6661b5f
https://github.com/qemu/qemu/commit/fc417e5b5784eec92163ad36140ab029c6661b5f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M hw/arm/pxa2xx.c
Log Message:
-----------
hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
Replace printf() calls by qemu_log_mask(), which is disabled
by default. This avoid flooding the terminal when fuzzing the
device.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200525114123.21317-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a04b68e1d4c4f0cd5cd7542697b1b230b84532f5
https://github.com/qemu/qemu/commit/a04b68e1d4c4f0cd5cd7542697b1b230b84532f5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/crypto_helper.c
M target/arm/helper.h
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/vec_helper.c
A target/arm/vec_internal.h
Log Message:
-----------
target/arm: Convert aes and sm4 to gvec helpers
With this conversion, we will be able to use the same helpers
with sve. In particular, pass 3 vector parameters for the
3-operand operations; for advsimd the destination register
is also an input.
This also fixes a bug in which we failed to clear the high bits
of the SVE register after an AdvSIMD operation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1738860d7e60dec5dbeba17f8b44d31aae3accac
https://github.com/qemu/qemu/commit/1738860d7e60dec5dbeba17f8b44d31aae3accac
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/crypto_helper.c
M target/arm/helper.h
M target/arm/translate-a64.c
M target/arm/translate-a64.h
Log Message:
-----------
target/arm: Convert rax1 to gvec helpers
With this conversion, we will be able to use the same helpers
with sve. This also fixes a bug in which we failed to clear
the high bits of the SVE register after an AdvSIMD operation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: aaffebd6d3135b8aed7e61932af53b004d261579
https://github.com/qemu/qemu/commit/aaffebd6d3135b8aed7e61932af53b004d261579
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/crypto_helper.c
M target/arm/helper.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Convert sha512 and sm3 to gvec helpers
Do not yet convert the helpers to loop over opr_sz, but the
descriptor allows the vector tail to be cleared. Which fixes
an existing bug vs SVE.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: effa992f153f5e7ab97ab843b565690748c5b402
https://github.com/qemu/qemu/commit/effa992f153f5e7ab97ab843b565690748c5b402
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/crypto_helper.c
M target/arm/helper.h
M target/arm/neon-dp.decode
M target/arm/translate-a64.c
M target/arm/translate-neon.inc.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert sha1 and sha256 to gvec helpers
Do not yet convert the helpers to loop over opr_sz, but the
descriptor allows the vector tail to be cleared. Which fixes
an existing bug vs SVE.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: afc8b7d32668547308bdd654a63cf5228936e0ba
https://github.com/qemu/qemu/commit/afc8b7d32668547308bdd654a63cf5228936e0ba
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/crypto_helper.c
M target/arm/helper.h
M target/arm/neon-dp.decode
M target/arm/translate-a64.c
M target/arm/translate-neon.inc.c
Log Message:
-----------
target/arm: Split helper_crypto_sha1_3reg
Rather than passing an opcode to a helper, fully decode the
operation at translate time. Use clear_tail_16 to zap the
balance of the SVE register with the AdvSIMD write.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 43fa36c96c24349145497adc1b451f9caf74e344
https://github.com/qemu/qemu/commit/43fa36c96c24349145497adc1b451f9caf74e344
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/crypto_helper.c
M target/arm/helper.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Split helper_crypto_sm3tt
Rather than passing an opcode to a helper, fully decode the
operation at translate time. Use clear_tail_16 to zap the
balance of the SVE register with the AdvSIMD write.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d04bf49c9ee8fa3e8f2961462a9f053c3faa8548
https://github.com/qemu/qemu/commit/d04bf49c9ee8fa3e8f2961462a9f053c3faa8548
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M hw/adc/stm32f2xx_adc.c
Log Message:
-----------
hw/adc/stm32f2xx_adc: Correct memory region size and access size
The ADC region size is 256B, split as:
- [0x00 - 0x4f] defined
- [0x50 - 0xff] reserved
All registers are 32-bit (thus when the datasheet mentions the
last defined register is 0x4c, it means its address range is
0x4c .. 0x4f.
This model implementation is also 32-bit. Set MemoryRegionOps
'impl' fields.
See:
'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map".
Reported-by: Seth Kintigh <skintigh@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200603055915.17678-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 27dfbafaa78c3937122954cb0706e4e203812c56
https://github.com/qemu/qemu/commit/27dfbafaa78c3937122954cb0706e4e203812c56
Author: Thomas Huth <thuth@redhat.com>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
tests/acceptance: Add a boot test for the xlnx-versal-virt machine
As described by Edgar here:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg605124.html
we can use the Ubuntu kernel for testing the xlnx-versal-virt machine.
So let's add a boot test for this now.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200525141237.15243-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7a1e049a707149b306b7b65c66d504d251c0a4b0
https://github.com/qemu/qemu/commit/7a1e049a707149b306b7b65c66d504d251c0a4b0
Author: Cédric Le Goater <clg@kaod.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
A docs/system/arm/aspeed.rst
M docs/system/target-arm.rst
Log Message:
-----------
docs/system: Document Aspeed boards
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200602135050.593692-1-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3d46938bbbd7cea47ab9b994c0438aea3d10d98f
https://github.com/qemu/qemu/commit/3d46938bbbd7cea47ab9b994c0438aea3d10d98f
Author: Paul Zimmerman <pauldzim@gmail.com>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M hw/arm/bcm2835_peripherals.c
M hw/misc/Makefile.objs
A hw/misc/bcm2835_mphi.c
M include/hw/arm/bcm2835_peripherals.h
A include/hw/misc/bcm2835_mphi.h
Log Message:
-----------
raspi: add BCM2835 SOC MPHI emulation
Add BCM2835 SOC MPHI (Message-based Parallel Host Interface)
emulation. It is very basic, only providing the FIQ interrupt
needed to allow the dwc-otg USB host controller driver in the
Raspbian kernel to function.
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Acked-by: Philippe Mathieu-Daude <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200520235349.21215-2-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3f5b312a3f9faf2e20a700be70d921e26220a0fe
https://github.com/qemu/qemu/commit/3f5b312a3f9faf2e20a700be70d921e26220a0fe
Author: Paul Zimmerman <pauldzim@gmail.com>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
A include/hw/usb/dwc2-regs.h
Log Message:
-----------
dwc-hsotg (dwc2) USB host controller register definitions
Import the dwc-hsotg (dwc2) register definitions file from the
Linux kernel. This is a copy of drivers/usb/dwc2/hw.h from the
mainline Linux kernel, the only changes being to the header, and
two instances of 'u32' changed to 'uint32_t' to allow it to
compile. Checkpatch throws a boatload of errors due to the tab
indentation, but I would rather import it as-is than reformat it.
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-3-pauldzim@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 104a010f24f7ae9d16ff67bce66c309a4a070915
https://github.com/qemu/qemu/commit/104a010f24f7ae9d16ff67bce66c309a4a070915
Author: Paul Zimmerman <pauldzim@gmail.com>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
A hw/usb/hcd-dwc2.h
Log Message:
-----------
dwc-hsotg (dwc2) USB host controller state definitions
Add the dwc-hsotg (dwc2) USB host controller state definitions.
Mostly based on hw/usb/hcd-ehci.h.
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-4-pauldzim@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 153ef1662c35ba3d3bbcedefe8dc24cfa4e8c33d
https://github.com/qemu/qemu/commit/153ef1662c35ba3d3bbcedefe8dc24cfa4e8c33d
Author: Paul Zimmerman <pauldzim@gmail.com>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M hw/usb/Kconfig
M hw/usb/Makefile.objs
A hw/usb/hcd-dwc2.c
M hw/usb/trace-events
Log Message:
-----------
dwc-hsotg (dwc2) USB host controller emulation
Add the dwc-hsotg (dwc2) USB host controller emulation code.
Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c.
Note that to use this with the dwc-otg driver in the Raspbian
kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0" on
the kernel command line.
Emulation of slave mode and of descriptor-DMA mode has not been
implemented yet. These modes are seldom used.
I have used some on-line sources of information while developing
this emulation, including:
http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf
which has a pretty complete description of the controller starting
on page 370.
https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf
which has a description of the controller registers starting on
page 130.
Thanks to Felippe Mathieu-Daude for providing a cleaner method
of implementing the memory regions for the controller registers.
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-5-pauldzim@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7ad3d51ebb8a522ffcad391c4bef281245739dde
https://github.com/qemu/qemu/commit/7ad3d51ebb8a522ffcad391c4bef281245739dde
Author: Paul Zimmerman <pauldzim@gmail.com>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M hw/usb/dev-storage.c
Log Message:
-----------
usb: add short-packet handling to usb-storage driver
The dwc-hsotg (dwc2) USB host depends on a short packet to
indicate the end of an IN transfer. The usb-storage driver
currently doesn't provide this, so fix it.
I have tested this change rather extensively using a PC
emulation with xhci, ehci, and uhci controllers, and have
not observed any regressions.
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200520235349.21215-6-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 60bf734e647f8a6e243766929813358c9fcd4335
https://github.com/qemu/qemu/commit/60bf734e647f8a6e243766929813358c9fcd4335
Author: Paul Zimmerman <pauldzim@gmail.com>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M hw/arm/bcm2835_peripherals.c
M include/hw/arm/bcm2835_peripherals.h
Log Message:
-----------
wire in the dwc-hsotg (dwc2) USB host controller emulation
Wire the dwc-hsotg (dwc2) emulation into Qemu
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
Message-id: 20200520235349.21215-7-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d02ded087030d2b5b5906b127d616acb2a6d1483
https://github.com/qemu/qemu/commit/d02ded087030d2b5b5906b127d616acb2a6d1483
Author: Paul Zimmerman <pauldzim@gmail.com>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host
Add a check for functional dwc-hsotg (dwc2) USB host emulation to
the Raspi 2 acceptance test
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org>
Message-id: 20200520235349.21215-8-pauldzim@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d3c8c736f8b4bdd02831076286b1788232f46ced
https://github.com/qemu/qemu/commit/d3c8c736f8b4bdd02831076286b1788232f46ced
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/neon-dp.decode
M target/arm/translate-neon.inc.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
Convert the VSHL and VSLI insns from the Neon 2-registers-and-a-shift
group to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-2-peter.maydell@linaro.org
Commit: 66432d6b8294e3508218b360acfdf7c244eea993
https://github.com/qemu/qemu/commit/66432d6b8294e3508218b360acfdf7c244eea993
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/neon-dp.decode
M target/arm/translate-neon.inc.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree
Convert the VSHR 2-reg-shift insns to decodetree.
Note that unlike the legacy decoder, we present the right shift
amount to the trans_ function as a positive integer.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-3-peter.maydell@linaro.org
Commit: 434f71ef96d69dbf57d6bb3883a15d2d0b32dea8
https://github.com/qemu/qemu/commit/434f71ef96d69dbf57d6bb3883a15d2d0b32dea8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/neon-dp.decode
M target/arm/translate-neon.inc.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to
decodetree
Convert the VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree.
(These are the last instructions in the group that are vectorized;
the rest all require looping over each element.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-4-peter.maydell@linaro.org
Commit: 37bfce81b10450071193c8495a07f182ec652e2a
https://github.com/qemu/qemu/commit/37bfce81b10450071193c8495a07f182ec652e2a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/neon-dp.decode
M target/arm/translate-neon.inc.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree
Convert the VQSHLU and QVSHL 2-reg-shift insns to decodetree.
These are the last of the simple shift-by-immediate insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-5-peter.maydell@linaro.org
Commit: 712182d340e33c2ce86143f25fb2f04ae23d90de
https://github.com/qemu/qemu/commit/712182d340e33c2ce86143f25fb2f04ae23d90de
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/neon-dp.decode
M target/arm/translate-neon.inc.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert Neon narrowing shifts with op==8 to decodetree
Convert the Neon narrowing shifts where op==8 to decodetree:
* VSHRN
* VRSHRN
* VQSHRUN
* VQRSHRUN
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-6-peter.maydell@linaro.org
Commit: b4a3a77bb7a0dff1cc5673fe3be467d9e3635d44
https://github.com/qemu/qemu/commit/b4a3a77bb7a0dff1cc5673fe3be467d9e3635d44
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/neon-dp.decode
M target/arm/translate-neon.inc.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert Neon narrowing shifts with op==9 to decodetree
Convert the remaining Neon narrowing shifts to decodetree:
* VQSHRN
* VQRSHRN
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-7-peter.maydell@linaro.org
Commit: 968bf842742a5ffbb0041cb31089e61a9f7a833d
https://github.com/qemu/qemu/commit/968bf842742a5ffbb0041cb31089e61a9f7a833d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/neon-dp.decode
M target/arm/translate-neon.inc.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert Neon VSHLL, VMOVL to decodetree
Convert the VSHLL and VMOVL insns from the 2-reg-shift group
to decodetree. Since the loop always has two passes, we unroll
it to avoid the awkward reassignment of one TCGv to another.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-8-peter.maydell@linaro.org
Commit: 3da26f11711caeaa18318b6afa14dfb81d7650ab
https://github.com/qemu/qemu/commit/3da26f11711caeaa18318b6afa14dfb81d7650ab
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/neon-dp.decode
M target/arm/translate-neon.inc.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert VCVT fixed-point ops to decodetree
Convert the VCVT fixed-point conversion operations in the
Neon 2-regs-and-shift group to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-9-peter.maydell@linaro.org
Commit: 2c35a39eda0b16c2ed85c94cec204bf5efb97812
https://github.com/qemu/qemu/commit/2c35a39eda0b16c2ed85c94cec204bf5efb97812
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
M target/arm/neon-dp.decode
M target/arm/translate-neon.inc.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Convert Neon one-register-and-immediate insns to decodetree
Convert the insns in the one-register-and-immediate group to decodetree.
In the new decode, our asimd_imm_const() function returns a 64-bit value
rather than a 32-bit one, which means we don't need to treat cmode=14 op=1
as a special case in the decoder (it is the only encoding where the two
halves of the 64-bit value are different).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200522145520.6778-10-peter.maydell@linaro.org
Commit: 5a922419feb980592ef3dc16d74f0d9cf5ca4830
https://github.com/qemu/qemu/commit/5a922419feb980592ef3dc16d74f0d9cf5ca4830
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2020-06-05 (Fri, 05 Jun 2020)
Changed paths:
A docs/system/arm/aspeed.rst
M docs/system/target-arm.rst
M hw/adc/stm32f2xx_adc.c
M hw/arm/bcm2835_peripherals.c
M hw/arm/pxa2xx.c
M hw/input/pxa2xx_keypad.c
M hw/misc/Makefile.objs
A hw/misc/bcm2835_mphi.c
M hw/ssi/imx_spi.c
M hw/usb/Kconfig
M hw/usb/Makefile.objs
M hw/usb/dev-storage.c
A hw/usb/hcd-dwc2.c
A hw/usb/hcd-dwc2.h
M hw/usb/trace-events
M include/hw/arm/bcm2835_peripherals.h
A include/hw/misc/bcm2835_mphi.h
A include/hw/usb/dwc2-regs.h
M target/arm/crypto_helper.c
M target/arm/helper.h
M target/arm/neon-dp.decode
M target/arm/translate-a64.c
M target/arm/translate-a64.h
M target/arm/translate-neon.inc.c
M target/arm/translate.c
M target/arm/vec_helper.c
A target/arm/vec_internal.h
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200605'
into staging
target-arm queue:
hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly
hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask()
hw/arm/pxa2xx: Replace printf() call by qemu_log_mask()
target/arm: Convert crypto insns to gvec
hw/adc/stm32f2xx_adc: Correct memory region size and access size
tests/acceptance: Add a boot test for the xlnx-versal-virt machine
docs/system: Document Aspeed boards
raspi: Add model of the USB controller
target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree
# gpg: Signature made Fri 05 Jun 2020 17:48:39 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200605: (29 commits)
target/arm: Convert Neon one-register-and-immediate insns to decodetree
target/arm: Convert VCVT fixed-point ops to decodetree
target/arm: Convert Neon VSHLL, VMOVL to decodetree
target/arm: Convert Neon narrowing shifts with op==9 to decodetree
target/arm: Convert Neon narrowing shifts with op==8 to decodetree
target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree
target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to
decodetree
target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree
target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree
raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host
wire in the dwc-hsotg (dwc2) USB host controller emulation
usb: add short-packet handling to usb-storage driver
dwc-hsotg (dwc2) USB host controller emulation
dwc-hsotg (dwc2) USB host controller state definitions
dwc-hsotg (dwc2) USB host controller register definitions
raspi: add BCM2835 SOC MPHI emulation
docs/system: Document Aspeed boards
tests/acceptance: Add a boot test for the xlnx-versal-virt machine
hw/adc/stm32f2xx_adc: Correct memory region size and access size
target/arm: Split helper_crypto_sm3tt
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/175198ad91d8...5a922419feb9
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