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[Qemu-commits] [qemu/qemu] c888f7: target/arm: Use correct GDB XML for M

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] c888f7: target/arm: Use correct GDB XML for M-profile cores
Date: Thu, 14 May 2020 09:45:29 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: c888f7e0fdcc09c86004330ab5cad62bf98cc71c
      
https://github.com/qemu/qemu/commit/c888f7e0fdcc09c86004330ab5cad62bf98cc71c
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M configure
    A gdb-xml/arm-m-profile.xml
    M target/arm/cpu_tcg.c
    M target/arm/gdbstub.c

  Log Message:
  -----------
  target/arm: Use correct GDB XML for M-profile cores

GDB's remote protocol requires M-profile cores to use the feature
name 'org.gnu.gdb.arm.m-profile' instead of the 'org.gnu.gdb.arm.core'
feature used for A- and R-profile cores. We weren't doing this, which
meant GDB treated our M-profile cores like A-profile ones. This mostly
doesn't matter, but for instance means that it doesn't correctly
handle backtraces where an M-profile exception frame is involved.

Ship a copy of GDB's arm-m-profile.xml and use it on the M-profile
cores.  The integer registers have the same offsets as the
arm-core.xml, but register 25 is the M-profile XPSR rather than the
A-profile CPSR, so we need to update arm_cpu_gdb_read_register() and
arm_cpu_gdb_write_register() to handle XSPR reads and writes.

Fixes: https://bugs.launchpad.net/qemu/+bug/1877136
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 631e565450c483e0622eec3d8b61d7fa41d16bca
      
https://github.com/qemu/qemu/commit/631e565450c483e0622eec3d8b61d7fa41d16bca
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Create gen_gvec_[us]sra

The functions eliminate duplication of the special cases for
this operation.  They match up with the GVecGen2iFn typedef.

Add out-of-line helpers.  We got away with only having inline
expanders because the neon vector size is only 16 bytes, and
we know that the inline expansion will always succeed.
When we reuse this for SVE, tcg-gvec-op may decide to use an
out-of-line helper due to longer vector lengths.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6ccd48d4ea244c1c46a24dfa50bfb547f11422dd
      
https://github.com/qemu/qemu/commit/6ccd48d4ea244c1c46a24dfa50bfb547f11422dd
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Create gen_gvec_{u,s}{rshr,rsra}

Create vectorized versions of handle_shri_with_rndacc
for shift+round and shift+round+accumulate.  Add out-of-line
helpers in preparation for longer vector lengths from SVE.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 893ab0542aa385a287cbe46d5535c8b9e95ce699
      
https://github.com/qemu/qemu/commit/893ab0542aa385a287cbe46d5535c8b9e95ce699
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Create gen_gvec_{sri,sli}

The functions eliminate duplication of the special cases for
this operation.  They match up with the GVecGen2iFn typedef.

Add out-of-line helpers.  We got away with only having inline
expanders because the neon vector size is only 16 bytes, and
we know that the inline expansion will always succeed.
When we reuse this for SVE, tcg-gvec-op may decide to use an
out-of-line helper due to longer vector lengths.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2f27c5244db300387f15d9ffa5067a204ffd625d
      
https://github.com/qemu/qemu/commit/2f27c5244db300387f15d9ffa5067a204ffd625d
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Remove unnecessary range check for VSHL

In 1dc8425e551, while converting to gvec, I added an extra range check
against the shift count.  This was unnecessary because the encoding of
the shift count produces 0 to the element size - 1.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3f08f0bce841e7857ec98ce7909629d0c335005e
      
https://github.com/qemu/qemu/commit/3f08f0bce841e7857ec98ce7909629d0c335005e
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Tidy handle_vec_simd_shri

Now that we've converted all cases to gvec, there is quite a bit
of dead code at the end of the function.  Remove it.

Sink the call to gen_gvec_fn2i to the end, loading a function
pointer within the switch statement.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 69d5e2bf8c3cefedbfa1c1670137e636dbd7faa5
      
https://github.com/qemu/qemu/commit/69d5e2bf8c3cefedbfa1c1670137e636dbd7faa5
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Create gen_gvec_{ceq,clt,cle,cgt,cge}0

Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.

Macro-ize the 5 nearly identical comparisons.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 271063206a46062a45fc6bab8dabe45f0b88159d
      
https://github.com/qemu/qemu/commit/271063206a46062a45fc6bab8dabe45f0b88159d
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Create gen_gvec_{mla,mls}

Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e9eee5316ffec5f37643de806b2e5577c5c189cf
      
https://github.com/qemu/qemu/commit/e9eee5316ffec5f37643de806b2e5577c5c189cf
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c

  Log Message:
  -----------
  target/arm: Swap argument order for VSHL during decode

Rather than perform the argument swap during code generation,
perform it during decode.  This means it doesn't have to be
special cased later, and we can share code with aarch64 code
generation.  Hopefully the decode comment addresses any confusion
that might arise in between.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8161b75357095fef54c76b1a6ed1e54d0e8655e0
      
https://github.com/qemu/qemu/commit/8161b75357095fef54c76b1a6ed1e54d0e8655e0
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Create gen_gvec_{cmtst,ushl,sshl}

Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c7715b6b51a6f7a5412c5fcb40a4c8586105e597
      
https://github.com/qemu/qemu/commit/c7715b6b51a6f7a5412c5fcb40a4c8586105e597
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Create gen_gvec_{uqadd, sqadd, uqsub, sqsub}

Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fe6fb4beb2f9bb0afc813e565504b66a92bbf04b
      
https://github.com/qemu/qemu/commit/fe6fb4beb2f9bb0afc813e565504b66a92bbf04b
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Remove fp_status from helper_{recpe, rsqrte}_u32

These operations do not touch fp_status.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 146aa66ce58b686b8037d0eb3921c1125942dbde
      
https://github.com/qemu/qemu/commit/146aa66ce58b686b8037d0eb3921c1125942dbde
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Create gen_gvec_{qrdmla,qrdmls}

Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e286bf4a72fe3a60490b8d6e3f28d6335677e08c
      
https://github.com/qemu/qemu/commit/e286bf4a72fe3a60490b8d6e3f28d6335677e08c
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/translate.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Pass pointer to qc to qrdmla/qrdmls

Pass a pointer directly to env->vfp.qc[0], rather than env.
This will allow SVE2, which does not modify QC, to pass a
pointer to dummy storage.

Change the return type of inl_qrdml.h_s16 to match the
sense of the operation: signed.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 525d9b6d42844e187211d25b69be8b378785bc24
      
https://github.com/qemu/qemu/commit/525d9b6d42844e187211d25b69be8b378785bc24
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Clear tail in gvec_fmul_idx_*, gvec_fmla_idx_*

Must clear the tail for AdvSIMD when SVE is enabled.

Fixes: ca40a6e6e39
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 50c160d44eb059c7fc7f348ae2c3b0cb41437044
      
https://github.com/qemu/qemu/commit/50c160d44eb059c7fc7f348ae2c3b0cb41437044
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Vectorize SABD/UABD

Include 64-bit element size in preparation for SVE2.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cfdb2c0c95ae9205b0dd7f0f5e970cdec50fef20
      
https://github.com/qemu/qemu/commit/cfdb2c0c95ae9205b0dd7f0f5e970cdec50fef20
  Author: Richard Henderson <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Vectorize SABA/UABA

Include 64-bit element size in preparation for SVE2.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 143b040f4abfafcbb562252df9fb350192ae6160
      
https://github.com/qemu/qemu/commit/143b040f4abfafcbb562252df9fb350192ae6160
  Author: Patrick Williams <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Add support for the sonorapass-bmc board

Sonora Pass is a 2 socket x86 motherboard designed by Facebook
and supported by OpenBMC.  Strapping configuration was obtained
from hardware and i2c configuration is based on dts found at:

https://github.com/facebook/openbmc-linux/blob/1633c87b8ba7c162095787c988979b748ba65dc8/arch/arm/boot/dts/aspeed-bmc-facebook-sonorapass.dts

Booted a test image of http://github.com/facebook/openbmc to login
prompt.

Signed-off-by: Patrick Williams <address@hidden>
Reviewed-by: Amithash Prasad <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
[PMM: fixed block comment style nit]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1439f213074a8ebc30e6713ce1bf766407ddce46
      
https://github.com/qemu/qemu/commit/1439f213074a8ebc30e6713ce1bf766407ddce46
  Author: Dongjiu Geng <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M hw/acpi/nvdimm.c
    M include/qemu/uuid.h

  Log Message:
  -----------
  acpi: nvdimm: change NVDIMM_UUID_LE to a common macro

The little end UUID is used in many places, so make
NVDIMM_UUID_LE to a common macro to convert the UUID
to a little end array.

Reviewed-by: Xiang Zheng <address@hidden>
Signed-off-by: Dongjiu Geng <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2afa8c85192595e2b6a61e2045df7bea66bdea08
      
https://github.com/qemu/qemu/commit/2afa8c85192595e2b6a61e2045df7bea66bdea08
  Author: Dongjiu Geng <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M hw/arm/virt.c
    M include/hw/arm/virt.h

  Log Message:
  -----------
  hw/arm/virt: Introduce a RAS machine option

RAS Virtualization feature is not supported now, so
add a RAS machine option and disable it by default.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Dongjiu Geng <address@hidden>
Signed-off-by: Xiang Zheng <address@hidden>
Reviewed-by: Jonathan Cameron <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5fb004a2650dde16ac41b7ee801fc30961524821
      
https://github.com/qemu/qemu/commit/5fb004a2650dde16ac41b7ee801fc30961524821
  Author: Dongjiu Geng <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    A docs/specs/acpi_hest_ghes.rst
    M docs/specs/index.rst

  Log Message:
  -----------
  docs: APEI GHES generation and CPER record description

Add APEI/GHES detailed design document

Signed-off-by: Dongjiu Geng <address@hidden>
Signed-off-by: Xiang Zheng <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: aa16508f1d1bce2411fdbe82aa20e559bbd90e48
      
https://github.com/qemu/qemu/commit/aa16508f1d1bce2411fdbe82aa20e559bbd90e48
  Author: Dongjiu Geng <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/acpi/Kconfig
    M hw/acpi/Makefile.objs
    M hw/acpi/aml-build.c
    A hw/acpi/ghes.c
    M hw/arm/virt-acpi-build.c
    M include/hw/acpi/aml-build.h
    A include/hw/acpi/ghes.h

  Log Message:
  -----------
  ACPI: Build related register address fields via hardware error fw_cfg blob

This patch builds error_block_address and read_ack_register fields
in hardware errors table , the error_block_address points to Generic
Error Status Block(GESB) via bios_linker. The max size for one GESB
is 1kb, For more detailed information, please refer to
document: docs/specs/acpi_hest_ghes.rst

Now we only support one Error source, if necessary, we can extend to
support more.

Suggested-by: Laszlo Ersek <address@hidden>
Signed-off-by: Xiang Zheng <address@hidden>
Reviewed-by: Jonathan Cameron <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Signed-off-by: Dongjiu Geng <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 205cc75deec196bb3266a0dac407a195a646b5fc
      
https://github.com/qemu/qemu/commit/205cc75deec196bb3266a0dac407a195a646b5fc
  Author: Dongjiu Geng <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M hw/acpi/ghes.c
    M hw/arm/virt-acpi-build.c
    M include/hw/acpi/ghes.h

  Log Message:
  -----------
  ACPI: Build Hardware Error Source Table

This patch builds Hardware Error Source Table(HEST) via fw_cfg blobs.
Now it only supports ARMv8 SEA, a type of Generic Hardware Error
Source version 2(GHESv2) error source. Afterwards, we can extend
the supported types if needed. For the CPER section, currently it
is memory section because kernel mainly wants userspace to handle
the memory errors.

This patch follows the spec ACPI 6.2 to build the Hardware Error
Source table. For more detailed information, please refer to
document: docs/specs/acpi_hest_ghes.rst

build_ghes_hw_error_notification() helper will help to add Hardware
Error Notification to ACPI tables without using packed C structures
and avoid endianness issues as API doesn't need explicit conversion.

Signed-off-by: Xiang Zheng <address@hidden>
Signed-off-by: Dongjiu Geng <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a08a64627b6b5874f3dbf202fb08563e7a74b1ea
      
https://github.com/qemu/qemu/commit/a08a64627b6b5874f3dbf202fb08563e7a74b1ea
  Author: Dongjiu Geng <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M hw/acpi/generic_event_device.c
    M hw/acpi/ghes.c
    M hw/arm/virt-acpi-build.c
    M include/hw/acpi/generic_event_device.h
    M include/hw/acpi/ghes.h

  Log Message:
  -----------
  ACPI: Record the Generic Error Status Block address

Record the GHEB address via fw_cfg file, when recording
a error to CPER, it will use this address to find out
Generic Error Data Entries and write the error.

In order to avoid migration failure, make hardware
error table address to a part of GED device instead
of global variable, then this address will be migrated
to target QEMU.

Acked-by: Xiang Zheng <address@hidden>
Signed-off-by: Dongjiu Geng <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6b552b9bc8421c48e91c9a40ce5dccf78020c339
      
https://github.com/qemu/qemu/commit/6b552b9bc8421c48e91c9a40ce5dccf78020c339
  Author: Dongjiu Geng <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M accel/kvm/kvm-all.c
    M include/sysemu/kvm_int.h
    M target/i386/kvm.c

  Log Message:
  -----------
  KVM: Move hwpoison page related functions into kvm-all.c

kvm_hwpoison_page_add() and kvm_unpoison_all() will both
be used by X86 and ARM platforms, so moving them into
"accel/kvm/kvm-all.c" to avoid duplicate code.

For architectures that don't use the poison-list functionality
the reset handler will harmlessly do nothing, so let's register
the kvm_unpoison_all() function in the generic kvm_init() function.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Dongjiu Geng <address@hidden>
Signed-off-by: Xiang Zheng <address@hidden>
Acked-by: Xiang Zheng <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 558b9d86407d56e13d8a2cd61cdecf0359e7804a
      
https://github.com/qemu/qemu/commit/558b9d86407d56e13d8a2cd61cdecf0359e7804a
  Author: Dongjiu Geng <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M hw/acpi/ghes.c
    M include/hw/acpi/ghes.h

  Log Message:
  -----------
  ACPI: Record Generic Error Status Block(GESB) table

kvm_arch_on_sigbus_vcpu() error injection uses source_id as
index in etc/hardware_errors to find out Error Status Data
Block entry corresponding to error source. So supported source_id
values should be assigned here and not be changed afterwards to
make sure that guest will write error into expected Error Status
Data Block.

Before QEMU writes a new error to ACPI table, it will check whether
previous error has been acknowledged. If not acknowledged, the new
errors will be ignored and not be recorded. For the errors section
type, QEMU simulate it to memory section error.

Signed-off-by: Dongjiu Geng <address@hidden>
Signed-off-by: Xiang Zheng <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e24fd076a59604c4ba3c05fe9d19ea6fc5320a12
      
https://github.com/qemu/qemu/commit/e24fd076a59604c4ba3c05fe9d19ea6fc5320a12
  Author: Dongjiu Geng <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M include/sysemu/kvm.h
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/kvm64.c
    M target/arm/tlb_helper.c
    M target/i386/cpu.h

  Log Message:
  -----------
  target-arm: kvm64: handle SIGBUS signal from kernel or KVM

Add a SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translates the host VA delivered by host to guest PA, then fills this PA
to guest APEI GHES memory, then notifies guest according to the SIGBUS
type.

When guest accesses the poisoned memory, it will generate a Synchronous
External Abort(SEA). Then host kernel gets an APEI notification and calls
memory_failure() to unmapped the affected page in stage 2, finally
returns to guest.

Guest continues to access the PG_hwpoison page, it will trap to KVM as
stage2 fault, then a SIGBUS_MCEERR_AR synchronous signal is delivered to
Qemu, Qemu records this error address into guest APEI GHES memory and
notifes guest using Synchronous-External-Abort(SEA).

In order to inject a vSEA, we introduce the kvm_inject_arm_sea() function
in which we can setup the type of exception and the syndrome information.
When switching to guest, the target vcpu will jump to the synchronous
external abort vector table entry.

The ESR_ELx.DFSC is set to synchronous external abort(0x10), and the
ESR_ELx.FnV is set to not valid(0x1), which will tell guest that FAR is
not valid and hold an UNKNOWN value. These values will be set to KVM
register structures through KVM_SET_ONE_REG IOCTL.

Signed-off-by: Dongjiu Geng <address@hidden>
Signed-off-by: Xiang Zheng <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Acked-by: Xiang Zheng <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f7e462f82b06d39acefff7b8f153bf5e6b3d28e5
      
https://github.com/qemu/qemu/commit/f7e462f82b06d39acefff7b8f153bf5e6b3d28e5
  Author: Dongjiu Geng <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add ACPI/HEST/GHES entries

I and Xiang are willing to review the APEI-related patches and
volunteer as the reviewers for the HEST/GHES part.

Signed-off-by: Dongjiu Geng <address@hidden>
Signed-off-by: Xiang Zheng <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a063569508af8295cf6271e06700e5b956bb402d
      
https://github.com/qemu/qemu/commit/a063569508af8295cf6271e06700e5b956bb402d
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-same VQRDMLAH/VQRDMLSH to decodetree

Convert the Neon VQRDMLAH and VQRDMLSH insns in the 3-reg-same group
to decodetree.  These don't use do_3same() because they want to
operate on VFP double registers, whose offsets are different from the
neon_reg_offset() calculations do_3same does.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 21290edfc29d8929741c0ed043733c23c69bc3b9
      
https://github.com/qemu/qemu/commit/21290edfc29d8929741c0ed043733c23c69bc3b9
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-same SHA to decodetree

Convert the Neon SHA instructions in the 3-reg-same group
to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 35d4352fa9e94b35bf17f58181cb16c184b98d56
      
https://github.com/qemu/qemu/commit/35d4352fa9e94b35bf17f58181cb16c184b98d56
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 64-bit element 3-reg-same insns

Convert the 64-bit element insns in the 3-reg-same group
to decodetree. This covers VQSHL, VRSHL and VQRSHL where
size==0b11.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: cb294bca866f1cd776e44e03e5e432942bc676e8
      
https://github.com/qemu/qemu/commit/cb294bca866f1cd776e44e03e5e432942bc676e8
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VHADD 3-reg-same insns

Convert the Neon VHADD insns in the 3-reg-same group to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 7715098f93ff5205334edf161e5fe156346122b0
      
https://github.com/qemu/qemu/commit/7715098f93ff5205334edf161e5fe156346122b0
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VABA/VABD 3-reg-same to decodetree

Convert the Neon VABA and VABD insns in the 3-reg-same group to
decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 8e44d03f4b5590e19a4f7910ca1c327609933dd7
      
https://github.com/qemu/qemu/commit/8e44d03f4b5590e19a4f7910ca1c327609933dd7
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VRHADD, VHSUB 3-reg-same insns to decodetree

Convert the Neon VRHADD and VHSUB 3-reg-same insns to decodetree.
(These are all the other insns in 3-reg-same which were using
GEN_NEON_INTEGER_OP() and which are not pairwise or
reversed-operands.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 6812dfdc6b0286730d6f903ebfbdc4f81b80c29b
      
https://github.com/qemu/qemu/commit/6812dfdc6b0286730d6f903ebfbdc4f81b80c29b
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VQSHL, VRSHL, VQRSHL 3-reg-same insns to decodetree

Convert the VQSHL, VRSHL and VQRSHL insns in the 3-reg-same
group to decodetree. We have already implemented the size==0b11
case of these insns; this commit handles the remaining sizes.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 059c2398a2b1ae86c6722c45e79fb0d0f4d95b1d
      
https://github.com/qemu/qemu/commit/059c2398a2b1ae86c6722c45e79fb0d0f4d95b1d
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VPMAX/VPMIN 3-reg-same insns to decodetree

Convert the Neon integer VPMAX and VPMIN 3-reg-same insns to
decodetree. These are 'pairwise' operations.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: fa22827d4eb078b6c58cd3d19af0b50ed951e832
      
https://github.com/qemu/qemu/commit/fa22827d4eb078b6c58cd3d19af0b50ed951e832
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VPADD 3-reg-same insns to decodetree

Convert the Neon integer VPADD 3-reg-same insns to decodetree.  These
are 'pairwise' operations.  (Note that VQRDMLAH, which shares the
same primary opcode but has U=1, has already been converted.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 7ecc28bc72b8033cf4e0c6332135ec20d4125dfb
      
https://github.com/qemu/qemu/commit/7ecc28bc72b8033cf4e0c6332135ec20d4125dfb
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VQDMULH/VQRDMULH 3-reg-same to decodetree

Convert the Neon VQDMULH and VQRDMULH 3-reg-same insns to
decodetree. These are the last integer operations in the
3-reg-same group.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: a26a352bb498662cd0c205cb433a352f86fac7d2
      
https://github.com/qemu/qemu/commit/a26a352bb498662cd0c205cb433a352f86fac7d2
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon-dp.decode
    M target/arm/neon_helper.c
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree

Convert the Neon VADD, VSUB, VABD 3-reg-same insns to decodetree.
We already have gvec helpers for addition and subtraction, but must
add one for fabd.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: ab978335a56e3618212868fdce3a54217c6e71e6
      
https://github.com/qemu/qemu/commit/ab978335a56e3618212868fdce3a54217c6e71e6
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon VPMIN/VPMAX/VPADD float 3-reg-same insns to 
decodetree

Convert the Neon float VPMIN, VPMAX and VPADD 3-reg-same insns to
decodetree. These are the only remaining 'pairwise' operations,
so we can delete the pairwise-specific bits of the old decoder's
for-each-element loop now.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 8aa71ead912ca0a9c0d29b74e0976f91952f950a
      
https://github.com/qemu/qemu/commit/8aa71ead912ca0a9c0d29b74e0976f91952f950a
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon fp VMUL, VMLA, VMLS 3-reg-same insns to decodetree

Convert the Neon integer VMUL, VMLA, and VMLS 3-reg-same inssn to
decodetree.

We don't have a gvec helper for multiply-accumulate, so VMLA and VMLS
need a loop function do_3same_fp().  This takes a reads_vd parameter
to do_3same_fp() which tells it to load the old value into vd before
calling the callback function, in the same way that the do_vfp_3op_sp()
and do_vfp_3op_dp() functions in translate-vfp.inc.c work. (The
only uses in this patch pass reads_vd == true, but later commits
will use reads_vd == false.)

This conversion fixes in passing an underdecoding for VMUL
(originally reported by Fredrik Strupe <address@hidden>): bit 1
of the 'size' field must be 0.  The old decoder didn't enforce this,
but the decodetree pattern does.

The gen_VMLA_fp_reg() function performs the addition operation
with the operands in the opposite order to the old decoder:
since Neon sets 'default NaN mode' float32_add operations are
commutative so there is no behaviour difference, but putting
them this way around matches the Arm ARM pseudocode and the
required operation order for the subtraction in gen_VMLS_fp_reg().

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 727ff1d63213e6666e511956903b9e97a339ec7e
      
https://github.com/qemu/qemu/commit/727ff1d63213e6666e511956903b9e97a339ec7e
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon 3-reg-same compare insns to decodetree

Convert the Neon integer 3-reg-same compare insns VCGE, VCGT,
VCEQ, VACGE and VACGT to decodetree.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 26c6f695cfd2a3ccddb4d015a25b56f56aa62928
      
https://github.com/qemu/qemu/commit/26c6f695cfd2a3ccddb4d015a25b56f56aa62928
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate.c
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Move 'env' argument of recps_f32 and rsqrts_f32 helpers to usual 
place

The usual location for the env argument in the argument list of a TCG helper
is immediately after the return-value argument. recps_f32 and rsqrts_f32
differ in that they put it at the end.

Move the env argument to its usual place; this will allow us to
more easily use these helper functions with the gvec APIs.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: d5fdf9e9e1c6f2bbb0a4bcaafd85d344cce9c298
      
https://github.com/qemu/qemu/commit/d5fdf9e9e1c6f2bbb0a4bcaafd85d344cce9c298
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS to 
decodetree

Convert the Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS 3-reg-same
insns to decodetree. (These are all the remaining non-accumulation
instructions in this group.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: e95485f85657be21135c17a9226e297c21e73360
      
https://github.com/qemu/qemu/commit/e95485f85657be21135c17a9226e297c21e73360
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M target/arm/neon-dp.decode
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert NEON VFMA, VFMS 3-reg-same insns to decodetree

Convert the Neon floating point VFMA and VFMS insn to decodetree.
These are the last insns in the 3-reg-same group so we can
remove all the support/loop code from the old decoder.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 013a18edbbc59cdad019100c7d03c0494642b74c
      
https://github.com/qemu/qemu/commit/013a18edbbc59cdad019100c7d03c0494642b74c
  Author: Peter Maydell <address@hidden>
  Date:   2020-05-14 (Thu, 14 May 2020)

  Changed paths:
    M MAINTAINERS
    M accel/kvm/kvm-all.c
    M configure
    M default-configs/arm-softmmu.mak
    A docs/specs/acpi_hest_ghes.rst
    M docs/specs/index.rst
    A gdb-xml/arm-m-profile.xml
    M hw/acpi/Kconfig
    M hw/acpi/Makefile.objs
    M hw/acpi/aml-build.c
    M hw/acpi/generic_event_device.c
    A hw/acpi/ghes.c
    M hw/acpi/nvdimm.c
    M hw/arm/aspeed.c
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M include/hw/acpi/aml-build.h
    M include/hw/acpi/generic_event_device.h
    A include/hw/acpi/ghes.h
    M include/hw/arm/virt.h
    M include/qemu/uuid.h
    M include/sysemu/kvm.h
    M include/sysemu/kvm_int.h
    M target/arm/cpu.h
    M target/arm/cpu_tcg.c
    M target/arm/gdbstub.c
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/internals.h
    M target/arm/kvm64.c
    M target/arm/neon-dp.decode
    M target/arm/neon_helper.c
    M target/arm/tlb_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-neon.inc.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vec_helper.c
    M target/arm/vfp_helper.c
    M target/i386/cpu.h
    M target/i386/kvm.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200514' 
into staging

target-arm queue:
 * target/arm: Use correct GDB XML for M-profile cores
 * target/arm: Code cleanup to use gvec APIs better
 * aspeed: Add support for the sonorapass-bmc board
 * target/arm: Support reporting KVM host memory errors
   to the guest via ACPI notifications
 * target/arm: Finish conversion of Neon 3-reg-same insns to decodetree

# gpg: Signature made Thu 14 May 2020 15:19:15 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200514: (45 commits)
  target/arm: Convert NEON VFMA, VFMS 3-reg-same insns to decodetree
  target/arm: Convert Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS to 
decodetree
  target/arm: Move 'env' argument of recps_f32 and rsqrts_f32 helpers to usual 
place
  target/arm: Convert Neon 3-reg-same compare insns to decodetree
  target/arm: Convert Neon fp VMUL, VMLA, VMLS 3-reg-same insns to decodetree
  target/arm: Convert Neon VPMIN/VPMAX/VPADD float 3-reg-same insns to 
decodetree
  target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree
  target/arm: Convert Neon VQDMULH/VQRDMULH 3-reg-same to decodetree
  target/arm: Convert Neon VPADD 3-reg-same insns to decodetree
  target/arm: Convert Neon VPMAX/VPMIN 3-reg-same insns to decodetree
  target/arm: Convert Neon VQSHL, VRSHL, VQRSHL 3-reg-same insns to decodetree
  target/arm: Convert Neon VRHADD, VHSUB 3-reg-same insns to decodetree
  target/arm: Convert Neon VABA/VABD 3-reg-same to decodetree
  target/arm: Convert Neon VHADD 3-reg-same insns
  target/arm: Convert Neon 64-bit element 3-reg-same insns
  target/arm: Convert Neon 3-reg-same SHA to decodetree
  target/arm: Convert Neon 3-reg-same VQRDMLAH/VQRDMLSH to decodetree
  MAINTAINERS: Add ACPI/HEST/GHES entries
  target-arm: kvm64: handle SIGBUS signal from kernel or KVM
  ACPI: Record Generic Error Status Block(GESB) table
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/0ffd3d64bd1b...013a18edbbc5
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