[Qemu-commits] [qemu/qemu] 523e34: riscv/sifive_u: Fix up file ordering

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 523e34646788d877d16b422f43f23911eb0ea7cd
      
https://github.com/qemu/qemu/commit/523e34646788d877d16b422f43f23911eb0ea7cd
  Author: Alistair Francis <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv/sifive_u: Fix up file ordering

Split the file into clear machine and SoC sections.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>


  Commit: fda5b000faf401cf595c4e87809eac3378ddbfd4
      
https://github.com/qemu/qemu/commit/fda5b000faf401cf595c4e87809eac3378ddbfd4
  Author: Alistair Francis <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv/sifive_u: Add a serial property to the sifive_u SoC

At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.

A new "serial" property is introduced to the sifive_u SoC to specify
the board serial number. When not given, the default serial number
1 is used.

Suggested-by: Bin Meng <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>


  Commit: 3ca109c3f8d6225efdfa801252d25f3e526b004a
      
https://github.com/qemu/qemu/commit/3ca109c3f8d6225efdfa801252d25f3e526b004a
  Author: Bin Meng <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv/sifive_u: Add a serial property to the sifive_u machine

At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.

A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-Id: <address@hidden>
[ Changed by AF:
 - Use the SoC's serial property to pass the info to the SoC
 - Fixup commit title
 - Rebase on file restructuring
]
Signed-off-by: Alistair Francis <address@hidden>


  Commit: 384728905441279e54fa3d714b11bf1b1bcbfd27
      
https://github.com/qemu/qemu/commit/384728905441279e54fa3d714b11bf1b1bcbfd27
  Author: Alistair Francis <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  riscv: Don't use stage-2 PTE lookup protection flags

When doing the fist of a two stage lookup (Hypervisor extensions) don't
set the current protection flags from the second stage lookup of the
base address PTE.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Anup Patel <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>


  Commit: 8f67cd6db7375f9133d900b13b300931fbc2e1d8
      
https://github.com/qemu/qemu/commit/8f67cd6db7375f9133d900b13b300931fbc2e1d8
  Author: Alistair Francis <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  riscv: AND stage-1 and stage-2 protection flags

Take the result of stage-1 and stage-2 page table walks and AND the two
protection flags together. This way we require both to set permissions
instead of just stage-2.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Anup Patel <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>


  Commit: ee79e7cd47ef47074d7c20c221321c5d31d3683d
      
https://github.com/qemu/qemu/commit/ee79e7cd47ef47074d7c20c221321c5d31d3683d
  Author: Anup Patel <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  riscv: Fix Stage2 SV32 page table walk

As-per RISC-V H-Extension v0.5 draft, the Stage2 SV32 page table has
12bits of VPN[1] and 10bits of VPN[0]. The additional 2bits in VPN[1]
is required to handle the 34bit intermediate physical address coming
from Stage1 SV32 page table. The 12bits of VPN[1] implies that Stage2
SV32 level-0 page table will be 16KB in size with total 4096 enteries
where each entry maps 4MB of memory (same as Stage1 SV32 page table).

The get_physical_address() function is broken for Stage2 SV32 level-0
page table because it incorrectly computes output physical address for
Stage2 SV32 level-0 page table entry.

The root cause of the issue is that get_physical_address() uses the
"widened" variable to compute level-0 physical address mapping which
changes level-0 mapping size (instead of 4MB). We should use the
"widened" variable only for computing index of Stage2 SV32 level-0
page table.

Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>


  Commit: e883e9927ae667a2473c4a4ec666df53af1b34d9
      
https://github.com/qemu/qemu/commit/e883e9927ae667a2473c4a4ec666df53af1b34d9
  Author: Bin Meng <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: Generate correct "mmu-type" for 32-bit machines

32-bit machine should have its CPU's "mmu-type" set to "riscv,sv32".

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>


  Commit: 74dbba9b734b3509dc3682715187339a91fcd3fb
      
https://github.com/qemu/qemu/commit/74dbba9b734b3509dc3682715187339a91fcd3fb
  Author: Corey Wharton <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M hw/riscv/sifive_e.c

  Log Message:
  -----------
  riscv: sifive_e: Support changing CPU type

Allows the CPU to be changed from the default via the -cpu command
line option.

Signed-off-by: Corey Wharton <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
[ Changes by AF:
 - Set "cpu-type" from the machine and not SoC
]
Signed-off-by: Alistair Francis <address@hidden>


  Commit: d784733bf1875c1ba355c69739518f24d56f1260
      
https://github.com/qemu/qemu/commit/d784733bf1875c1ba355c69739518f24d56f1260
  Author: Corey Wharton <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add a sifive-e34 cpu type

The sifive-e34 cpu type is the same as the sifive-e31 with the
single precision floating-point extension enabled.

Signed-off-by: Corey Wharton <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>


  Commit: 64ce00a6c7c00c0b120270e1644009e5d521e277
      
https://github.com/qemu/qemu/commit/64ce00a6c7c00c0b120270e1644009e5d521e277
  Author: LIU Zhiwei <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M linux-user/riscv/signal.c

  Log Message:
  -----------
  linux-user/riscv: fix up struct target_ucontext definition

As struct target_ucontext will be transfered to signal handler, it
must keep pace with struct ucontext_t defined in Linux kernel.

Signed-off-by: LIU Zhiwei <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>


  Commit: 0b2f78e524d70d40200fa1f9334b2a6db7ca10e4
      
https://github.com/qemu/qemu/commit/0b2f78e524d70d40200fa1f9334b2a6db7ca10e4
  Author: Bin Meng <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
    M pc-bios/opensbi-riscv32-virt-fw_jump.bin
    M pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
    M pc-bios/opensbi-riscv64-virt-fw_jump.bin
    M roms/opensbi

  Log Message:
  -----------
  roms: opensbi: Upgrade from v0.6 to v0.7

Upgrade OpenSBI from v0.6 to v0.7 and the pre-built bios images.

The v0.7 release includes the following commits:

f64f4b9 lib: Add a new platform feature to bringup secondary harts
b677a9b lib: Implement hart hotplug
5b48240 lib: Add possible hart status values
e3f69fc lib: Implement Hart State Management (HSM) SBI extension
6704216 lib: Check MSIP bit after returning from WFI
82ae8e8 makefile: Do setup of the install target more flexible
e1a5b73 platform: sifive: fu540: allow sv32 as an mmu-type
8c83fb2 lib: Fix return type of sbi_hsm_hart_started()
00d332b include: Move bits related defines and macros to sbi_bitops.h
a148996 include: sbi_bitops: More useful bit operations
4a603eb platform: kendryte/k210: Set per-HART stack size to 8KB
678c3c3 include: sbi_scratch: Set per-HART scratch size to 4KB
2abc55b lib: Sort build objects in alphabetical order
6e87507 platform: ae350: Sort build objects in alphabetical order
650c0e5 lib: sbi: Fix coding style issues
078686d lib: serial: Fix coding style issues
3226bd9 lib: Simple bitmap library
c741abc include: Simple hartmask library
d6d7e18 lib: sbi_init: Don't allow HARTID greater than SBI_HARTMASK_MAX_BITS
a4a6a81 lib: Introduce SBI_TLB_INFO_INIT() helper macro
d963164 lib: sbi_tlb: Use sbi_hartmask in sbi_tlb_info
71d2b83 lib: Move all coldboot wait APIs to sbi_init.c
2b945fc lib: sbi_init: Use hartmask for coldboot wait
44ce5b9 include: Remove disabled_hart_mask from sbi_platform
2db381f lib: Introduce sbi_hsm_hart_started_mask() API
61f7768 lib: sbi_ecall_legacy: Use sbi_hsm_hart_started_mask() API
466fecb lib: sbi_system: Use sbi_hsm_hart_started_mask() API
9aad831 lib: sbi_ipi: Use sbi_hsm_hart_started_mask() API
eede1aa lib: sbi_hart: Remove HART available mask and related APIs
757bb44 docs: Remove out-of-date documentation
86d37bb lib: sbi: Fix misaligned trap handling
ffdc858 platform: ariane-fpga: Change license for ariane-fpga from GPL-2.0 to 
BSD-2
4b2f594 sbi: Add definitions for true/false
0cfe49a libfdt: Add INT32_MAX and UINT32_MAX in libfdt_env.h
baac7e0 libfdt: Upgrade to v1.5.1 release
f92147c include: Make sbi_hart_id_to_scratch() as macro
eeae3d9 firmware: fw_base: Optimize _hartid_to_scratch() implementation
16e7071 lib: sbi_hsm: Optimize sbi_hsm_hart_get_state() implementation
823345e include: Make sbi_current_hartid() as macro in riscv_asm.h
9aabba2 Makefile: Fix distclean make target
9275ed3 platform: ariane-fpga: Set per-HART stack size to 8KB
2343efd platform: Set per-HART stack size to 8KB in the template platform codes
72a0628 platform: Use one unified per-HART stack size macro for all platforms
327ba36 scripts: Cover sifive/fu540 in the 32-bit build
5fbcd62 lib: sbi: Update pmp_get() to return decoded size directly
dce8846 libfdt: Compile fdt_addresses.c
fcb1ded lib: utils: Add a fdt_reserved_memory_fixup() helper
666be6d platform: Clean up include header files
6af5576 lib: utils: Move PLIC DT fix up codes to fdt_helper.c
e846ce1 platform: andes/ae350: Fix up DT for reserved memory
8135520 platform: ariane-fpga: Fix up DT for reserved memory
c9a5268 platform: qemu/virt: Fix up DT for reserved memory
6f9bb83 platform: sifive/fu540: Fix up DT for reserved memory
1071f05 platform: sifive/fu540: Remove "stdout-path" fix-up
dd9439f lib: utils: Add a fdt_cpu_fixup() helper
3f1c847 platform: sifive/fu540: Replace cpu0 node fix-up with the new helper
db6a2b5 lib: utils: Add a general device tree fix-up helper
3f8d754 platform: Update to call general DT fix-up helper
87a7ef7 lib: sbi_scratch: Introduce HART id to scratch table
e23d3ba include: Simplify HART id to scratch macro
19bd531 lib: sbi_hsm: Simplify hart_get_state() and hart_started() APIs
3ebfe0e lib: sbi_tlb: Simplify sbi_tlb_entry_process() function
209134d lib: Handle failure of sbi_hartid_to_scratch() API
bd6ef02 include: sbi_platform: Improve sbi_platform_hart_disabled() API
c9f60fc lib: sbi_scratch: Don't set hartid_to_scratch table for disabled HART
680b098 lib: sbi_hsm: Don't use sbi_platform_hart_count() API
db187d6 lib: sbi_hsm: Remove scratch parameter from hart_started_mask() API
814f38d lib: sbi_hsm: Don't use sbi_platform_hart_disabled() API
75eec9d lib: Don't use sbi_platform_hart_count() API
c51f02c include: sbi_platform: Introduce HART index to HART id table
315a877 platform: sifive/fu540: Remove FU540_ENABLED_HART_MASK option
a0c88dd lib: Fix sbi_ecall_register_extension to prevent extension IDs overlap
9a74a64 lib: Check MSIP bit after returning from WFI
5968894 platform: Move ariane standalone fpga project to its own project
ed265b4 platform: fpga/ariane: Remove redundant plic address macros
fb84879 platform: Add OpenPiton platform support
d1d6560 platform: fpga/common: Add a fdt parsing helper functions
040e4e2 lib: utils: Move fdt fixup helper routines to a different file
4c37451 platform: openpiton: Read the device configurations from device tree
4d93586 lib: prevent coldboot_lottery from overflowing
550ba88 scripts: Extend create-binary-archive.sh for unified binary tar ball
160c885 lib: utils: Improve fdt_cpu_fixup() implementation
1de66d1 lib: Optimize unpriv load/store implementation
626467c lib: Remove scratch parameter from unpriv load/store functions
cb78a48 lib: sbi_trap: Remove scratch parameter from sbi_trap_redirect()
d11c79c lib: sbi_emulate_csr: Remove scratch and hartid parameter
5a7bd0c lib: sbi_illegal_insn: Remove mcause, scratch and hartid parameters
fe37d7d lib: sbi_misaligned_ldst: Remove mcause, scratch and hartid parameters
7487116 lib: sbi_ecall: Remove mcause, scratch and hartid parameters
40b221b lib: sbi_trap: Simplify sbi_trap_handler() API
7b211ff include: sbi_platform: Remove priv parameter from hart_start() callback
5b6957e include: Use more consistent name for atomic xchg() and cmpxchg()
dd0f21c lib: sbi_scratch: Introduce sbi_scratch_last_hartid() API
54b2779 include: sbi_tlb: Remove scratch parameter from sbi_tlb_request()
9e52a45 include: sbi_ipi: Remove scratch parameter from most functions
ec0d80f include: sbi_system: Remove scratch parameter and redundant functions
0a28ea5 include: sbi_timer: Remove scratch parameter from most funcitons
648507a include: sbi_console: Remove scratch parameter from sbi_dprintf()
e5a7f55 platform: thead/c910: Use HSM extension to boot secondary cores
f281de8 lib: irqchip/plic: Fix maximum priority threshold value
6c7922e lib: Support vector extension
615587c docs: Update README about supported SBI versions
66d0184 lib: Allow overriding SBI implementation ID
9f1b72c include: Bump-up version to 0.7

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>


  Commit: 02777ac3036187077c98a05843d888b4be8c51b3
      
https://github.com/qemu/qemu/commit/02777ac3036187077c98a05843d888b4be8c51b3
  Author: Anup Patel <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()

This patch adds an optional function pointer, "sym_cb", to
riscv_load_firmware() which provides the possibility to access
the symbol table during kernel loading.

The pointer is ignored, if supplied with flat (non-elf) firmware image.

The Spike board requires it locate the HTIF symbols from firmware ELF
passed via "-bios" option.

Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>


  Commit: 5b8a986350a9ee2d9d95a76c29017c3c603bb350
      
https://github.com/qemu/qemu/commit/5b8a986350a9ee2d9d95a76c29017c3c603bb350
  Author: Anup Patel <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M hw/riscv/spike.c

  Log Message:
  -----------
  hw/riscv/spike: Allow loading firmware separately using -bios option

This patch extends Spike machine support to allow loading OpenSBI
firmware (fw_jump.elf) separately using -bios option.

Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>


  Commit: 31e6d70485b1a719ca27e9a2d21f2a61ac497cdf
      
https://github.com/qemu/qemu/commit/31e6d70485b1a719ca27e9a2d21f2a61ac497cdf
  Author: Anup Patel <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M hw/riscv/spike.c

  Log Message:
  -----------
  hw/riscv/spike: Allow more than one CPUs

Currently, the upstream Spike ISA simulator allows more than
one CPUs so we update QEMU Spike machine on similar lines to
allow more than one CPUs.

The maximum number of CPUs for QEMU Spike machine is kept
same as QEMU Virt machine.

Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>


  Commit: 157360331ab3a423e2481b62c60d5399bf2957bd
      
https://github.com/qemu/qemu/commit/157360331ab3a423e2481b62c60d5399bf2957bd
  Author: Peter Maydell <address@hidden>
  Date:   2020-04-29 (Wed, 29 Apr 2020)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h
    M include/hw/riscv/sifive_u.h
    M linux-user/riscv/signal.c
    M pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
    M pc-bios/opensbi-riscv32-virt-fw_jump.bin
    M pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
    M pc-bios/opensbi-riscv64-virt-fw_jump.bin
    M roms/opensbi
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20200429-2' into staging

RISC-V pull request for 5.1

This is the first pull request for the 5.1 development period. It
contains all of the patches that were sent during the 5.0 timeframe.

This is an assortment of fixes for RISC-V, including fixes for the
Hypervisor extension, the Spike machine and an update to OpenSBI.

# gpg: Signature made Wed 29 Apr 2020 21:17:17 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <address@hidden>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200429-2:
  hw/riscv/spike: Allow more than one CPUs
  hw/riscv/spike: Allow loading firmware separately using -bios option
  hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
  roms: opensbi: Upgrade from v0.6 to v0.7
  linux-user/riscv: fix up struct target_ucontext definition
  target/riscv: Add a sifive-e34 cpu type
  riscv: sifive_e: Support changing CPU type
  hw/riscv: Generate correct "mmu-type" for 32-bit machines
  riscv: Fix Stage2 SV32 page table walk
  riscv: AND stage-1 and stage-2 protection flags
  riscv: Don't use stage-2 PTE lookup protection flags
  riscv/sifive_u: Add a serial property to the sifive_u machine
  riscv/sifive_u: Add a serial property to the sifive_u SoC
  riscv/sifive_u: Fix up file ordering

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/648db19685b7...157360331ab3