[Qemu-commits] [qemu/qemu] 7568b2: hw/386: Add EPYC mode topology decoding functions

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 7568b205555a6405042f62c64af3268f4330aed5
      
https://github.com/qemu/qemu/commit/7568b205555a6405042f62c64af3268f4330aed5
  Author: Babu Moger <address@hidden>
  Date:   2020-03-31 (Tue, 31 Mar 2020)

  Changed paths:
    M include/hw/i386/topology.h

  Log Message:
  -----------
  hw/386: Add EPYC mode topology decoding functions

These functions add support for building EPYC mode topology given the smp
details like numa nodes, cores, threads and sockets.

The new apic id decoding is mostly similar to current apic id decoding
except that it adds a new field node_id when numa configured. Removes all
the hardcoded values. Subsequent patches will use these functions to build
the topology.

Following functions are added.
apicid_llc_width_epyc
apicid_llc_offset_epyc
apicid_pkg_offset_epyc
apicid_from_topo_ids_epyc
x86_topo_ids_from_idx_epyc
x86_topo_ids_from_apicid_epyc
x86_apicid_from_cpu_idx_epyc

The topology details are available in Processor Programming Reference (PPR)
for AMD Family 17h Model 01h, Revision B1 Processors. The revision guides are
available from the bugzilla Link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537

Signed-off-by: Babu Moger <address@hidden>
Acked-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: dd08ef0318e2b61d14bc069590d174913f7f437a
      
https://github.com/qemu/qemu/commit/dd08ef0318e2b61d14bc069590d174913f7f437a
  Author: Babu Moger <address@hidden>
  Date:   2020-03-31 (Tue, 31 Mar 2020)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  target/i386: Cleanup and use the EPYC mode topology functions

Use the new functions from topology.h and delete the unused code. Given the
sockets, nodes, cores and threads, the new functions generate apic id for EPYC
mode. Removes all the hardcoded values.

Signed-off-by: Babu Moger <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Acked-by: Igor Mammedov <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 6121c7fbfd98dbc3af1b00b56ff2eef66df87828
      
https://github.com/qemu/qemu/commit/6121c7fbfd98dbc3af1b00b56ff2eef66df87828
  Author: Babu Moger <address@hidden>
  Date:   2020-03-31 (Tue, 31 Mar 2020)

  Changed paths:
    M hw/i386/x86.c
    M include/hw/i386/x86.h

  Log Message:
  -----------
  hw/i386: Introduce apicid functions inside X86MachineState

Introduce model specific apicid functions inside X86MachineState.
These functions will be loaded from X86CPUDefinition.

Signed-off-by: Babu Moger <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 0c1538cb1a26287c072645f4759b9872b1596d79
      
https://github.com/qemu/qemu/commit/0c1538cb1a26287c072645f4759b9872b1596d79
  Author: Babu Moger <address@hidden>
  Date:   2020-03-31 (Tue, 31 Mar 2020)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition

Add a boolean variable use_epyc_apic_id_encoding in X86CPUDefinition.
This will be set if this cpu model needs to use new EPYC based
apic id encoding.

Override the handlers with EPYC based handlers if use_epyc_apic_id_encoding
is set. This will be done in x86_cpus_init.

Signed-off-by: Babu Moger <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 2e26f4ab3bf8390a2677d3afd9b1a04f015d7721
      
https://github.com/qemu/qemu/commit/2e26f4ab3bf8390a2677d3afd9b1a04f015d7721
  Author: Babu Moger <address@hidden>
  Date:   2020-03-31 (Tue, 31 Mar 2020)

  Changed paths:
    M hw/i386/pc.c
    M hw/i386/x86.c

  Log Message:
  -----------
  hw/i386: Move arch_id decode inside x86_cpus_init

Apicid calculation depends on knowing the total number of numa nodes
for EPYC cpu models. Right now, we are calculating the arch_id while
parsing the numa(parse_numa). At this time, it is not known how many
total numa nodes are configured in the system.

Move the arch_id calculation inside x86_cpus_init. At this time, smp
parse is already completed and numa node information is available.

Override the handlers if use_epyc_apic_id_encoding is enabled in
cpu model definition.

Also replace the calling convention to use handlers from
X86MachineState.

Signed-off-by: Babu Moger <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 247b18c593ec298446645af8d5d28911daf653b1
      
https://github.com/qemu/qemu/commit/247b18c593ec298446645af8d5d28911daf653b1
  Author: Babu Moger <address@hidden>
  Date:   2020-03-31 (Tue, 31 Mar 2020)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  target/i386: Enable new apic id encoding for EPYC based cpus models

The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
This works fine for most standard AMD and other vendors' configurations,
but this decoding sequence does not follow that of AMD's APIC ID enumeration
strictly. In some cases this can cause CPU topology inconsistency.

When booting a guest VM, the kernel tries to validate the topology, and finds
it inconsistent with the enumeration of EPYC cpu models. The more details are
in the bug https://bugzilla.redhat.com/show_bug.cgi?id=1728166.

To fix the problem we need to build the topology as per the Processor
Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors. The documentation is available from the bugzilla Link below.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
It is also available at
https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip

Here is the text from the PPR.
Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
number of least significant bits in the Initial APIC ID that indicate core ID
within a processor, in constructing per-core CPUID masks.
Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
(MNC) that the processor could theoretically support, not the actual number of
cores that are actually implemented or enabled on the processor, as indicated
by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}

The new apic id encoding is enabled for EPYC and EPYC-Rome models.

Signed-off-by: Babu Moger <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Acked-by: Igor Mammedov <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 7b225762c8c05fd31d4c2be116aedfbc00383f8b
      
https://github.com/qemu/qemu/commit/7b225762c8c05fd31d4c2be116aedfbc00383f8b
  Author: Babu Moger <address@hidden>
  Date:   2020-03-31 (Tue, 31 Mar 2020)

  Changed paths:
    M hw/i386/pc.c
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Fix pkg_id offset for EPYC cpu models

If the system is numa configured the pkg_offset needs
to be adjusted for EPYC cpu models. Fix it calling the
model specific handler.

Signed-off-by: Babu Moger <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: ddc2fc9e4e42ebce48b088963dc7fbd1c08d5f33
      
https://github.com/qemu/qemu/commit/ddc2fc9e4e42ebce48b088963dc7fbd1c08d5f33
  Author: Luwei Kang <address@hidden>
  Date:   2020-03-31 (Tue, 31 Mar 2020)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  target/i386: set the CPUID level to 0x14 on old machine-type

The CPUID level need to be set to 0x14 manually on old
machine-type if Intel PT is enabled in guest. E.g. the
CPUID[0].EAX(level)=7 and CPUID[7].EBX[25](intel-pt)=1 when the
Qemu with "-machine pc-i440fx-3.1 -cpu qemu64,+intel-pt" parameter.

Some Intel PT capabilities are exposed by leaf 0x14 and the
missing capabilities will cause some MSRs access failed.
This patch add a warning message to inform the user to extend
the CPUID level.

Suggested-by: Eduardo Habkost <address@hidden>
Signed-off-by: Luwei Kang <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: d965dc35592d24c0c1519f1c566223c6277cb80e
      
https://github.com/qemu/qemu/commit/d965dc35592d24c0c1519f1c566223c6277cb80e
  Author: Xiaoyao Li <address@hidden>
  Date:   2020-03-31 (Tue, 31 Mar 2020)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  target/i386: Add ARCH_CAPABILITIES related bits into Icelake-Server CPU model

Current Icelake-Server CPU model lacks all the features enumerated by
MSR_IA32_ARCH_CAPABILITIES.

Add them, so that guest of "Icelake-Server" can see all of them.

Signed-off-by: Xiaoyao Li <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: f2a8261110c32c4dccd84e774d8dd7a0524e00fb
      
https://github.com/qemu/qemu/commit/f2a8261110c32c4dccd84e774d8dd7a0524e00fb
  Author: Peter Maydell <address@hidden>
  Date:   2020-04-03 (Fri, 03 Apr 2020)

  Changed paths:
    M hw/i386/pc.c
    M hw/i386/x86.c
    M include/hw/i386/topology.h
    M include/hw/i386/x86.h
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' 
into staging

x86 queue for -rc2

Fixes:
* EPYC CPU model APIC ID topology fixes (Babu Moger)
* Fix crash when enabling intel-pt on older machine types
  (Luwei Kang)
* Add missing ARCH_CAPABILITIES bits to Icelake-Server CPU model
  (Xiaoyao Li)

# gpg: Signature made Thu 02 Apr 2020 23:18:30 BST
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Eduardo Habkost <address@hidden>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  target/i386: Add ARCH_CAPABILITIES related bits into Icelake-Server CPU model
  target/i386: set the CPUID level to 0x14 on old machine-type
  i386: Fix pkg_id offset for EPYC cpu models
  target/i386: Enable new apic id encoding for EPYC based cpus models
  hw/i386: Move arch_id decode inside x86_cpus_init
  i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition
  hw/i386: Introduce apicid functions inside X86MachineState
  target/i386: Cleanup and use the EPYC mode topology functions
  hw/386: Add EPYC mode topology decoding functions

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/5142ca078d1c...f2a8261110c3