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[Qemu-commits] [qemu/qemu] 312b42: tcg/i386: Bound shift count expanding


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 312b42: tcg/i386: Bound shift count expanding sari_vec
Date: Thu, 19 Mar 2020 03:30:15 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 312b426fea4d6dd322d7472c80010a8ba7a166d2
      
https://github.com/qemu/qemu/commit/312b426fea4d6dd322d7472c80010a8ba7a166d2
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M tcg/i386/tcg-target.inc.c

  Log Message:
  -----------
  tcg/i386: Bound shift count expanding sari_vec

A given RISU testcase for SVE can produce

tcg-op-vec.c:511: do_shifti: Assertion `i >= 0 && i < (8 << vece)' failed.

because expand_vec_sari gave a shift count of 32 to a MO_32
vector shift.

In 44f1441dbe1, we changed from direct expansion of vector opcodes
to re-use of the tcg expanders.  So while the comment correctly notes
that the hw will handle such a shift count, we now have to take our
own sanity checks into account.  Which is easy in this particular case.

Fixes: 44f1441dbe1
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 43d1ccd2a02fadf3c36b46a8c31125a28864d141
      
https://github.com/qemu/qemu/commit/43d1ccd2a02fadf3c36b46a8c31125a28864d141
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c
    M configure

  Log Message:
  -----------
  tcg: Remove CONFIG_VECTOR16

The comment in tcg-runtime-gvec.c about CONFIG_VECTOR16 says that
tcg-op-gvec.c has eliminated size 8 vectors, and only passes on
multiples of 16.  This may have been true of the first few operations,
but is not true of all operations.

In particular, multiply, shift by scalar, and compare of 8- and 16-bit
elements are not expanded inline if host vector operations are not
supported.

For an x86_64 host that does not support AVX, this means that we will
fall back to the helper, which will attempt to use SSE instructions,
which will SEGV on an invalid 8-byte aligned memory operation.

This patch simply removes the CONFIG_VECTOR16 code and configuration
without further simplification.

Buglink: https://bugs.launchpad.net/bugs/1863508
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 6c7ab3015ac498181444deff55dcc8fd43ad468c
      
https://github.com/qemu/qemu/commit/6c7ab3015ac498181444deff55dcc8fd43ad468c
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c

  Log Message:
  -----------
  tcg: Tidy tcg-runtime-gvec.c types

Partial cleanup from the CONFIG_VECTOR16 removal.
Replace the vec* types with their scalar expansions.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 0a83e43a9ee624b44da61514db9b77d86e74e8c2
      
https://github.com/qemu/qemu/commit/0a83e43a9ee624b44da61514db9b77d86e74e8c2
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c

  Log Message:
  -----------
  tcg: Tidy tcg-runtime-gvec.c DUP*

Partial cleanup from the CONFIG_VECTOR16 removal.
Replace the DUP* expansions with the scalar argument.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 0270bd503e3699b7202200a2d693ad1feb57473f
      
https://github.com/qemu/qemu/commit/0270bd503e3699b7202200a2d693ad1feb57473f
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c

  Log Message:
  -----------
  tcg: Remove tcg-runtime-gvec.c DO_CMP0

Partial cleanup from the CONFIG_VECTOR16 removal.
Replace DO_CMP0 with its scalar expansion, a simple negation.

Signed-off-by: Richard Henderson <address@hidden>


  Commit: 0a4833b3b4bce181834d4c736ceba78434dfd471
      
https://github.com/qemu/qemu/commit/0a4833b3b4bce181834d4c736ceba78434dfd471
  Author: Peter Maydell <address@hidden>
  Date:   2020-03-18 (Wed, 18 Mar 2020)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c
    M configure
    M tcg/i386/tcg-target.inc.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200317' into staging

Fix tcg/i386 bug vs sari_vec.
Fix tcg-runtime-gvec.c vs i386 without avx.

# gpg: Signature made Tue 17 Mar 2020 18:58:14 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Richard Henderson <address@hidden>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20200317:
  tcg: Remove tcg-runtime-gvec.c DO_CMP0
  tcg: Tidy tcg-runtime-gvec.c DUP*
  tcg: Tidy tcg-runtime-gvec.c types
  tcg: Remove CONFIG_VECTOR16
  tcg/i386: Bound shift count expanding sari_vec

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/9214813489eb...0a4833b3b4bc



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