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[Qemu-commits] [qemu/qemu] 8c4985: hw/intc/armv7m_nvic: Rebuild hflags o
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 8c4985: hw/intc/armv7m_nvic: Rebuild hflags on reset |
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Date: |
Thu, 12 Mar 2020 13:45:12 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 8c4985298fca616e91b88996c225a9efd04b7500
https://github.com/qemu/qemu/commit/8c4985298fca616e91b88996c225a9efd04b7500
Author: Peter Maydell <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
hw/intc/armv7m_nvic: Rebuild hflags on reset
Some of an M-profile CPU's cached hflags state depends on state that's
in our NVIC object. We already do an hflags rebuild when the NVIC
registers are written, but we also need to do this on NVIC reset,
because there's no guarantee that this will happen before the
CPU reset.
This fixes an assertion due to mismatched hflags which happens if
the CPU is reset from inside a HardFault handler.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 0ea9e6583b0778568ba4c6e749f2848291e4a9b8
https://github.com/qemu/qemu/commit/0ea9e6583b0778568ba4c6e749f2848291e4a9b8
Author: Peter Maydell <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Update hflags in trans_CPS_v7m()
For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index
(it changes the NegPri bit). We update the hflags after calls
to the v7m_msr helper in trans_MSR_v7m() but forgot to do so
in trans_CPS_v7m().
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 19717e9b44f5a14bbf92fb3bb9b99006d2f63dcf
https://github.com/qemu/qemu/commit/19717e9b44f5a14bbf92fb3bb9b99006d2f63dcf
Author: Peter Maydell <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M target/arm/helper.c
M target/arm/helper.h
M target/arm/translate.c
Log Message:
-----------
target/arm: Recalculate hflags correctly after writes to CONTROL
A write to the CONTROL register can change our current EL (by
writing to the nPRIV bit). That means that we can't assume
that s->current_el is still valid in trans_MSR_v7m() when
we try to rebuild the hflags.
Add a new helper rebuild_hflags_m32_newel() which, like the
existing rebuild_hflags_a32_newel(), recalculates the current
EL from scratch, and use it in trans_MSR_v7m().
This fixes an assertion about an hflags mismatch when the
guest changes privilege by writing to CONTROL.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 563152e0d4cff72eaa2e1de36a842e99ea3c222f
https://github.com/qemu/qemu/commit/563152e0d4cff72eaa2e1de36a842e99ea3c222f
Author: Peter Maydell <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M target/arm/helper.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Fix some comment typos
Fix a couple of comment typos.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: bd6ce9a6ed99889803b044510dc753ed6ac7bfeb
https://github.com/qemu/qemu/commit/bd6ce9a6ed99889803b044510dc753ed6ac7bfeb
Author: Cédric Le Goater <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M Makefile.objs
M hw/ssi/aspeed_smc.c
A hw/ssi/trace-events
Log Message:
-----------
aspeed/smc: Add some tracing
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e7e741ca9dc24dc01cd2b7cb86e8ca5c0b0d9bec
https://github.com/qemu/qemu/commit/e7e741ca9dc24dc01cd2b7cb86e8ca5c0b0d9bec
Author: Cédric Le Goater <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/ssi/aspeed_smc.c
M hw/ssi/trace-events
Log Message:
-----------
aspeed/smc: Fix User mode select/unselect scheme
The Aspeed SMC Controller can operate in different modes : Read, Fast
Read, Write and User modes. When the User mode is configured, it
selects automatically the SPI slave device until the CE_STOP_ACTIVE
bit is set to 1. When any other modes are configured the device is
unselected. The HW logic handles the chip select automatically when
the flash is accessed through its AHB window.
When configuring the CEx Control Register, the User mode logic to
select and unselect the slave is incorrect and data corruption can be
seen on machines using two chips, witherspoon and romulus.
Rework the handler setting the CEx Control Register to fix this issue.
Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)")
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: cebfb64859284c3c451d14564fdd22546c48696e
https://github.com/qemu/qemu/commit/cebfb64859284c3c451d14564fdd22546c48696e
Author: Richard Henderson <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Check addresses for disabled regimes
We fail to validate the upper bits of a virtual address on a
translation disabled regime, as per AArch64.TranslateAddressS1Off.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 38d931687fa196a7ef860f8583815abc7fd5521a
https://github.com/qemu/qemu/commit/38d931687fa196a7ef860f8583815abc7fd5521a
Author: Richard Henderson <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Disable clean_data_tbi for system mode
We must include the tag in the FAR_ELx register when raising
an addressing exception. Which means that we should not clear
out the tag during translation.
We cannot at present comply with this for user mode, so we
retain the clean_data_tbi function for the moment, though it
no longer does what it says on the tin for system mode. This
function is to be replaced with MTE, so don't worry about the
slight misnaming.
Buglink: https://bugs.launchpad.net/qemu/+bug/1867072
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: d6f33c557ce9e4a9c5c7285e7aa71b5884241629
https://github.com/qemu/qemu/commit/d6f33c557ce9e4a9c5c7285e7aa71b5884241629
Author: Igor Mammedov <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/cubieboard.c
Log Message:
-----------
hw/arm/cubieboard: make sure SOC object isn't leaked
SOC object returned by object_new() is leaked in current code.
Set SOC parent explicitly to board and then unref to SOC object
to make sure that refererence returned by object_new() is taken
care of.
The SOC object will be kept alive by its parent (machine) and
will be automatically freed when MachineState is destroyed.
Signed-off-by: Igor Mammedov <address@hidden>
Reported-by: Andrew Jones <address@hidden>
Tested-by: Niek Linnenbank <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: bfae1772c4377fdaa1b33ca361edf8d70a7ae820
https://github.com/qemu/qemu/commit/bfae1772c4377fdaa1b33ca361edf8d70a7ae820
Author: Guenter Roeck <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/fsl-imx25.c
M hw/arm/imx25_pdk.c
M include/hw/arm/fsl-imx25.h
Log Message:
-----------
hw/arm/fsl-imx25: Wire up eSDHC controllers
Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives
provided on the command line to available eSDHC controllers.
This patch enables booting the imx25-pdk emulation from SD card.
Signed-off-by: Guenter Roeck <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: made commit subject consistent with other patch]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 67f52ebe54b0c1cfd141d46b9135d7f9b9956d7f
https://github.com/qemu/qemu/commit/67f52ebe54b0c1cfd141d46b9135d7f9b9956d7f
Author: Guenter Roeck <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/fsl-imx25.c
M include/hw/arm/fsl-imx25.h
Log Message:
-----------
hw/arm/fsl-imx25: Wire up USB controllers
i.MX25 supports two USB controllers. Let's wire them up.
With this patch, imx25-pdk can boot from both USB ports.
Signed-off-by: Guenter Roeck <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 740dafc0ba0787abddb0ec8daf8f23759112ac81
https://github.com/qemu/qemu/commit/740dafc0ba0787abddb0ec8daf8f23759112ac81
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M MAINTAINERS
M default-configs/arm-softmmu.mak
M hw/arm/Kconfig
M hw/arm/Makefile.objs
A hw/arm/allwinner-h3.c
A include/hw/arm/allwinner-h3.h
Log Message:
-----------
hw/arm: add Allwinner H3 System-on-Chip
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
processor cores. Features and specifications include DDR2/DDR3 memory,
SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
various I/O modules. This commit adds support for the Allwinner H3
System on Chip.
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b0c966661e9fcdf48bb736414df8230ab2a2da9d
https://github.com/qemu/qemu/commit/b0c966661e9fcdf48bb736414df8230ab2a2da9d
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M MAINTAINERS
M hw/arm/Makefile.objs
A hw/arm/orangepi.c
Log Message:
-----------
hw/arm: add Xunlong Orange Pi PC machine
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
based embedded computer with mainline support in both U-Boot
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
various other I/O. This commit add support for the Xunlong
Orange Pi PC machine.
Signed-off-by: Niek Linnenbank <address@hidden>
Tested-by: KONRAD Frederic <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Acked-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: fef06c8b1b2ea786e660f0c694dc88d052cde33c
https://github.com/qemu/qemu/commit/fef06c8b1b2ea786e660f0c694dc88d052cde33c
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/allwinner-h3.c
M hw/misc/Makefile.objs
A hw/misc/allwinner-h3-ccu.c
M include/hw/arm/allwinner-h3.h
A include/hw/misc/allwinner-h3-ccu.h
Log Message:
-----------
hw/arm/allwinner-h3: add Clock Control Unit
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2e4dfe80f04e31e60d2664b3b81b3681e41a5ff2
https://github.com/qemu/qemu/commit/2e4dfe80f04e31e60d2664b3b81b3681e41a5ff2
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/Kconfig
M hw/arm/allwinner-h3.c
M hw/usb/hcd-ehci-sysbus.c
M hw/usb/hcd-ehci.h
M include/hw/arm/allwinner-h3.h
Log Message:
-----------
hw/arm/allwinner-h3: add USB host controller
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
connections which provide software access using the Enhanced
Host Controller Interface (EHCI) and Open Host Controller
Interface (OHCI) interfaces. This commit adds support for
both interfaces in the Allwinner H3 System on Chip.
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Gerd Hoffmann <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7e83c9ddbb01a94aeccb5c914fe12d4ef61a4e01
https://github.com/qemu/qemu/commit/7e83c9ddbb01a94aeccb5c914fe12d4ef61a4e01
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/allwinner-h3.c
M hw/misc/Makefile.objs
A hw/misc/allwinner-h3-sysctrl.c
M include/hw/arm/allwinner-h3.h
A include/hw/misc/allwinner-h3-sysctrl.h
Log Message:
-----------
hw/arm/allwinner-h3: add System Control module
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d26af5ded95c9fb9031786bf10ab0ad7c0e848e9
https://github.com/qemu/qemu/commit/d26af5ded95c9fb9031786bf10ab0ad7c0e848e9
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/allwinner-h3.c
M hw/misc/Makefile.objs
A hw/misc/allwinner-cpucfg.c
M hw/misc/trace-events
M include/hw/arm/allwinner-h3.h
A include/hw/misc/allwinner-cpucfg.h
Log Message:
-----------
hw/arm/allwinner: add CPU Configuration module
Various Allwinner System on Chip designs contain multiple processors
that can be configured and reset using the generic CPU Configuration
module interface. This commit adds support for the Allwinner CPU
configuration interface which emulates the following features:
* CPU reset
* CPU status
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 6556617ce1a3c4a2ad91e5c5d1c936ee9134ed04
https://github.com/qemu/qemu/commit/6556617ce1a3c4a2ad91e5c5d1c936ee9134ed04
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/allwinner-h3.c
M hw/arm/orangepi.c
M hw/misc/Makefile.objs
A hw/misc/allwinner-sid.c
M hw/misc/trace-events
M include/hw/arm/allwinner-h3.h
A include/hw/misc/allwinner-sid.h
Log Message:
-----------
hw/arm/allwinner: add Security Identifier device
The Security Identifier device found in various Allwinner System on Chip
designs gives applications a per-board unique identifier. This commit
adds support for the Allwinner Security Identifier using a 128-bit
UUID value as input.
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 82e4838249b23c3fe20cee295f9c1b3e6abd68d1
https://github.com/qemu/qemu/commit/82e4838249b23c3fe20cee295f9c1b3e6abd68d1
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/Kconfig
M hw/arm/allwinner-a10.c
M hw/arm/allwinner-h3.c
M hw/arm/cubieboard.c
M hw/arm/orangepi.c
M hw/sd/Makefile.objs
A hw/sd/allwinner-sdhost.c
M hw/sd/trace-events
M include/hw/arm/allwinner-a10.h
M include/hw/arm/allwinner-h3.h
A include/hw/sd/allwinner-sdhost.h
Log Message:
-----------
hw/arm/allwinner: add SD/MMC host controller
The Allwinner System on Chip families sun4i and above contain
an integrated storage controller for Secure Digital (SD) and
Multi Media Card (MMC) interfaces. This commit adds support
for the Allwinner SD/MMC storage controller with the following
emulated features:
* DMA transfers
* Direct FIFO I/O
* Short/Long format command responses
* Auto-Stop command (CMD12)
* Insert & remove card detection
The following boards are extended with the SD host controller:
* Cubieboard (hw/arm/cubieboard.c)
* Orange Pi PC (hw/arm/orangepi.c)
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 29d08975d1cc2ec668d9eb430c507a4fee515ea5
https://github.com/qemu/qemu/commit/29d08975d1cc2ec668d9eb430c507a4fee515ea5
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/Kconfig
M hw/arm/allwinner-h3.c
M hw/arm/orangepi.c
M hw/net/Kconfig
M hw/net/Makefile.objs
A hw/net/allwinner-sun8i-emac.c
M hw/net/trace-events
M include/hw/arm/allwinner-h3.h
A include/hw/net/allwinner-sun8i-emac.h
Log Message:
-----------
hw/arm/allwinner-h3: add EMAC ethernet device
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
which provides 10M/100M/1000M Ethernet connectivity. This commit
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc),
including emulation for the following functionality:
* DMA transfers
* MII interface
* Transmit CRC calculation
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: a80beb160d4e89937b0afccb146a9f3247f88588
https://github.com/qemu/qemu/commit/a80beb160d4e89937b0afccb146a9f3247f88588
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/allwinner-h3.c
M hw/arm/orangepi.c
M include/hw/arm/allwinner-h3.h
Log Message:
-----------
hw/arm/allwinner-h3: add Boot ROM support
A real Allwinner H3 SoC contains a Boot ROM which is the
first code that runs right after the SoC is powered on.
The Boot ROM is responsible for loading user code (e.g. a bootloader)
from any of the supported external devices and writing the downloaded
code to internal SRAM. After loading the SoC begins executing the code
written to SRAM.
This commits adds emulation of the Boot ROM firmware setup functionality
by loading user code from SD card in the A1 SRAM. While the A1 SRAM is
64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects
sizes larger than 32KiB. For reference, this behaviour is documented
by the Linux Sunxi project wiki at:
https://linux-sunxi.org/BROM#U-Boot_SPL_limitations
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b71d0385e97e230b45a88c604756c44a748736fb
https://github.com/qemu/qemu/commit/b71d0385e97e230b45a88c604756c44a748736fb
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/allwinner-h3.c
M hw/arm/orangepi.c
M hw/misc/Makefile.objs
A hw/misc/allwinner-h3-dramc.c
M hw/misc/trace-events
M include/hw/arm/allwinner-h3.h
A include/hw/misc/allwinner-h3-dramc.h
Log Message:
-----------
hw/arm/allwinner-h3: add SDRAM controller device
In the Allwinner H3 SoC the SDRAM controller is responsible
for interfacing with the external Synchronous Dynamic Random
Access Memory (SDRAM). Types of memory that the SDRAM controller
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
adds emulation support of the Allwinner H3 SDRAM controller.
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: a9ad9e73a733fee77b8287b660e2c9894cbc5255
https://github.com/qemu/qemu/commit/a9ad9e73a733fee77b8287b660e2c9894cbc5255
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/allwinner-a10.c
M hw/arm/allwinner-h3.c
M hw/rtc/Makefile.objs
A hw/rtc/allwinner-rtc.c
M hw/rtc/trace-events
M include/hw/arm/allwinner-a10.h
M include/hw/arm/allwinner-h3.h
A include/hw/rtc/allwinner-rtc.h
Log Message:
-----------
hw/arm/allwinner: add RTC device support
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
for non-volatile system date and time keeping. This commit adds a generic
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
The following RTC functionality and features are implemented:
* Year-Month-Day read/write
* Hour-Minute-Second read/write
* General Purpose storage
The following boards are extended with the RTC device:
* Cubieboard (hw/arm/cubieboard.c)
* Orange Pi PC (hw/arm/orangepi.c)
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5abe9f0baacbf824ff690f605cb56b66fd02355d
https://github.com/qemu/qemu/commit/5abe9f0baacbf824ff690f605cb56b66fd02355d
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
tests/boot_linux_console: Add a quick test for the OrangePi PC board
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ make check-venv
$ ./tests/venv/bin/avocado --show=console,app run -t machine:orangepi-pc
tests/acceptance/boot_linux_console.py
JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a
JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log
(1/1)
tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (address@hidden) (gcc version 7.2.1
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction
cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
console: Memory policy: Data cache writealloc
console: OF: reserved mem: failed to allocate memory for node 'cma@4a000000'
console: cma: Failed to reserve 128 MiB
console: psci: probing for conduit method from DT.
console: psci: PSCIv0.2 detected in firmware.
console: psci: Using standard PSCI v0.2 function IDs
console: psci: Trusted OS migration not required
console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 with
crng_init=0
console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u73728
console: Built 1 zonelists, mobility grouping on. Total pages: 32480
console: Kernel command line: printk.time=0 console=ttyS0,115200
PASS (8.59 s)
JOB TIME : 8.81 s
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
Signed-off-by: Peter Maydell <address@hidden>
Commit: c40b1ded0af6ee5b26e4b2eb5e0ce68c308e8de3
https://github.com/qemu/qemu/commit/c40b1ded0af6ee5b26e4b2eb5e0ce68c308e8de3
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The cpio image used comes from the linux-build-test project:
https://github.com/groeck/linux-build-test
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ avocado --show=console run -t machine:orangepi-pc
tests/acceptance/boot_linux_console.py
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (address@hidden) (gcc version 7.2.1
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction
cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
[...]
console: Trying to unpack rootfs image as initramfs...
console: Freeing initrd memory: 3256K
console: Freeing unused kernel memory: 1024K
console: Run /init as init process
console: mount: mounting devtmpfs on /dev failed: Device or resource busy
console: Starting logging: OK
console: Initializing random number generator... random: dd: uninitialized
urandom read (512 bytes read)
console: done.
console: Starting network: OK
console: Found console ttyS0
console: Linux version 4.20.7-sunxi (address@hidden) (gcc version 7.2.1
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: Boot successful.
console: cat /proc/cpuinfo
console: / # cat /proc/cpuinfo
console: processor : 0
console: model name : ARMv7 Processor rev 5 (v7l)
console: BogoMIPS : 125.00
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4
idiva idivt vfpd32 lpae evtstrm
console: CPU implementer : 0x41
console: CPU architecture: 7
console: CPU variant : 0x0
console: CPU part : 0xc07
console: CPU revision : 5
[...]
console: processor : 3
console: model name : ARMv7 Processor rev 5 (v7l)
console: BogoMIPS : 125.00
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4
idiva idivt vfpd32 lpae evtstrm
console: CPU implementer : 0x41
console: CPU architecture: 7
console: CPU variant : 0x0
console: CPU part : 0xc07
console: CPU revision : 5
console: Hardware : Allwinner sun8i Family
console: Revision : 0000
console: Serial : 0000000000000000
console: cat /proc/iomem
console: / # cat /proc/iomem
console: 01000000-010fffff : clock@1000000
console: 01c00000-01c00fff : system-control@1c00000
console: 01c02000-01c02fff : dma-controller@1c02000
[...]
console: reboot
console: / # reboot
console: / # Found console ttyS0
console: Stopping network: OK
console: hrtimer: interrupt took 21852064 ns
console: Saving random seed... random: dd: uninitialized urandom read (512
bytes read)
console: done.
console: Stopping logging: OK
console: umount: devtmpfs busy - remounted read-only
console: umount: can't unmount /: Invalid argument
console: The system is going down NOW!
console: Sent SIGTERM to all processes
console: Sent SIGKILL to all processes
console: Requesting system reboot
console: reboot: Restarting system
PASS (48.32 s)
JOB TIME : 49.16 s
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
Signed-off-by: Peter Maydell <address@hidden>
Commit: de2749bcb2459d0722022fb70c70310a04413fc1
https://github.com/qemu/qemu/commit/de2749bcb2459d0722022fb70c70310a04413fc1
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The SD image is from the kernelci.org project:
https://kernelci.org/faq/#the-code
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ avocado --show=console run -t machine:orangepi-pc
tests/acceptance/boot_linux_console.py
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (address@hidden) (gcc version 7.2.1
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
[...]
console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=16 sec,
nowayout=0)
console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2
console: sunxi-mmc 1c0f000.mmc: Got CD GPIO
console: ledtrig-cpu: registered to indicate activity on CPUs
console: hidraw: raw HID events driver (C) Jiri Kosina
console: usbcore: registered new interface driver usbhid
console: usbhid: USB HID core driver
console: Initializing XFRM netlink socket
console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB
console: NET: Registered protocol family 10
console: mmc0: host does not support reading read-only switch, assuming
write-enable
console: mmc0: Problem switching card into high-speed mode!
console: mmc0: new SD card at address 4567
console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB
[...]
console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subsystem
console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (null)
console: VFS: Mounted root (ext2 filesystem) on device 179:0.
console: Run /sbin/init as init process
console: EXT4-fs (mmcblk0): re-mounted. Opts:
block_validity,barrier,user_xattr,acl
console: Starting syslogd: OK
console: Starting klogd: OK
console: Populating /dev using udev: udevd[203]: starting version 3.2.7
console: /bin/sh: can't access tty; job control turned off
console: cat /proc/partitions
console: / # cat /proc/partitions
console: major minor #blocks name
console: 1 0 4096 ram0
console: 1 1 4096 ram1
console: 1 2 4096 ram2
console: 1 3 4096 ram3
console: 179 0 61440 mmcblk0
console: reboot
console: / # reboot
console: umount: devtmpfs busy - remounted read-only
console: EXT4-fs (mmcblk0): re-mounted. Opts: (null)
console: The system is going down NOW!
console: Sent SIGTERM to all processes
console: Sent SIGKILL to all processes
console: Requesting system reboot
console: reboot: Restarting system
JOB TIME : 68.64 s
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
[NL: extend test with ethernet device checks]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 784b8796380532351737d753a6a092ed4e1ffebf
https://github.com/qemu/qemu/commit/784b8796380532351737d753a6a092ed4e1ffebf
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
This test boots Ubuntu Bionic on a OrangePi PC board.
As it requires 1GB of storage, and is slow, this test is disabled
on automatic CI testing.
It is useful for workstation testing. Currently Avocado timeouts too
quickly, so we can't run userland commands.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The Ubuntu image is downloaded from:
https://dl.armbian.com/orangepipc/Bionic_current
This test can be run using:
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
avocado --show=app,console run -t machine:orangepi-pc \
tests/acceptance/boot_linux_console.py
console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100)
console: DRAM: 1024 MiB
console: Failed to set core voltage! Can't set CPU frequency
console: Trying to boot from MMC1
console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner
Technology
console: CPU: Allwinner H3 (SUN8I 0000)
console: Model: Xunlong Orange Pi PC
console: DRAM: 1 GiB
console: MMC: mmc@1c0f000: 0
[...]
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU
Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.11.3
SMP Mon Nov 18 18:49:43 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction
cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
[...]
console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode.
Opts: (null)
console: done.
console: Begin: Running /scripts/local-bottom ... done.
console: Begin: Running /scripts/init-bottom ... done.
console: systemd[1]: systemd 237 running in system mode. (...)
console: systemd[1]: Detected architecture arm.
console: Welcome to Ubuntu 18.04.3 LTS!
console: systemd[1]: Set hostname to <orangepipc>.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
[NL: changed test to boot from SD card via BootROM, added check for 7z]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 921589fb72441e9f3f91a5291d703ffa64cce860
https://github.com/qemu/qemu/commit/921589fb72441e9f3f91a5291d703ffa64cce860
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
This test boots U-Boot then NetBSD (stored on a SD card) on
a OrangePi PC board.
As it requires ~1.3GB of storage, it is disabled by default.
U-Boot is built by the Debian project [1], and the SD card image
is provided by the NetBSD organization [2].
Once the compressed SD card image is downloaded (304MB) and
extracted, this test is fast:
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
avocado --show=app,console run -t machine:orangepi-pc \
tests/acceptance/boot_linux_console.py
console: U-Boot SPL 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000)
console: DRAM: 1024 MiB
console: U-Boot 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) Allwinner
Technology
console: CPU: Allwinner H3 (SUN8I 0000)
console: scanning bus usb@1c1b000 for devices... 1 USB Device(s) found
console: scanning bus usb@1c1d000 for devices... 1 USB Device(s) found
console: scanning usb for storage devices... 0 Storage Device(s) found
console: Hit any key to stop autoboot: 0
console: => setenv bootargs root=ld0a
console: => setenv kernel netbsd-GENERIC.ub
console: => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
console: => boot
console: ## Booting kernel from Legacy Image at 42000000 ...
console: Image Name: NetBSD/earmv7hf 9.0_RC1
console: Image Type: ARM Linux Kernel Image (no loading done) (uncompressed)
console: XIP Kernel Image (no loading done)
console: Loading Device Tree to 49ff6000, end 49fffe01 ... OK
console: Starting kernel ...
console: [ 1.0000000] NetBSD/evbarm (fdt) booting ...
console: [ 1.0000000] NetBSD 9.0 (GENERIC) #0: Fri Feb 14 00:06:28 UTC 2020
console: [ 1.0000000]
address@hidden:/usr/src/sys/arch/evbarm/compile/GENERIC
console: [ 1.0000000] total memory = 1024 MB
console: [ 1.0000000] avail memory = 1003 MB
console: [ 1.0000000] armfdt0 (root)
console: [ 1.0000000] simplebus0 at armfdt0: Xunlong Orange Pi PC
console: [ 1.0000000] cpu0 at cpus0: Cortex-A7 r0p5 (Cortex V7A core)
console: [ 1.0000000] cpu0: DC enabled IC enabled WB enabled LABT branch
prediction enabled
console: [ 1.0000000] cpu0: 32KB/64B 2-way L1 VIPT Instruction cache
console: [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT
Data cache
console: [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified
cache
console: [ 1.0000000] vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN
propagation, denormals
...
console: [ 2.3812082] sdmmc0: SD card status: 4-bit, C0
console: [ 2.3812082] ld0 at sdmmc0:
<0xaa:0x5859:QEMU!:0x01:0xdeadbeef:0x062>
console: [ 2.4012856] ld0: 1226 MB, 622 cyl, 64 head, 63 sec, 512
bytes/sect x 2511872 sectors
console: [ 2.5321222] ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz
console: [ 3.1068718] WARNING: 4 errors while detecting hardware; check
system log.
console: [ 3.1179868] boot device: ld0
console: [ 3.1470623] root on ld0a dumps on ld0b
console: [ 3.2464436] root file system type: ffs
console: [ 3.2897123] kern.module.path=/stand/evbarm/9.0/modules
console: Mon Feb 17 20:33:35 UTC 2020
console: Starting root file system check:
PASS (35.96 s)
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 |
CANCEL 0
JOB TIME : 36.09 s
Note, this test only took ~65 seconds to run on Travis-CI, see: [3].
This test is based on a description from Niek Linnenbank from [4].
[1]
https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot
[2] https://wiki.netbsd.org/ports/evbarm/allwinner/
[3] https://travis-ci.org/philmd/qemu/jobs/638823612#L3778
[4] https://www.mail-archive.com/address@hidden/msg669347.html
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[NL: changed test to use NetBSD 9.0 final release and -global
allwinner-rtc.base-year]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 0553ef42571ea494c4607696fbd675cbecd61da0
https://github.com/qemu/qemu/commit/0553ef42571ea494c4607696fbd675cbecd61da0
Author: Niek Linnenbank <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M MAINTAINERS
A docs/system/arm/orangepi.rst
M docs/system/target-arm.rst
Log Message:
-----------
docs: add Orange Pi PC document
The Xunlong Orange Pi PC machine is a functional ARM machine
based on the Allwinner H3 System-on-Chip. It supports mainline
Linux, U-Boot, NetBSD and is covered by acceptance tests.
This commit adds a documentation text file with a description
of the machine and instructions for the user.
Signed-off-by: Niek Linnenbank <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
[PMM: moved file into docs/system/arm to match the reorg
of the arm target part of the docs; tweaked heading to
match other boards]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 71b296d981f34763e1ff5bb45e1a1fedc4c8672c
https://github.com/qemu/qemu/commit/71b296d981f34763e1ff5bb45e1a1fedc4c8672c
Author: Eric Auger <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Document 'max' value in gic-version property description
Mention 'max' value in the gic-version property description.
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d04460e587c152c31e686bf7e0d6345419f649bc
https://github.com/qemu/qemu/commit/d04460e587c152c31e686bf7e0d6345419f649bc
Author: Eric Auger <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Introduce VirtGICType enum type
We plan to introduce yet another value for the gic version (nosel).
As we already use exotic values such as 0 and -1, let's introduce
a dedicated enum type and let vms->gic_version take this
type.
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 36bf4ec8c8bb943f5be99172cb0506e1b520096e
https://github.com/qemu/qemu/commit/36bf4ec8c8bb943f5be99172cb0506e1b520096e
Author: Eric Auger <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/virt.c
M include/hw/arm/virt.h
Log Message:
-----------
hw/arm/virt: Introduce finalize_gic_version()
Let's move the code which freezes which gic-version to
be applied in a dedicated function. We also now set by
default the VIRT_GIC_VERSION_NO_SET. This eventually
turns into the legacy v2 choice in the finalize() function.
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d45efe47824a3d143fdc8d5990032deff4cec72b
https://github.com/qemu/qemu/commit/d45efe47824a3d143fdc8d5990032deff4cec72b
Author: Eric Auger <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/virt.c
M target/arm/kvm.c
M target/arm/kvm_arm.h
Log Message:
-----------
target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
Convert kvm_arm_vgic_probe() so that it returns a
bitmap of supported in-kernel emulation VGIC versions instead
of the max version: at the moment values can be v2 and v3.
This allows to expose the case where the host GICv3 also
supports GICv2 emulation. This will be useful to choose the
default version in KVM accelerated mode.
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 97b4c9188c6537151defd7632bd7b5908f10052c
https://github.com/qemu/qemu/commit/97b4c9188c6537151defd7632bd7b5908f10052c
Author: Eric Auger <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: kvm: Restructure finalize_gic_version()
Restructure the finalize_gic_version with switch cases and
clearly separate the following cases:
- KVM mode / in-kernel irqchip
- KVM mode / userspace irqchip
- TCG mode
In KVM mode / in-kernel irqchip , we explictly check whether
the chosen version is supported by the host. If the end-user
explicitly sets v2/v3 and this is not supported by the host,
then the user gets an explicit error message. Note that for
old kernels where the CREATE_DEVICE ioctl doesn't exist then
we will now fail if the user specifically asked for gicv2,
where previously we (probably) would have succeeded.
In KVM mode / userspace irqchip we immediatly output an error
in case the end-user explicitly selected v3. Also we warn the
end-user about the unexpected usage of gic-version=host in
that case as only userspace GICv2 is supported.
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 6785aee00c0797c1c8ce7d07dc434ace464f97ea
https://github.com/qemu/qemu/commit/6785aee00c0797c1c8ce7d07dc434ace464f97ea
Author: Eric Auger <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work
At the moment if the end-user does not specify the gic-version along
with KVM acceleration, v2 is set by default. However most of the
systems now have GICv3 and sometimes they do not support GICv2
compatibility.
This patch keeps the default v2 selection in all cases except
in the KVM accelerated mode when either
- the host does not support GICv2 in-kernel emulation or
- number of VCPUS exceeds 8.
Those cases did not work anyway so we do not break any compatibility.
Now we get v3 selected in such a case.
Signed-off-by: Eric Auger <address@hidden>
Reported-by: Dr. David Alan Gilbert <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: aca53be34ac3e7cac5f39396a51a338860a5a837
https://github.com/qemu/qemu/commit/aca53be34ac3e7cac5f39396a51a338860a5a837
Author: Beata Michalska <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M target/arm/kvm32.c
M target/arm/kvm64.c
Log Message:
-----------
target/arm: kvm: Inject events at the last stage of sync
KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
As such this should be the last step of sync to avoid potential overwriting
of whatever changes KVM might have done.
Signed-off-by: Beata Michalska <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d4f7d56759f7c75270c13d5f3f5f736a9558929c
https://github.com/qemu/qemu/commit/d4f7d56759f7c75270c13d5f3f5f736a9558929c
Author: Peter Maydell <address@hidden>
Date: 2020-03-12 (Thu, 12 Mar 2020)
Changed paths:
M MAINTAINERS
M Makefile.objs
M default-configs/arm-softmmu.mak
A docs/system/arm/orangepi.rst
M docs/system/target-arm.rst
M hw/arm/Kconfig
M hw/arm/Makefile.objs
M hw/arm/allwinner-a10.c
A hw/arm/allwinner-h3.c
M hw/arm/cubieboard.c
M hw/arm/fsl-imx25.c
M hw/arm/imx25_pdk.c
A hw/arm/orangepi.c
M hw/arm/virt.c
M hw/intc/armv7m_nvic.c
M hw/misc/Makefile.objs
A hw/misc/allwinner-cpucfg.c
A hw/misc/allwinner-h3-ccu.c
A hw/misc/allwinner-h3-dramc.c
A hw/misc/allwinner-h3-sysctrl.c
A hw/misc/allwinner-sid.c
M hw/misc/trace-events
M hw/net/Kconfig
M hw/net/Makefile.objs
A hw/net/allwinner-sun8i-emac.c
M hw/net/trace-events
M hw/rtc/Makefile.objs
A hw/rtc/allwinner-rtc.c
M hw/rtc/trace-events
M hw/sd/Makefile.objs
A hw/sd/allwinner-sdhost.c
M hw/sd/trace-events
M hw/ssi/aspeed_smc.c
A hw/ssi/trace-events
M hw/usb/hcd-ehci-sysbus.c
M hw/usb/hcd-ehci.h
M include/hw/arm/allwinner-a10.h
A include/hw/arm/allwinner-h3.h
M include/hw/arm/fsl-imx25.h
M include/hw/arm/virt.h
A include/hw/misc/allwinner-cpucfg.h
A include/hw/misc/allwinner-h3-ccu.h
A include/hw/misc/allwinner-h3-dramc.h
A include/hw/misc/allwinner-h3-sysctrl.h
A include/hw/misc/allwinner-sid.h
A include/hw/net/allwinner-sun8i-emac.h
A include/hw/rtc/allwinner-rtc.h
A include/hw/sd/allwinner-sdhost.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/kvm.c
M target/arm/kvm32.c
M target/arm/kvm64.c
M target/arm/kvm_arm.h
M target/arm/translate-a64.c
M target/arm/translate.c
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200312'
into staging
target-arm queue:
* Fix various bugs that might result in an assert() due to
incorrect hflags for M-profile CPUs
* Fix Aspeed SMC Controller user-mode select handling
* Report correct (with-tag) address in fault address register
when TBI is enabled
* cubieboard: make sure SOC object isn't leaked
* fsl-imx25: Wire up eSDHC controllers
* fsl-imx25: Wire up USB controllers
* New board model: orangepi-pc (OrangePi PC)
* ARM/KVM: if user doesn't select GIC version and the
host kernel can only provide GICv3, use that, rather
than defaulting to "fail because GICv2 isn't possible"
* kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync
# gpg: Signature made Thu 12 Mar 2020 16:43:46 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200312: (36 commits)
target/arm: kvm: Inject events at the last stage of sync
hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work
hw/arm/virt: kvm: Restructure finalize_gic_version()
target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
hw/arm/virt: Introduce finalize_gic_version()
hw/arm/virt: Introduce VirtGICType enum type
hw/arm/virt: Document 'max' value in gic-version property description
docs: add Orange Pi PC document
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
tests/boot_linux_console: Add a quick test for the OrangePi PC board
hw/arm/allwinner: add RTC device support
hw/arm/allwinner-h3: add SDRAM controller device
hw/arm/allwinner-h3: add Boot ROM support
hw/arm/allwinner-h3: add EMAC ethernet device
hw/arm/allwinner: add SD/MMC host controller
hw/arm/allwinner: add Security Identifier device
hw/arm/allwinner: add CPU Configuration module
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/49780a582d8b...d4f7d56759f7
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