[Qemu-commits] [qemu/qemu] 8a2186: hw/arm: versal: Add support for the L

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[Qemu-commits] [qemu/qemu] 8a2186: hw/arm: versal: Add support for the L

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 8a2186: hw/arm: versal: Add support for the LPD ADMAs
Date:	Thu, 05 Mar 2020 10:00:13 -0800
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8a21865157b4d234f0ea1a5862feb913813e9409
      
https://github.com/qemu/qemu/commit/8a21865157b4d234f0ea1a5862feb913813e9409
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm: versal: Add support for the LPD ADMAs

Add support for the Versal LPD ADMAs.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ce5f4f01116b2002925877930d603690296be519
      
https://github.com/qemu/qemu/commit/ce5f4f01116b2002925877930d603690296be519
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c

  Log Message:
  -----------
  hw/arm: versal: Generate xlnx-versal-virt zdma FDT nodes

Generate xlnx-versal-virt zdma FDT nodes.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 41a4bf1feab098da4cd5495cd56a99b0339e2275
      
https://github.com/qemu/qemu/commit/41a4bf1feab098da4cd5495cd56a99b0339e2275
  Author: Peter Maydell <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu64.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement (trivially) ARMv8.2-TTCNP

The ARMv8.2-TTCNP extension allows an implementation to optimize by
sharing TLB entries between multiple cores, provided that software
declares that it's ready to deal with this by setting a CnP bit in
the TTBRn_ELx.  It is mandatory from ARMv8.2 onward.

For QEMU's TLB implementation, sharing TLB entries between different
cores would not really benefit us and would be a lot of work to
implement.  So we implement this extension in the "trivial" manner:
we allow the guest to set and read back the CnP bit, but don't change
our behaviour (this is an architecturally valid implementation
choice).

The only code path which looks at the TTBRn_ELx values for the
long-descriptor format where the CnP bit is defined is already doing
enough masking to not get confused when the CnP bit at the bottom of
the register is set, so we can simply add a comment noting why we're
relying on that mask.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: a2d3b8f24c53b3c7d4cf07cb92b2db42abf804d0
      
https://github.com/qemu/qemu/commit/a2d3b8f24c53b3c7d4cf07cb92b2db42abf804d0
  Author: Eric Auger <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/smmu-common.c

  Log Message:
  -----------
  hw/arm/smmu-common: a fix to smmu_find_smmu_pcibus

Make sure a null SMMUPciBus is returned in case we were
not able to identify a pci bus matching the @bus_num.

This matches the fix done on intel iommu in commit:
a2e1cd41ccfe796529abfd1b6aeb1dd4393762a2

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5ca0e6fec591fd07add84f1f28b5c95a494b8401
      
https://github.com/qemu/qemu/commit/5ca0e6fec591fd07add84f1f28b5c95a494b8401
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/smmu-common.c

  Log Message:
  -----------
  hw/arm/smmu-common: Simplify smmu_find_smmu_pcibus() logic

The smmu_find_smmu_pcibus() function was introduced (in commit
cac994ef43b) in a code format that could return an incorrect
pointer, which was then fixed by the previous commit.
We could have avoided this by writing the if() statement
differently. Do it now, in case this function is re-used.
The code is easier to review (harder to miss bugs).

Acked-by: Eric Auger <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b6cb2453da92e983ba99d1c7a39a629595e04bf6
      
https://github.com/qemu/qemu/commit/b6cb2453da92e983ba99d1c7a39a629595e04bf6
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/gumstix.c

  Log Message:
  -----------
  hw/arm/gumstix: Simplify since the machines are little-endian only

As the Connex and Verdex machines only boot in little-endian,
we can simplify the code.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8ad1b683fd5ef7334c32c3d17b7f11cbc24e2758
      
https://github.com/qemu/qemu/commit/8ad1b683fd5ef7334c32c3d17b7f11cbc24e2758
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/mainstone.c

  Log Message:
  -----------
  hw/arm/mainstone: Simplify since the machines are little-endian only

We only build the little-endian softmmu configurations. Checking
for big endian is pointless, remove the unused code.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 88e68dfcc5f72dc18b9ca82a69902cc3a3a80fd9
      
https://github.com/qemu/qemu/commit/88e68dfcc5f72dc18b9ca82a69902cc3a3a80fd9
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/omap_sx1.c

  Log Message:
  -----------
  hw/arm/omap_sx1: Simplify since the machines are little-endian only

We only build the little-endian softmmu configurations. Checking
for big endian is pointless, remove the unused code.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 56329e38e6572bc6714282ff9f9ac0d1ed4ff55a
      
https://github.com/qemu/qemu/commit/56329e38e6572bc6714282ff9f9ac0d1ed4ff55a
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/z2.c

  Log Message:
  -----------
  hw/arm/z2: Simplify since the machines are little-endian only

We only build the little-endian softmmu configurations. Checking
for big endian is pointless, remove the unused code.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 98335f61794d96e57dbd3f3f529b8c4c7d188ba3
      
https://github.com/qemu/qemu/commit/98335f61794d96e57dbd3f3f529b8c4c7d188ba3
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/musicpal.c

  Log Message:
  -----------
  hw/arm/musicpal: Simplify since the machines are little-endian only

We only build the little-endian softmmu configurations. Checking
for big endian is pointless, remove the unused code.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1afaadb592f3eeb7043a9fb7ae507862579ebf9d
      
https://github.com/qemu/qemu/commit/1afaadb592f3eeb7043a9fb7ae507862579ebf9d
  Author: Pan Nengyuan <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/pxa2xx.c

  Log Message:
  -----------
  hw/arm/pxa2xx: move timer_new from init() into realize() to avoid memleaks

There are some memleaks when we call 'device_list_properties'. This patch move 
timer_new from init into realize to fix it.

Reported-by: Euler Robot <address@hidden>
Signed-off-by: Pan Nengyuan <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5719f9745ef54c1b644e3df0bc69869be70cf810
      
https://github.com/qemu/qemu/commit/5719f9745ef54c1b644e3df0bc69869be70cf810
  Author: Pan Nengyuan <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/spitz.c

  Log Message:
  -----------
  hw/arm/spitz: move timer_new from init() into realize() to avoid memleaks

There are some memleaks when we call 'device_list_properties'. This patch move 
timer_new from init into realize to fix it.

Reported-by: Euler Robot <address@hidden>
Signed-off-by: Pan Nengyuan <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: efb27a49af974baaad602ed26ef999f567063f12
      
https://github.com/qemu/qemu/commit/efb27a49af974baaad602ed26ef999f567063f12
  Author: Pan Nengyuan <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/strongarm.c

  Log Message:
  -----------
  hw/arm/strongarm: move timer_new from init() into realize() to avoid memleaks

There are some memleaks when we call 'device_list_properties'. This patch move 
timer_new from init into realize to fix it.

Reported-by: Euler Robot <address@hidden>
Signed-off-by: Pan Nengyuan <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f4228077e80cb30811e185d5330d2df778e667b3
      
https://github.com/qemu/qemu/commit/f4228077e80cb30811e185d5330d2df778e667b3
  Author: Pan Nengyuan <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/timer/cadence_ttc.c

  Log Message:
  -----------
  hw/timer/cadence_ttc: move timer_new from init() into realize() to avoid 
memleaks

There are some memleaks when we call 'device_list_properties'. This patch move 
timer_new from init into realize to fix it.

Reported-by: Euler Robot <address@hidden>
Signed-off-by: Pan Nengyuan <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d1fb4da208411ce7b3dafb9f9e7726ebcec14edb
      
https://github.com/qemu/qemu/commit/d1fb4da208411ce7b3dafb9f9e7726ebcec14edb
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Improve masking of HCR/HCR2 RES0 bits

Don't merely start with v8.0, handle v7VE as well.  Ensure that writes
from aarch32 mode do not change bits in the other half of the register.
Protect reads of aa64 id registers with ARM_FEATURE_AARCH64.

Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e0a38bb35aa930c2d3b9982914297f0c0e8fd5c8
      
https://github.com/qemu/qemu/commit/e0a38bb35aa930c2d3b9982914297f0c0e8fd5c8
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add HCR_EL2 bit definitions from ARMv8.6

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 45ca3a14081e069722a12db1c12facb3a73ed562
      
https://github.com/qemu/qemu/commit/45ca3a14081e069722a12db1c12facb3a73ed562
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Disable has_el2 and has_el3 for user-only

In arm_cpu_reset, we configure many system registers so that user-only
behaves as it should with a minimum of ifdefs.  However, we do not set
all of the system registers as required for a cpu with EL2 and EL3.

Disabling EL2 and EL3 mean that we will not look at those registers,
which means that we don't have to worry about configuring them.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a6c2b338113a710dbd97e5c35baf66354d615d1f
      
https://github.com/qemu/qemu/commit/a6c2b338113a710dbd97e5c35baf66354d615d1f
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Remove EL2 and EL3 setup from user-only

We have disabled EL2 and EL3 for user-only, which means that these
registers "don't exist" and should not be set.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4990e1d3c128580dd2fa0bbb1a42b6d63ba1ac28
      
https://github.com/qemu/qemu/commit/4990e1d3c128580dd2fa0bbb1a42b6d63ba1ac28
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Improve masking in arm_hcr_el2_eff

Update the {TGE,E2H} == '11' masking to ARMv8.6.
If EL2 is configured for aarch32, disable all of
the bits that are RES0 in aarch32 mode.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 84929218512c19ec9a296fbfd7b39219e0c592ae
      
https://github.com/qemu/qemu/commit/84929218512c19ec9a296fbfd7b39219e0c592ae
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Honor the HCR_EL2.{TVM,TRVM} bits

These bits trap EL1 access to various virtual memory controls.

Buglink: https://bugs.launchpad.net/bugs/1855072
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1803d2713b29d85031cc964d545036bda9880f26
      
https://github.com/qemu/qemu/commit/1803d2713b29d85031cc964d545036bda9880f26
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Honor the HCR_EL2.TSW bit

These bits trap EL1 access to set/way cache maintenance insns.

Buglink: https://bugs.launchpad.net/bugs/1863685
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9960237769ada2faaaf1898b96da7a55e1691cf4
      
https://github.com/qemu/qemu/commit/9960237769ada2faaaf1898b96da7a55e1691cf4
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Honor the HCR_EL2.TACR bit

This bit traps EL1 access to the auxiliary control registers.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1bed4d2e55459129c19f5952bcfc65bd0c70db5b
      
https://github.com/qemu/qemu/commit/1bed4d2e55459129c19f5952bcfc65bd0c70db5b
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Honor the HCR_EL2.TPCP bit

This bit traps EL1 access to cache maintenance insns that operate
to the point of coherency or persistence.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 38262d8a732f8bd0e9ca3dc064f6e73d00c08b9a
      
https://github.com/qemu/qemu/commit/38262d8a732f8bd0e9ca3dc064f6e73d00c08b9a
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Honor the HCR_EL2.TPU bit

This bit traps EL1 access to cache maintenance insns that operate
to the point of unification.  There are no longer any references to
plain aa64_cacheop_access, so remove it.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 30881b7353b5bb41210c32cd8e00421da757808c
      
https://github.com/qemu/qemu/commit/30881b7353b5bb41210c32cd8e00421da757808c
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Honor the HCR_EL2.TTLB bit

This bit traps EL1 access to tlb maintenance insns.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e2d30df9079a277c7c98a55be91dd28a7f1b8e1c
      
https://github.com/qemu/qemu/commit/e2d30df9079a277c7c98a55be91dd28a7f1b8e1c
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M tests/tcg/aarch64/pauth-1.c

  Log Message:
  -----------
  tests/tcg/aarch64: Add newline in pauth-1 printf

Make the output just a bit prettier when running by hand.

Cc: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2104df2a1fbf44b2564427aa72fd58d66ce290a7
      
https://github.com/qemu/qemu/commit/2104df2a1fbf44b2564427aa72fd58d66ce290a7
  Author: Niek Linnenbank <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/cubieboard.c

  Log Message:
  -----------
  hw/arm/cubieboard: use ARM Cortex-A8 as the default CPU in machine definition

The Cubieboard is a singleboard computer with an Allwinner A10 System-on-Chip 
[1].
As documented in the Allwinner A10 User Manual V1.5 [2], the SoC has an ARM
Cortex-A8 processor. Currently the Cubieboard machine definition specifies the
ARM Cortex-A9 in its description and as the default CPU.

This patch corrects the Cubieboard machine definition to use the ARM Cortex-A8.

The only user-visible effect is that our textual description of the
machine was wrong, because hw/arm/allwinner-a10.c always creates a
Cortex-A8 CPU regardless of the default value in the MachineClass struct.

 [1] http://docs.cubieboard.org/products/start#cubieboard1
 [2] https://linux-sunxi.org/File:Allwinner_A10_User_manual_V1.5.pdf

Fixes: 8a863c8120994981a099
Signed-off-by: Niek Linnenbank <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
[note in commit message that the bug didn't have much visible effect]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 17c7576263339f20d77964083704f3da4e4b8c91
      
https://github.com/qemu/qemu/commit/17c7576263339f20d77964083704f3da4e4b8c91
  Author: Niek Linnenbank <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/cubieboard.c

  Log Message:
  -----------
  hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8

The Cubieboard has an ARM Cortex-A8.  Instead of simply ignoring a
bogus -cpu option provided by the user, give them an error message so
they know their command line is wrong.

Signed-off-by: Niek Linnenbank <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e207245fc20aab00faf4d9c4c63fcc170e7a3ba7
      
https://github.com/qemu/qemu/commit/e207245fc20aab00faf4d9c4c63fcc170e7a3ba7
  Author: Niek Linnenbank <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/cubieboard.c

  Log Message:
  -----------
  hw/arm/cubieboard: restrict allowed RAM size to 512MiB and 1GiB

The Cubieboard contains either 512MiB or 1GiB of onboard RAM [1].
Prevent changing RAM to a different size which could break user programs.

 [1] http://linux-sunxi.org/Cubieboard

Signed-off-by: Niek Linnenbank <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3c2fb21ad2a02186bec986001ae1f1eefdfdb549
      
https://github.com/qemu/qemu/commit/3c2fb21ad2a02186bec986001ae1f1eefdfdb549
  Author: Niek Linnenbank <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/cubieboard.c

  Log Message:
  -----------
  hw/arm/cubieboard: report error when using unsupported -bios argument

The Cubieboard machine does not support the -bios argument.
Report an error when -bios is used and exit immediately.

Signed-off-by: Niek Linnenbank <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3e270f67f0f05277021763af119a6ce195f8ed51
      
https://github.com/qemu/qemu/commit/3e270f67f0f05277021763af119a6ce195f8ed51
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Replicate TBI/TBID bits for single range regimes

Replicate the single TBI bit from TCR_EL2 and TCR_EL3 so that
we can unconditionally use pointer bit 55 to index into our
composite TBI1:TBI0 field.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fb901c905dc34254f3edfbee86143460594c564b
      
https://github.com/qemu/qemu/commit/fb901c905dc34254f3edfbee86143460594c564b
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Optimize cpu_mmu_index

We now cache the core mmu_idx in env->hflags.  Rather than recompute
from scratch, extract the field.  All of the uses of cpu_mmu_index
within target/arm are within helpers, and env->hflags is always stable
within a translation block from whence helpers are called.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 20dc67c947a691fa9df05e76aec6df50204b4b94
      
https://github.com/qemu/qemu/commit/20dc67c947a691fa9df05e76aec6df50204b4b94
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/internals.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Introduce core_to_aa64_mmu_idx

If by context we know that we're in AArch64 mode, we need not
test for M-profile when reconstructing the full ARMMMUIdx.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d4564afe14708a09684ca417f7dc8e8c328658f5
      
https://github.com/qemu/qemu/commit/d4564afe14708a09684ca417f7dc8e8c328658f5
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper-a64.c

  Log Message:
  -----------
  target/arm: Apply TBI to ESR_ELx in helper_exception_return

We missed this case within AArch64.ExceptionReturn.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7b182eb2467af6c47c9c77c64bbbeed8ed53c330
      
https://github.com/qemu/qemu/commit/7b182eb2467af6c47c9c77c64bbbeed8ed53c330
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/helper.h
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Move helper_dc_zva to helper-a64.c

This is an aarch64-only function.  Move it out of the shared file.
This patch is code movement only.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1371b02c5a060e423e70560dbca769b54e471ba9
      
https://github.com/qemu/qemu/commit/1371b02c5a060e423e70560dbca769b54e471ba9
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/helper-a64.h

  Log Message:
  -----------
  target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva

The function does not write registers, and only reads them by
implication via the exception path.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 597d61a3b1f94c53a3aaa77671697c0c5f797dbf
      
https://github.com/qemu/qemu/commit/597d61a3b1f94c53a3aaa77671697c0c5f797dbf
  Author: Richard Henderson <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Clean address for DC ZVA

This data access was forgotten when we added support for cleaning
addresses of TBI information.

Fixes: 3a471103ac1823ba
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 55afdac3b29e672aad51e953412364127e54268b
      
https://github.com/qemu/qemu/commit/55afdac3b29e672aad51e953412364127e54268b
  Author: Peter Maydell <address@hidden>
  Date:   2020-03-05 (Thu, 05 Mar 2020)

  Changed paths:
    M hw/arm/cubieboard.c
    M hw/arm/gumstix.c
    M hw/arm/mainstone.c
    M hw/arm/musicpal.c
    M hw/arm/omap_sx1.c
    M hw/arm/pxa2xx.c
    M hw/arm/smmu-common.c
    M hw/arm/spitz.c
    M hw/arm/strongarm.c
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M hw/arm/z2.c
    M hw/timer/cadence_ttc.c
    M include/hw/arm/xlnx-versal.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/internals.h
    M target/arm/op_helper.c
    M target/arm/translate-a64.c
    M tests/tcg/aarch64/pauth-1.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200305' 
into staging

 * versal: Implement ADMA
 * Implement (trivially) ARMv8.2-TTCNP
 * hw/arm/smmu-common: a fix to smmu_find_smmu_pcibus
 * Remove unnecessary endianness-handling on some boards
 * Avoid minor memory leaks from timer_new in some devices
 * Honour more of the HCR_EL2 trap bits
 * Complain rather than ignoring bad command line options for cubieboard
 * Honour TBI for DC ZVA and exception return

# gpg: Signature made Thu 05 Mar 2020 16:30:17 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200305: (37 commits)
  target/arm: Clean address for DC ZVA
  target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva
  target/arm: Move helper_dc_zva to helper-a64.c
  target/arm: Apply TBI to ESR_ELx in helper_exception_return
  target/arm: Introduce core_to_aa64_mmu_idx
  target/arm: Optimize cpu_mmu_index
  target/arm: Replicate TBI/TBID bits for single range regimes
  hw/arm/cubieboard: report error when using unsupported -bios argument
  hw/arm/cubieboard: restrict allowed RAM size to 512MiB and 1GiB
  hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8
  hw/arm/cubieboard: use ARM Cortex-A8 as the default CPU in machine definition
  tests/tcg/aarch64: Add newline in pauth-1 printf
  target/arm: Honor the HCR_EL2.TTLB bit
  target/arm: Honor the HCR_EL2.TPU bit
  target/arm: Honor the HCR_EL2.TPCP bit
  target/arm: Honor the HCR_EL2.TACR bit
  target/arm: Honor the HCR_EL2.TSW bit
  target/arm: Honor the HCR_EL2.{TVM,TRVM} bits
  target/arm: Improve masking in arm_hcr_el2_eff
  target/arm: Remove EL2 and EL3 setup from user-only
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/af4378c39e54...55afdac3b29e
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