[Qemu-commits] [qemu/qemu] d8f6d1: hw/arm: Use TYPE_PL011 to create serial port

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d8f6d15fd580eec310a3aee9365f206871cadb8d
      
https://github.com/qemu/qemu/commit/d8f6d15fd580eec310a3aee9365f206871cadb8d
  Author: Gavin Shan <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M hw/arm/sbsa-ref.c
    M hw/arm/virt.c
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm: Use TYPE_PL011 to create serial port

This uses TYPE_PL011 when creating the serial port so that the code
looks cleaner.

Signed-off-by: Gavin Shan <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dac65ba1d7945c5d58ab63d8769103634adb2b01
      
https://github.com/qemu/qemu/commit/dac65ba1d7945c5d58ab63d8769103634adb2b01
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn

We had set this for aarch32-only in arm_max_initfn, but
failed to set the same bit for aarch64.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5df2cfbc8b61e0c5d050a69814f713d2ba045ec5
      
https://github.com/qemu/qemu/commit/5df2cfbc8b61e0c5d050a69814f713d2ba045ec5
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M hw/arm/Kconfig
    M hw/arm/integratorcp.c

  Log Message:
  -----------
  hw/arm/integratorcp: Map the audio codec controller

The Linux kernel displays errors why trying to detect the PL041
audio interface:

  Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro 
GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018
  CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00093177
  CPU: VIVT data cache, VIVT instruction cache
  OF: fdt: Machine model: ARM Integrator/CP
  ...
  OF: amba_device_add() failed (-19) for /fpga/aaci@1d000000

Since we have it already modelled, simply plug it.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 11411489da890ae40c182be7fa745c647e8ce399
      
https://github.com/qemu/qemu/commit/11411489da890ae40c182be7fa745c647e8ce399
  Author: Sai Pavan Boddu <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M include/hw/intc/arm_gic.h
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  arm_gic: Mask the un-supported priority bits

The GICv2 allows the implementation to implement a variable number
of priority bits; unimplemented bits in the priority registers
are read as zeros, writes ignored. We were previously always
implementing a full 8 bits of priority, which is allowed but not
what the real hardware typically does (which is usually to have
4 or 5 bits of priority).

Add a new device property to allow the number of implemented
property bits to be specified.

Signed-off-by: Sai Pavan Boddu <address@hidden>
Message-id: address@hidden
Suggested-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
[PMM: improved commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b3df30ad2cf8f7e313a14d5073051cf59c06e9ed
      
https://github.com/qemu/qemu/commit/b3df30ad2cf8f7e313a14d5073051cf59c06e9ed
  Author: Sai Pavan Boddu <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M hw/cpu/a9mpcore.c

  Log Message:
  -----------
  cpu/a9mpcore: Set number of GIC priority bits to 5

All A9 CPUs have a GIC with 5 bits of priority.

Signed-off-by: Sai Pavan Boddu <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Suggested-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 25f1d9f38bac040498814561714b794431af86c4
      
https://github.com/qemu/qemu/commit/25f1d9f38bac040498814561714b794431af86c4
  Author: Sai Pavan Boddu <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M hw/cpu/arm11mpcore.c

  Log Message:
  -----------
  cpu/arm11mpcore: Set number of GIC priority bits to 4

The GIC built into the ARM11MPCore is always implemented with 4
priority bits; set the GIC property accordingly.

Signed-off-by: Sai Pavan Boddu <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Suggested-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7fbc6a403a0aab834e764fa61d81ed8586cfe352
      
https://github.com/qemu/qemu/commit/7fbc6a403a0aab834e764fa61d81ed8586cfe352
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M linux-user/arm/signal.c
    M target/arm/arch_dump.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: Add isar_feature_aa32_vfp_simd

Use this in the places that were checking ARM_FEATURE_VFP, and
are obviously testing for the existance of the register set
as opposed to testing for some particular instruction extension.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c4ff873583834c8275586914fff714e3ae65dee4
      
https://github.com/qemu/qemu/commit/c4ff873583834c8275586914fff714e3ae65dee4
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/translate-vfp.inc.c

  Log Message:
  -----------
  target/arm: Rename isar_feature_aa32_fpdp_v2

The old name, isar_feature_aa32_fpdp, does not reflect
that the test includes VFPv2.  We will introduce another
feature tests for VFPv3.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f67957e17cbf8fc3cc5d1146a2db2023404578b0
      
https://github.com/qemu/qemu/commit/f67957e17cbf8fc3cc5d1146a2db2023404578b0
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}

We will shortly use these to test for VFPv2 and VFPv3
in different situations.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7d63183ff1a61b3f7934dc9b40b10e4fd5e100cd
      
https://github.com/qemu/qemu/commit/7d63183ff1a61b3f7934dc9b40b10e4fd5e100cd
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/machine.c

  Log Message:
  -----------
  target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp

We cannot easily create "any" functions for these, because the
ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero.
Which means that an aarch32-only cpu will return incorrect results
when testing the aarch64 registers.

To use these, we must either have context or additionally test
vs ARM_FEATURE_AARCH64.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 799449abda137153a0e68b8788d8e1486f389490
      
https://github.com/qemu/qemu/commit/799449abda137153a0e68b8788d8e1486f389490
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/translate-vfp.inc.c

  Log Message:
  -----------
  target/arm: Perform fpdp_v2 check first

Shuffle the order of the checks so that we test the ISA
before we test anything else, such as the register arguments.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 84774cc37f2c17e48a4867a8e8e055deb23bea69
      
https://github.com/qemu/qemu/commit/84774cc37f2c17e48a4867a8e8e055deb23bea69
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/translate-vfp.inc.c

  Log Message:
  -----------
  target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3

Sort this check to the start of a trans_* function.
Merge this with any existing test for fpdp_v2.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 82f6abe16b9b951180657c5fe15942d5214aa12e
      
https://github.com/qemu/qemu/commit/82f6abe16b9b951180657c5fe15942d5214aa12e
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/translate-vfp.inc.c

  Log Message:
  -----------
  target/arm: Add missing checks for fpsp_v2

We will eventually remove the early ARM_FEATURE_VFP test,
so add a proper test for each trans_* that does not already
have another ISA test.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c52881bbc22b50db99a6c37171ad3eea7d959ae6
      
https://github.com/qemu/qemu/commit/c52881bbc22b50db99a6c37171ad3eea7d959ae6
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac

All remaining tests for VFP4 are for fused multiply-add insns.

Since the MVFR1 field is used for both VFP and NEON, move its adjustment
from the !has_neon block to the (!has_vfp && !has_neon) block.

Test for vfp of the appropraite width alongside the test for simdfmac
within translate-vfp.inc.c.  Within disas_neon_data_insn, we have
already tested for ARM_FEATURE_NEON.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 46c98019255b056f5dbc9676a6490951469ca661
      
https://github.com/qemu/qemu/commit/46c98019255b056f5dbc9676a6490951469ca661
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn

We now have proper ISA checks within each trans_* function.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dc778a6873f534817a13257be2acba3ca87ec015
      
https://github.com/qemu/qemu/commit/dc778a6873f534817a13257be2acba3ca87ec015
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c
    M target/arm/vfp.decode

  Log Message:
  -----------
  target/arm: Move VLLDM and VLSTM to vfp.decode

Now that we no longer have an early check for ARM_FEATURE_VFP,
we can use the proper ISA check in trans_VLLDM_VLSTM.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f0f6d5c81be47d593e5ece7f06df6fba4c15738b
      
https://github.com/qemu/qemu/commit/f0f6d5c81be47d593e5ece7f06df6fba4c15738b
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Move the vfp decodetree calls next to the base isa

Have the calls adjacent as an intermediate step toward
actually merging the decodes.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bfa8a370d2f5d4ed03f7a7e2987982f15fe73758
      
https://github.com/qemu/qemu/commit/bfa8a370d2f5d4ed03f7a7e2987982f15fe73758
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP

Use isar feature tests instead of feature bit tests.

Although none of QEMUs current cpus have VFPv3 without D32,
replace the large comment explaining why with one line that
sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions.
Mirror the test sequence used in the linux kernel.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f9506e162c33e87b609549157dd8431fcc732085
      
https://github.com/qemu/qemu/commit/f9506e162c33e87b609549157dd8431fcc732085
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/kvm32.c
    M target/arm/kvm64.c

  Log Message:
  -----------
  target/arm: Remove ARM_FEATURE_VFP*

We have converted all tests against these features
to ISAR tests.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 906b60facc3d3dd3af56cb1a7860175d805e10a3
      
https://github.com/qemu/qemu/commit/906b60facc3d3dd3af56cb1a7860175d805e10a3
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/vfp.decode

  Log Message:
  -----------
  target/arm: Add formats for some vfp 2 and 3-register insns

Those vfp instructions without extra opcode fields can
share a common @format for brevity.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d486f8308a13543bbcc4887f246e856df991a4bc
      
https://github.com/qemu/qemu/commit/d486f8308a13543bbcc4887f246e856df991a4bc
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/translate-vfp.inc.c
    M target/arm/vfp.decode

  Log Message:
  -----------
  target/arm: Split VFM decode

Passing the raw o1 and o2 fields from the manual is less
instructive than it might be.  Do the full decode and let
the trans_* functions pass in booleans to a helper.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f2eafb75511e5d2ee601b43dc6ee0bcc6e453acd
      
https://github.com/qemu/qemu/commit/f2eafb75511e5d2ee601b43dc6ee0bcc6e453acd
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/translate-vfp.inc.c
    M target/arm/vfp-uncond.decode

  Log Message:
  -----------
  target/arm: Split VMINMAXNM decode

Passing the raw op field from the manual is less instructive
than it might be.  Do the full decode and use the existing
helpers to perform the expansion.

Since these are v8 insns, VECLEN+VECSTRIDE are already RES0.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 616ec12d0fcc49f916dc0ab3f778fdeb87a53cd9
      
https://github.com/qemu/qemu/commit/616ec12d0fcc49f916dc0ab3f778fdeb87a53cd9
  Author: Guenter Roeck <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M hw/arm/xilinx_zynq.c

  Log Message:
  -----------
  hw/arm/xilinx_zynq: Fix USB port instantiation

USB ports on Xilinx Zync must be instantiated as TYPE_CHIPIDEA to work.
Linux expects and checks various chipidea registers, which do not exist
with the basic ehci emulation. This patch series fixes the problem.

Without this patch, USB ports fail to instantiate under Linux.

ci_hdrc ci_hdrc.0: doesn't support host
ci_hdrc ci_hdrc.0: no supported roles

With this patch, USB ports are instantiated, and it is possible
to boot from USB drive.

ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
usb 1-1: new full-speed USB device number 2 using ci_hdrc
usb 1-1: not running at top speed; connect to a high speed hub
usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x81 has invalid maxpacket 
512, setting to 64
usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x2 has invalid maxpacket 
512, setting to 64
usb-storage 1-1:1.0: USB Mass Storage device detected
scsi host0: usb-storage 1-1:1.0

Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: Gerd Hoffmann <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f9c0a55da6ed2448bc4f95846fe3ecfad27cd143
      
https://github.com/qemu/qemu/commit/f9c0a55da6ed2448bc4f95846fe3ecfad27cd143
  Author: Guenter Roeck <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M hw/usb/hcd-ehci-sysbus.c

  Log Message:
  -----------
  hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class

Xilinx USB devices are now instantiated through TYPE_CHIPIDEA,
and xlnx support in the EHCI code is no longer needed.

Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: Gerd Hoffmann <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 050a82f0c5bc1ea21198c98780f04c043aabeca3
      
https://github.com/qemu/qemu/commit/050a82f0c5bc1ea21198c98780f04c043aabeca3
  Author: Thomas Huth <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M MAINTAINERS
    A tests/acceptance/machine_arm_n8x0.py

  Log Message:
  -----------
  tests/acceptance: Add a test for the N800 and N810 arm machines

Old kernels from the Meego project can be used to check that Linux
is at least starting on these machines.

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Wainer dos Santos Moschetta <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5e0ac7e0694c54cd99b4fe92426184a22b4f1e11
      
https://github.com/qemu/qemu/commit/5e0ac7e0694c54cd99b4fe92426184a22b4f1e11
  Author: Thomas Huth <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M MAINTAINERS
    A tests/acceptance/machine_arm_integratorcp.py

  Log Message:
  -----------
  tests/acceptance: Add a test for the integratorcp arm machine

There is a kernel and initrd available on github which we can use
for testing this machine.

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Wainer dos Santos Moschetta <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
[PMD: Renamed test method, moved description from class to method]
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 595f1acaa4f04197cd0c25eb7ca22102c4e217fb
      
https://github.com/qemu/qemu/commit/595f1acaa4f04197cd0c25eb7ca22102c4e217fb
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M tests/acceptance/machine_arm_integratorcp.py

  Log Message:
  -----------
  tests/acceptance: Extract boot_integratorcp() from test_integratorcp()

As we want to re-use this code, extract it as a new function.
Since we are using the PL011 serial console, add a Avocado tag
to ease filtering of tests.

Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Wainer dos Santos Moschetta <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 15b1bdca1e0ffb549a63493ecf296f727b5c95e2
      
https://github.com/qemu/qemu/commit/15b1bdca1e0ffb549a63493ecf296f727b5c95e2
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M tests/acceptance/machine_arm_integratorcp.py

  Log Message:
  -----------
  tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer

Add a test that verifies the Tux logo is displayed on the framebuffer.

We simply follow the OpenCV "Template Matching with Multiple Objects"
tutorial, replacing Lionel Messi by Tux:
https://docs.opencv.org/4.2.0/d4/dc6/tutorial_py_template_matching.html

When OpenCV and NumPy are installed, this test can be run using:

  $ AVOCADO_ALLOW_UNTRUSTED_CODE=hmmm \
    avocado --show=app,framebuffer run -t device:framebuffer \
      tests/acceptance/machine_arm_integratorcp.py
  JOB ID     : 8c46b0f8269242e87d738247883ea2a470df949e
  JOB LOG    : avocado/job-results/job-2020-01-31T21.38-8c46b0f/job.log
   (1/1) 
tests/acceptance/machine_arm_integratorcp.py:IntegratorMachine.test_framebuffer_tux_logo:
  framebuffer: found Tux at position [x, y] = (0, 0)
  PASS (3.96 s)
  RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | 
CANCEL 0
  JOB TIME   : 4.23 s

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Wainer dos Santos Moschetta <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 54117b90ffd8a3977917971c3bd99bb5242710d9
      
https://github.com/qemu/qemu/commit/54117b90ffd8a3977917971c3bd99bb5242710d9
  Author: Peter Maydell <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0

We missed an instance of using FIELD_EX32 on a 64-bit ID
register, in isar_feature_aa64_pmu_8_4(). Fix it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 2677cf9f92a5319bb995927f9225940414ce879d
      
https://github.com/qemu/qemu/commit/2677cf9f92a5319bb995927f9225940414ce879d
  Author: Peter Maydell <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M linux-user/elfload.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement v8.3-RCPC

The v8.3-RCPC extension implements three new load instructions
which provide slightly weaker consistency guarantees than the
existing load-acquire operations. For QEMU we choose to simply
implement them with a full LDAQ barrier.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: a1229109dec4375259d3fff99f362405aab7917a
      
https://github.com/qemu/qemu/commit/a1229109dec4375259d3fff99f362405aab7917a
  Author: Peter Maydell <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M linux-user/elfload.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement v8.4-RCPC

The v8.4-RCPC extension implements some new instructions:
 * LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW
 * STLUR, STLURB, STLURH

These are all in a new subgroup of encodings that sits below the
top-level "Loads and Stores" group in the Arm ARM.

The STLUR* instructions have standard store-release semantics; the
LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose
to implement them as the slightly stronger Load-Acquire.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 957e615503bd0de22393fd8dbcb22a5064fd2b5c
      
https://github.com/qemu/qemu/commit/957e615503bd0de22393fd8dbcb22a5064fd2b5c
  Author: Peter Maydell <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement ARMv8.3-CCIDX

The ARMv8.3-CCIDX extension makes the CCSIDR_EL1 system ID registers
have a format that uses the full 64 bit width of the register, and
adds a new CCSIDR2 register so AArch32 can get at the high 32 bits.

QEMU doesn't implement caches, so we just treat these ID registers as
opaque values that are set to the correct constant values for each
CPU.  The only thing we need to do is allow 64-bit values in our
cssidr[] array and provide the CCSIDR2 accessors.

We don't set the CCIDX field in our 'max' CPU because the CCSIDR
constant values we use are the same as the ones used by the
Cortex-A57 and they are in the old 32-bit format. This means
that the extra regdef added here is unused currently, but it
means that whenever in the future we add a CPU that does need
the new 64-bit format it will just work when we set the cssidr
values and the ID registers for it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 1904f9b5f1d94fe12fe021db6b504c87d684f6db
      
https://github.com/qemu/qemu/commit/1904f9b5f1d94fe12fe021db6b504c87d684f6db
  Author: Peter Maydell <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M hw/intc/arm_gic_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2

In our KVM GICv2 realize function, we try to cope with old kernels
that don't provide the device control API (KVM_CAP_DEVICE_CTRL): we
try to use the device control, and if that fails we fall back to
assuming that the kernel has the old style KVM_CREATE_IRQCHIP and
that it will provide a GICv2.

This doesn't cater for the possibility of a kernel and hardware which
only provide a GICv3, which is very common now.  On that setup we
will abort() later on in kvm_arm_pmu_set_irq() when we try to wire up
an interrupt to the GIC we failed to create:

qemu-system-aarch64: PMU: KVM_SET_DEVICE_ATTR: Invalid argument
qemu-system-aarch64: failed to set irq for PMU
Aborted

If the kernel advertises KVM_CAP_DEVICE_CTRL we should trust it if it
says it can't create a GICv2, rather than assuming it has one.  We
can then produce a more helpful error message including a hint about
the most probable reason for the failure.

If the kernel doesn't advertise KVM_CAP_DEVICE_CTRL then it is truly
ancient by this point but we might as well still fall back to a
KVM_CREATE_IRQCHIP GICv2.

With this patch then the user misconfiguration which previously
caused an abort now prints:
qemu-system-aarch64: Initialization of device kvm-arm-gic failed: error 
creating in-kernel VGIC: No such device
Perhaps the host CPU does not support GICv2?

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Tested-by: Andrew Jones <address@hidden>
Message-id: address@hidden


  Commit: e0175b71638cf4398903c0d25f93fe62e0606389
      
https://github.com/qemu/qemu/commit/e0175b71638cf4398903c0d25f93fe62e0606389
  Author: Peter Maydell <address@hidden>
  Date:   2020-02-28 (Fri, 28 Feb 2020)

  Changed paths:
    M MAINTAINERS
    M hw/arm/Kconfig
    M hw/arm/integratorcp.c
    M hw/arm/sbsa-ref.c
    M hw/arm/virt.c
    M hw/arm/xilinx_zynq.c
    M hw/arm/xlnx-versal.c
    M hw/cpu/a9mpcore.c
    M hw/cpu/arm11mpcore.c
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M hw/intc/arm_gic_kvm.c
    M hw/intc/armv7m_nvic.c
    M hw/usb/hcd-ehci-sysbus.c
    M include/hw/intc/arm_gic.h
    M include/hw/intc/arm_gic_common.h
    M linux-user/arm/signal.c
    M linux-user/elfload.c
    M target/arm/arch_dump.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/kvm32.c
    M target/arm/kvm64.c
    M target/arm/m_helper.c
    M target/arm/machine.c
    M target/arm/translate-a64.c
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c
    M target/arm/vfp-uncond.decode
    M target/arm/vfp.decode
    A tests/acceptance/machine_arm_integratorcp.py
    A tests/acceptance/machine_arm_n8x0.py

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200228' 
into staging

target-arm queue:
 * hw/arm: Use TYPE_PL011 to create serial port
 * target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn
 * hw/arm/integratorcp: Map the audio codec controller
 * GICv2: Correctly implement the limited number of priority bits
 * target/arm: refactoring of VFP related feature checks and decode
 * xilinx_zynq: Fix USB port instantiation
 * acceptance tests for n800, n810, integratorcp
 * Implement v8.3-RCPC, v8.4-RCPC, v8.3-CCIDX
 * arm_gic_kvm: Don't assume kernel can provide a GICv2
   (provide better error message for user error)

# gpg: Signature made Fri 28 Feb 2020 16:38:04 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200228: (33 commits)
  hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2
  target/arm: Implement ARMv8.3-CCIDX
  target/arm: Implement v8.4-RCPC
  target/arm: Implement v8.3-RCPC
  target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0
  tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer
  tests/acceptance: Extract boot_integratorcp() from test_integratorcp()
  tests/acceptance: Add a test for the integratorcp arm machine
  tests/acceptance: Add a test for the N800 and N810 arm machines
  hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class
  hw/arm/xilinx_zynq: Fix USB port instantiation
  target/arm: Split VMINMAXNM decode
  target/arm: Split VFM decode
  target/arm: Add formats for some vfp 2 and 3-register insns
  target/arm: Remove ARM_FEATURE_VFP*
  linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP
  target/arm: Move the vfp decodetree calls next to the base isa
  target/arm: Move VLLDM and VLSTM to vfp.decode
  target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn
  target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e27d5b488ef0...e0175b71638c