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[Qemu-commits] [qemu/qemu] c7e1f5: aspeed/scu: Create separate write cal
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] c7e1f5: aspeed/scu: Create separate write callbacks |
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Date: |
Fri, 21 Feb 2020 09:00:15 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: c7e1f57291f3bff7d369034b324f9671090567bb
https://github.com/qemu/qemu/commit/c7e1f57291f3bff7d369034b324f9671090567bb
Author: Joel Stanley <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/misc/aspeed_scu.c
Log Message:
-----------
aspeed/scu: Create separate write callbacks
This splits the common write callback into separate ast2400 and ast2500
implementations. This makes it clearer when implementing differing
behaviour.
Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7ffe647f52f85748b8d1d3a8dbebd742e0231bdc
https://github.com/qemu/qemu/commit/7ffe647f52f85748b8d1d3a8dbebd742e0231bdc
Author: Joel Stanley <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/misc/aspeed_scu.c
Log Message:
-----------
aspeed/scu: Implement chip ID register
This returns a fixed but non-zero value for the chip id.
Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9df7401b80e7b19789aa625d77fe79c1f48b4b84
https://github.com/qemu/qemu/commit/9df7401b80e7b19789aa625d77fe79c1f48b4b84
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/misc/iotkit-secctl.c
Log Message:
-----------
hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
Fix warning reported by Clang static code analyzer:
CC hw/misc/iotkit-secctl.o
hw/misc/iotkit-secctl.c:343:9: warning: Value stored to 'value' is never read
value &= 0x00f000f3;
^ ~~~~~~~~~~
Fixes: b3717c23e1c
Reported-by: Clang Static Analyzer
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: d4cf262ab5b057dff0dff86e90de9b1b8a32b307
https://github.com/qemu/qemu/commit/d4cf262ab5b057dff0dff86e90de9b1b8a32b307
Author: Guenter Roeck <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/arm/mainstone.c
Log Message:
-----------
mainstone: Make providing flash images non-mandatory
Up to now, the mainstone machine only boots if two flash images are
provided. This is not really necessary; the machine can boot from initrd
or from SD without it. At the same time, having to provide dummy flash
images is a nuisance and does not add any real value. Make it optional.
Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9e946eaba87916c43aaf0b2760bd5d5a54187c7b
https://github.com/qemu/qemu/commit/9e946eaba87916c43aaf0b2760bd5d5a54187c7b
Author: Guenter Roeck <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/arm/z2.c
Log Message:
-----------
z2: Make providing flash images non-mandatory
Up to now, the z2 machine only boots if a flash image is provided.
This is not really necessary; the machine can boot from initrd or from
SD without it. At the same time, having to provide dummy flash images
is a nuisance and does not add any real value. Make it optional.
Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 78cedfabd53b6f64e7e64fc84878d848e5df1d08
https://github.com/qemu/qemu/commit/78cedfabd53b6f64e7e64fc84878d848e5df1d08
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Flush high bits of sve register after AdvSIMD EXT
Writes to AdvSIMD registers flush the bits above 128.
Buglink: https://bugs.launchpad.net/bugs/1863247
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 263273bc988e677ebadeaf7d0e49f6792a112db5
https://github.com/qemu/qemu/commit/263273bc988e677ebadeaf7d0e49f6792a112db5
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
Writes to AdvSIMD registers flush the bits above 128.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 33649de62e40df0060a1c514574e4ef25c4e52e1
https://github.com/qemu/qemu/commit/33649de62e40df0060a1c514574e4ef25c4e52e1
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
Writes to AdvSIMD registers flush the bits above 128.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 528dc354b6f3aa82d65141cc60bc0e725e6cae98
https://github.com/qemu/qemu/commit/528dc354b6f3aa82d65141cc60bc0e725e6cae98
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Flush high bits of sve register after AdvSIMD INS
Writes to AdvSIMD registers flush the bits above 128.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7eeb4c2ce8dc0a5655526f3f39bd5d6cc02efb39
https://github.com/qemu/qemu/commit/7eeb4c2ce8dc0a5655526f3f39bd5d6cc02efb39
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/pauth_helper.c
Log Message:
-----------
target/arm: Use bit 55 explicitly for pauth
The psuedocode in aarch64/functions/pac/auth/Auth and
aarch64/functions/pac/strip/Strip always uses bit 55 for
extfield and do not consider if the current regime has 2 ranges.
Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 71d181640a1a9470f074fa28600ca85587e2ca6b
https://github.com/qemu/qemu/commit/71d181640a1a9470f074fa28600ca85587e2ca6b
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix select for aa64_va_parameters_both
Select should always be 0 for a regime with one range.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 03f27724dff15633911e68a3906c30f57938ea45
https://github.com/qemu/qemu/commit/03f27724dff15633911e68a3906c30f57938ea45
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Remove ttbr1_valid check from get_phys_addr_lpae
Now that aa64_va_parameters_both sets select based on the number
of ranges in the regime, the ttbr1_valid check is redundant.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: b830a5ee82e66f54697dcc6450fe9239b7412d13
https://github.com/qemu/qemu/commit/b830a5ee82e66f54697dcc6450fe9239b7412d13
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid
For the purpose of rebuild_hflags_a64, we do not need to compute
all of the va parameters, only tbi. Moreover, we can compute them
in a form that is more useful to storing in hflags.
This eliminates the need for aa64_va_parameter_both, so fold that
in to aa64_va_parameter. The remaining calls to aa64_va_parameter
are in get_phys_addr_lpae and in pauth_helper.c.
This reduces the total cpu consumption of aa64_va_parameter in a
kernel boot plus a kvm guest kernel boot from 3% to 0.5%.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 873b73c0c891ec20adacc7bd1ae789294334d675
https://github.com/qemu/qemu/commit/873b73c0c891ec20adacc7bd1ae789294334d675
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M linux-user/elfload.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate.c
Log Message:
-----------
target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers
Enforce a convention that an isar_feature function that tests a
32-bit ID register always has _aa32_ in its name, and one that
tests a 64-bit ID register always has _aa64_ in its name.
We already follow this except for three cases: thumb_div,
arm_div and jazelle, which all need _aa32_ adding.
(As noted in the comment, isar_feature_aa32_fp16_arith()
is an exception in that it currently tests ID_AA64PFR0_EL1,
but will switch to MVFR1 once we've properly implemented
FP16 for AArch32.)
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: f8af1143ef93954e77cf59e09b5e004dafbd64fd
https://github.com/qemu/qemu/commit/f8af1143ef93954e77cf59e09b5e004dafbd64fd
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan
In take_aarch32_exception(), we know we are dealing with a CPU that
has AArch32, so the right isar_feature test is aa32_pan, not aa64_pan.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 6e61f8391cc6cb0846d4bf078dbd935c2aeebff5
https://github.com/qemu/qemu/commit/6e61f8391cc6cb0846d4bf078dbd935c2aeebff5
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Add isar_feature_any_fp16 and document naming/usage conventions
Our current usage of the isar_feature feature tests almost always
uses an _aa32_ test when the code path is known to be AArch32
specific and an _aa64_ test when the code path is known to be
AArch64 specific. There is just one exception: in the vfp_set_fpscr
helper we check aa64_fp16 to determine whether the FZ16 bit in
the FP(S)CR exists, but this code is also used for AArch32.
There are other places in future where we're likely to want
a general "does this feature exist for either AArch32 or
AArch64" check (typically where architecturally the feature exists
for both CPU states if it exists at all, but the CPU might be
AArch32-only or AArch64-only, and so only have one set of ID
registers).
Introduce a new category of isar_feature_* functions:
isar_feature_any_foo() should be tested when what we want to
know is "does this feature exist for either AArch32 or AArch64",
and always returns the logical OR of isar_feature_aa32_foo()
and isar_feature_aa64_foo().
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 22e570730d15374453baa73ff2a699e01ef4e950
https://github.com/qemu/qemu/commit/22e570730d15374453baa73ff2a699e01ef4e950
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Define and use any_predinv isar_feature test
Instead of open-coding "ARM_FEATURE_AARCH64 ? aa64_predinv: aa32_predinv",
define and use an any_predinv isar_feature test function.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 24183fb6f00ecca8b508e245c95ff50ddde3f18b
https://github.com/qemu/qemu/commit/24183fb6f00ecca8b508e245c95ff50ddde3f18b
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Factor out PMU register definitions
Pull the code that defines the various PMU registers out
into its own function, matching the pattern we have
already for the debug registers.
Apart from one style fix to a multi-line comment, this
is purely movement of code with no changes to it.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: ceb2744b47a1ef4184dca56a158eb3156b6eba36
https://github.com/qemu/qemu/commit/ceb2744b47a1ef4184dca56a158eb3156b6eba36
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them
where we currently have hard-coded bit values.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: d52c061e541982a3663ad5c65bd3b518dbe85b87
https://github.com/qemu/qemu/commit/d52c061e541982a3663ad5c65bd3b518dbe85b87
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
We already define FIELD macros for ID_DFR0, so use them in the
one place where we're doing direct bit value manipulation.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: a617953855b65a602d36364b9643f7e5bc31288e
https://github.com/qemu/qemu/commit/a617953855b65a602d36364b9643f7e5bc31288e
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Define an aa32_pmu_8_1 isar feature test function
Instead of open-coding a check on the ID_DFR0 PerfMon ID register
field, create a standardly-named isar_feature for "does AArch32 have
a v8.1 PMUv3" and use it.
This entails moving the id_dfr0 field into the ARMISARegisters struct.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 2a609df87d9b886fd38a190a754dbc241ff707e8
https://github.com/qemu/qemu/commit/2a609df87d9b886fd38a190a754dbc241ff707e8
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks
Add the 64-bit version of the "is this a v8.1 PMUv3?"
ID register check function, and the _any_ version that
checks for either AArch32 or AArch64 support. We'll use
this in a later commit.
We don't (yet) do any isar_feature checks on ID_AA64DFR1_EL1,
but we move id_aa64dfr1 into the ARMISARegisters struct with
id_aa64dfr0, for consistency.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 88ce6c6ee85d902f59dc65afc3ca86b34f02b9ed
https://github.com/qemu/qemu/commit/88ce6c6ee85d902f59dc65afc3ca86b34f02b9ed
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/debug_helper.c
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Stop assuming DBGDIDR always exists
The AArch32 DBGDIDR defines properties like the number of
breakpoints, watchpoints and context-matching comparators. On an
AArch64 CPU, the register may not even exist if AArch32 is not
supported at EL1.
Currently we hard-code use of DBGDIDR to identify the number of
breakpoints etc; this works for all our TCG CPUs, but will break if
we ever add an AArch64-only CPU. We also have an assert() that the
AArch32 and AArch64 registers match, which currently works only by
luck for KVM because we don't populate either of these ID registers
from the KVM vCPU and so they are both zero.
Clean this up so we have functions for finding the number
of breakpoints, watchpoints and context comparators which look
in the appropriate ID register.
This allows us to drop the "check that AArch64 and AArch32 agree
on the number of breakpoints etc" asserts:
* we no longer look at the AArch32 versions unless that's the
right place to be looking
* it's valid to have a CPU (eg AArch64-only) where they don't match
* we shouldn't have been asserting the validity of ID registers
in a codepath used with KVM anyway
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 4426d3617d64922d97b74ed22e67e33b6fb7de0a
https://github.com/qemu/qemu/commit/4426d3617d64922d97b74ed22e67e33b6fb7de0a
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Move DBGDIDR into ARMISARegisters
We're going to want to read the DBGDIDR register from KVM in
a subsequent commit, which means it needs to be in the
ARMISARegisters sub-struct. Move it.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 1548a7b2ad621a31b4216ed703b6d658a2ecf0d0
https://github.com/qemu/qemu/commit/1548a7b2ad621a31b4216ed703b6d658a2ecf0d0
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/kvm32.c
M target/arm/kvm64.c
Log Message:
-----------
target/arm: Read debug-related ID registers from KVM
Now we have isar_feature test functions that look at fields in the
ID_AA64DFR0_EL1 and ID_DFR0 ID registers, add the code that reads
these register values from KVM so that the checks behave correctly
when we're using KVM.
No isar_feature function tests ID_AA64DFR1_EL1 or DBGDIDR yet, but we
add it to maintain the invariant that every field in the
ARMISARegisters struct is populated for a KVM CPU and can be relied
on. This requirement isn't actually written down yet, so add a note
to the relevant comment.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 0727f63b1ecf765ebc48266f616f8fc362dc7fbc
https://github.com/qemu/qemu/commit/0727f63b1ecf765ebc48266f616f8fc362dc7fbc
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement ARMv8.1-PMU extension
The ARMv8.1-PMU extension requires:
* the evtCount field in PMETYPER<n>_EL0 is 16 bits, not 10
* MDCR_EL2.HPMD allows event counting to be disabled at EL2
* two new required events, STALL_FRONTEND and STALL_BACKEND
* ID register bits in ID_AA64DFR0_EL1 and ID_DFR0
We already implement the 16-bit evtCount field and the
HPMD bit, so all that is missing is the two new events:
STALL_FRONTEND
"counts every cycle counted by the CPU_CYCLES event on which no
operation was issued because there are no operations available
to issue to this PE from the frontend"
STALL_BACKEND
"counts every cycle counted by the CPU_CYCLES event on which no
operation was issued because the backend is unable to accept
any available operations from the frontend"
QEMU never stalls in this sense, so our implementation is trivial:
always return a zero count.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 15dd1ebda4a6ef928d484c5a4f48b8ccb7438bb2
https://github.com/qemu/qemu/commit/15dd1ebda4a6ef928d484c5a4f48b8ccb7438bb2
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement ARMv8.4-PMU extension
The ARMv8.4-PMU extension adds:
* one new required event, STALL
* one new system register PMMIR_EL1
(There are also some more L1-cache related events, but since
we don't implement any cache we don't provide these, in the
same way we don't provide the base-PMUv3 cache events.)
The STALL event "counts every attributable cycle on which no
attributable instruction or operation was sent for execution on this
PE". QEMU doesn't stall in this sense, so this is another
always-reads-zero event.
The PMMIR_EL1 register is a read-only register providing
implementation-specific information about the PMU; currently it has
only one field, SLOTS, which defines behaviour of the STALL_SLOT PMU
event. Since QEMU doesn't implement the STALL_SLOT event, we can
validly make the register read zero.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 3bec78447a958d4819911252e056f29740ac25e4
https://github.com/qemu/qemu/commit/3bec78447a958d4819911252e056f29740ac25e4
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Provide ARMv8.4-PMU in '-cpu max'
Set the ID register bits to provide ARMv8.4-PMU (and implicitly
also ARMv8.1-PMU) in the 'max' CPU.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: a1ed04dd79aabb9dbeeb5fa7d49f1a3de0357553
https://github.com/qemu/qemu/commit/a1ed04dd79aabb9dbeeb5fa7d49f1a3de0357553
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Correct definition of PMCRDP
The PMCR_EL0.DP bit is bit 5, which is 0x20, not 0x10. 0x10 is 'X'.
Correct our #define of PMCRDP and add the missing PMCRX.
We do have the correct behaviour for handling the DP bit being
set, so this fixes a guest-visible bug.
Fixes: 033614c47de
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 62d96ff48510f4bf648ad12f5d3a5507227b026f
https://github.com/qemu/qemu/commit/62d96ff48510f4bf648ad12f5d3a5507227b026f
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Correct handling of PMCR_EL0.LC bit
The LC bit in the PMCR_EL0 register is supposed to be:
* read/write
* RES1 on an AArch64-only implementation
* an architecturally UNKNOWN value on reset
(and use of LC==0 by software is deprecated).
We were implementing it incorrectly as read-only always zero,
though we do have all the code needed to test it and behave
accordingly.
Instead make it a read-write bit which resets to 1 always, which
satisfies all the architectural requirements above.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 10054016eda1b13bdd8340d100fd029cc8b58f36
https://github.com/qemu/qemu/commit/10054016eda1b13bdd8340d100fd029cc8b58f36
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/kvm32.c
M target/arm/kvm64.c
Log Message:
-----------
target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions
are supposed to be testing fields in ID_MMFR3; but a cut-and-paste
error meant we were looking at MVFR0 instead.
Fix the functions to look at the right register; this requires
us to move at least id_mmfr3 to the ARMISARegisters struct; we
choose to move all the ID_MMFRn registers for consistency.
Fixes: 3d6ad6bb466f
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 4036b7d1cd9fb1097a5f4bc24d7d31744256260f
https://github.com/qemu/qemu/commit/4036b7d1cd9fb1097a5f4bc24d7d31744256260f
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Use isar_feature function for testing AA32HPD feature
Now we have moved ID_MMFR4 into the ARMISARegisters struct, we
can define and use an isar_feature for the presence of the
ARMv8.2-AA32HPD feature, rather than open-coding the test.
While we're here, correct a comment typo which missed an 'A'
from the feature name.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: b3a816f6ce1ec184ab6072f50bbe4479fc5116c3
https://github.com/qemu/qemu/commit/b3a816f6ce1ec184ab6072f50bbe4479fc5116c3
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Use FIELD_EX32 for testing 32-bit fields
Cut-and-paste errors mean we're using FIELD_EX64() to extract fields from
some 32-bit ID register fields. Use FIELD_EX32() instead. (This makes
no difference in behaviour, it's just more consistent.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: f6287c24c66d6b9187c1c2887e1c7cfa4d304b0c
https://github.com/qemu/qemu/commit/f6287c24c66d6b9187c1c2887e1c7cfa4d304b0c
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Correctly implement ACTLR2, HACTLR2
The ACTLR2 and HACTLR2 AArch32 system registers didn't exist in ARMv7
or the original ARMv8. They were later added as optional registers,
whose presence is signaled by the ID_MMFR4.AC2 field. From ARMv8.2
they are mandatory (ie ID_MMFR4.AC2 must be non-zero).
We implemented HACTLR2 in commit 0e0456ab8895a5e85, but we
incorrectly made it exist for all v8 CPUs, and we didn't implement
ACTLR2 at all.
Sort this out by implementing both registers only when they are
supposed to exist, and setting the ID_MMFR4 bit for -cpu max.
Note that this removes HACTLR2 from our Cortex-A53, -A47 and -A72
CPU models; this is correct, because those CPUs do not implement
this register.
Fixes: 0e0456ab8895a5e85
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: fbec359e9279ce78908b9f2af2c264e7448336af
https://github.com/qemu/qemu/commit/fbec359e9279ce78908b9f2af2c264e7448336af
Author: Guenter Roeck <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/usb/hcd-ohci.c
M hw/usb/hcd-ohci.h
Log Message:
-----------
hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file
We need to be able to use OHCISysBusState outside hcd-ohci.c, so move it
to its include file.
Reviewed-by: Gerd Hoffmann <address@hidden>
Signed-off-by: Guenter Roeck <address@hidden>
Tested-by: Niek Linnenbank <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: eb271ae58116863b22c02582788f841a7848e1af
https://github.com/qemu/qemu/commit/eb271ae58116863b22c02582788f841a7848e1af
Author: Guenter Roeck <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/usb/hcd-ehci-sysbus.c
Log Message:
-----------
hcd-ehci: Introduce "companion-enable" sysbus property
We'll use this property in a follow-up patch to insantiate an EHCI
bus with companion support.
Reviewed-by: Gerd Hoffmann <address@hidden>
Signed-off-by: Guenter Roeck <address@hidden>
Tested-by: Niek Linnenbank <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7abc8cabad977aeccbbb6e6b2026e68ab8e32c65
https://github.com/qemu/qemu/commit/7abc8cabad977aeccbbb6e6b2026e68ab8e32c65
Author: Guenter Roeck <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/arm/allwinner-a10.c
M include/hw/arm/allwinner-a10.h
Log Message:
-----------
arm: allwinner: Wire up USB ports
Instantiate EHCI and OHCI controllers on Allwinner A10. OHCI ports are
modeled as companions of the respective EHCI ports.
With this patch applied, USB controllers are discovered and instantiated
when booting the cubieboard machine with a recent Linux kernel.
ehci-platform 1c14000.usb: EHCI Host Controller
ehci-platform 1c14000.usb: new USB bus registered, assigned bus number 1
ehci-platform 1c14000.usb: irq 26, io mem 0x01c14000
ehci-platform 1c14000.usb: USB 2.0 started, EHCI 1.00
ehci-platform 1c1c000.usb: EHCI Host Controller
ehci-platform 1c1c000.usb: new USB bus registered, assigned bus number 2
ehci-platform 1c1c000.usb: irq 31, io mem 0x01c1c000
ehci-platform 1c1c000.usb: USB 2.0 started, EHCI 1.00
ohci-platform 1c14400.usb: Generic Platform OHCI controller
ohci-platform 1c14400.usb: new USB bus registered, assigned bus number 3
ohci-platform 1c14400.usb: irq 27, io mem 0x01c14400
ohci-platform 1c1c400.usb: Generic Platform OHCI controller
ohci-platform 1c1c400.usb: new USB bus registered, assigned bus number 4
ohci-platform 1c1c400.usb: irq 32, io mem 0x01c1c400
usb 2-1: new high-speed USB device number 2 using ehci-platform
usb-storage 2-1:1.0: USB Mass Storage device detected
scsi host1: usb-storage 2-1:1.0
usb 3-1: new full-speed USB device number 2 using ohci-platform
input: QEMU QEMU USB Mouse as
/devices/platform/soc/1c14400.usb/usb3/3-1/3-1:1.0/0003:0627:0001.0001/input/input0
Reviewed-by: Gerd Hoffmann <address@hidden>
Signed-off-by: Guenter Roeck <address@hidden>
Tested-by: Niek Linnenbank <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 87b74e8b6edd287ea2160caa0ebea725fa8f1ca1
https://github.com/qemu/qemu/commit/87b74e8b6edd287ea2160caa0ebea725fa8f1ca1
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper.h
M target/arm/neon_helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/translate.h
M target/arm/vec_helper.c
Log Message:
-----------
target/arm: Vectorize USHL and SSHL
These instructions shift left or right depending on the sign
of the input, and 7 bits are significant to the shift. This
requires several masks and selects in addition to the actual
shifts to form the complete answer.
That said, the operation is still a small improvement even for
two 64-bit elements -- 13 vector operations instead of 2 * 7
integer operations.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: a21bb78e5817be3f494922e1dadd6455fe5d6318
https://github.com/qemu/qemu/commit/a21bb78e5817be3f494922e1dadd6455fe5d6318
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper.h
M target/arm/neon_helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/vec_helper.c
Log Message:
-----------
target/arm: Convert PMUL.8 to gvec
The gvec form will be needed for implementing SVE2.
Extend the implementation to operate on uint64_t instead of uint32_t.
Use a counted inner loop instead of terminating when op1 goes to zero,
looking toward the required implementation for ARMv8.4-DIT.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b9ed510e46f2f9e31e5e8adb4661d5d1cbe9a459
https://github.com/qemu/qemu/commit/b9ed510e46f2f9e31e5e8adb4661d5d1cbe9a459
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper.h
M target/arm/neon_helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/vec_helper.c
Log Message:
-----------
target/arm: Convert PMULL.64 to gvec
The gvec form will be needed for implementing SVE2.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e7e96fc5ec8c79dc77fef522d5226ac09f684ba5
https://github.com/qemu/qemu/commit/e7e96fc5ec8c79dc77fef522d5226ac09f684ba5
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/helper-sve.h
M target/arm/helper.h
M target/arm/neon_helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/vec_helper.c
Log Message:
-----------
target/arm: Convert PMULL.8 to gvec
We still need two different helpers, since NEON and SVE2 get the
inputs from different locations within the source vector. However,
we can convert both to the same internal form for computation.
The sve2 helper is not used yet, but adding it with this patch
helps illustrate why the neon changes are helpful.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 33e2c4d8d3ff99af2280706dee5ce3385b78ff6d
https://github.com/qemu/qemu/commit/33e2c4d8d3ff99af2280706dee5ce3385b78ff6d
Author: Francisco Iglesias <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/ssi/xilinx_spips.c
Log Message:
-----------
xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
Correct the number of dummy cycles required by the FAST_READ_4 command (to
be eight, one dummy byte).
Fixes: ef06ca3946 ("xilinx_spips: Add support for RX discard and RX drain")
Suggested-by: Cédric Le Goater <address@hidden>
Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 47d2d36cd84c88f6c72f7800aa9201c45789a2c2
https://github.com/qemu/qemu/commit/47d2d36cd84c88f6c72f7800aa9201c45789a2c2
Author: Guenter Roeck <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/sh4/sh_pci.c
Log Message:
-----------
sh4: Fix PCI ISA IO memory subregion
Booting the r2d machine from flash fails because flash is not discovered.
Looking at the flattened memory tree, we see the following.
FlatView #1
AS "memory", root: system
AS "cpu-memory-0", root: system
AS "sh_pci_host", root: bus master container
Root memory region: system
0000000000000000-000000000000ffff (prio 0, i/o): io
0000000000010000-0000000000ffffff (prio 0, i/o): r2d.flash @0000000000010000
The overlapping memory region is sh_pci.isa, ie the ISA I/O region bridge.
This region is initially assigned to address 0xfe240000, but overwritten
with a write into the PCIIOBR register. This write is expected to adjust
the PCI memory window, but not to change the region's base adddress.
Peter Maydell provided the following detailed explanation.
"Section 22.3.7 and in particular figure 22.3 (of "SSH7751R user's manual:
hardware") are clear about how this is supposed to work: there is a window
at 0xfe240000 in the system register space for PCI I/O space. When the CPU
makes an access into that area, the PCI controller calculates the PCI
address to use by combining bits 0..17 of the system address with the
bits 31..18 value that the guest has put into the PCIIOBR. That is, writing
to the PCIIOBR changes which section of the IO address space is visible in
the 0xfe240000 window. Instead what QEMU's implementation does is move the
window to whatever value the guest writes to the PCIIOBR register -- so if
the guest writes 0 we put the window at 0 in system address space."
Fix the problem by calling memory_region_set_alias_offset() instead of
removing and re-adding the PCI ISA subregion on writes into PCIIOBR.
At the same time, in sh_pci_device_realize(), don't set iobr since
it is overwritten later anyway. Instead, pass the base address to
memory_region_add_subregion() directly.
Many thanks to Peter Maydell for the detailed problem analysis, and for
providing suggestions on how to fix the problem.
Signed-off-by: Guenter Roeck <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba
https://github.com/qemu/qemu/commit/0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/translate-vfp.inc.c
Log Message:
-----------
target/arm: Rename isar_feature_aa32_simd_r32
The old name, isar_feature_aa32_fp_d32, does not reflect
the MVFR0 field name, SIMDReg.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: wrapped one long line]
Signed-off-by: Peter Maydell <address@hidden>
Commit: a6627f5fc607939f7c8b9c3157fdcb2d368ba0ed
https://github.com/qemu/qemu/commit/a6627f5fc607939f7c8b9c3157fdcb2d368ba0ed
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.c
M target/arm/helper.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Use isar_feature_aa32_simd_r32 more places
Many uses of ARM_FEATURE_VFP3 are testing for the number of simd
registers implemented. Use the proper test vs MVFR0.SIMDReg.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: fix typo in commit message]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9eb4f58918a851fb46895fd9b7ce579afeac9d02
https://github.com/qemu/qemu/commit/9eb4f58918a851fb46895fd9b7ce579afeac9d02
Author: Richard Henderson <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Set MVFR0.FPSP for ARMv5 cpus
We are going to convert FEATURE tests to ISAR tests,
so FPSP needs to be set for these cpus, like we have
already for FPDP.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9ac5df20f51fabcba0d902025df4bd7ea987c158
https://github.com/qemu/qemu/commit/9ac5df20f51fabcba0d902025df4bd7ea987c158
Author: Peter Maydell <address@hidden>
Date: 2020-02-21 (Fri, 21 Feb 2020)
Changed paths:
M hw/arm/allwinner-a10.c
M hw/arm/mainstone.c
M hw/arm/z2.c
M hw/intc/armv7m_nvic.c
M hw/misc/aspeed_scu.c
M hw/misc/iotkit-secctl.c
M hw/sh4/sh_pci.c
M hw/ssi/xilinx_spips.c
M hw/usb/hcd-ehci-sysbus.c
M hw/usb/hcd-ohci.c
M hw/usb/hcd-ohci.h
M include/hw/arm/allwinner-a10.h
M linux-user/elfload.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/debug_helper.c
M target/arm/helper-sve.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/internals.h
M target/arm/kvm32.c
M target/arm/kvm64.c
M target/arm/neon_helper.c
M target/arm/pauth_helper.c
M target/arm/translate-a64.c
M target/arm/translate-vfp.inc.c
M target/arm/translate.c
M target/arm/translate.h
M target/arm/vec_helper.c
M target/arm/vfp_helper.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20200221-1' into staging
target-arm queue:
* aspeed/scu: Implement chip ID register
* hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register
* mainstone: Make providing flash images non-mandatory
* z2: Make providing flash images non-mandatory
* Fix failures to flush SVE high bits after AdvSIMD INS/ZIP/UZP/TRN/TBL/TBX/EXT
* Minor performance improvement: spend less time recalculating hflags values
* Code cleanup to isar_feature function tests
* Implement ARMv8.1-PMU and ARMv8.4-PMU extensions
* Bugfix: correct handling of PMCR_EL0.LC bit
* Bugfix: correct definition of PMCRDP
* Correctly implement ACTLR2, HACTLR2
* allwinner: Wire up USB ports
* Vectorize emulation of USHL, SSHL, PMUL*
* xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
* sh4: Fix PCI ISA IO memory subregion
# gpg: Signature made Fri 21 Feb 2020 16:17:37 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200221-1: (46 commits)
target/arm: Set MVFR0.FPSP for ARMv5 cpus
target/arm: Use isar_feature_aa32_simd_r32 more places
target/arm: Rename isar_feature_aa32_simd_r32
sh4: Fix PCI ISA IO memory subregion
xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd
target/arm: Convert PMULL.8 to gvec
target/arm: Convert PMULL.64 to gvec
target/arm: Convert PMUL.8 to gvec
target/arm: Vectorize USHL and SSHL
arm: allwinner: Wire up USB ports
hcd-ehci: Introduce "companion-enable" sysbus property
hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file
target/arm: Correctly implement ACTLR2, HACTLR2
target/arm: Use FIELD_EX32 for testing 32-bit fields
target/arm: Use isar_feature function for testing AA32HPD feature
target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
target/arm: Correct handling of PMCR_EL0.LC bit
target/arm: Correct definition of PMCRDP
target/arm: Provide ARMv8.4-PMU in '-cpu max'
target/arm: Implement ARMv8.4-PMU extension
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/a8c6af67e1e8...9ac5df20f51f
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- [Qemu-commits] [qemu/qemu] c7e1f5: aspeed/scu: Create separate write callbacks,
Peter Maydell <=