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[Qemu-commits] [qemu/qemu] 0e7bb1: i.MX: Fix inverted register bits in w
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 0e7bb1: i.MX: Fix inverted register bits in wdt code. |
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Date: |
Fri, 14 Feb 2020 08:45:14 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 0e7bb14b564b6eef9aa0eed45df47babcdcaba12
https://github.com/qemu/qemu/commit/0e7bb14b564b6eef9aa0eed45df47babcdcaba12
Author: Roman Kapl <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/misc/imx2_wdt.c
Log Message:
-----------
i.MX: Fix inverted register bits in wdt code.
Documentation says for WDA '0: Assert WDOG output.' and for SRS
'0: Assert system reset signal.'.
Signed-off-by: Roman Kapl <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5fecbf0f0cc9168da1b003a115ac18fe722f293a
https://github.com/qemu/qemu/commit/5fecbf0f0cc9168da1b003a115ac18fe722f293a
Author: Roman Kapl <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/fsl-imx6.c
M include/hw/arm/fsl-imx6.h
Log Message:
-----------
i.MX: Add support for WDT on i.MX6
Uses the i.MX2 rudimentary watchdog driver.
Signed-off-by: Roman Kapl <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: removed accidental duplicate #include line]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4ac637ef8439827d8db4a807c81df978a8c772c4
https://github.com/qemu/qemu/commit/4ac637ef8439827d8db4a807c81df978a8c772c4
Author: Heyi Guo <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
bios-tables-test: prepare to change ARM virt ACPI DSDT
We are going to change ARM virt ACPI DSDT table, which will cause make
check to fail, so temporarily add related golden masters to ignore
list.
Signed-off-by: Heyi Guo <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: cf48a9052e82b8fff57c2f2e2d53dee6496ee133
https://github.com/qemu/qemu/commit/cf48a9052e82b8fff57c2f2e2d53dee6496ee133
Author: Heyi Guo <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
arm/virt/acpi: remove meaningless sub device "RP0" from PCI0
The sub device "RP0" under PCI0 in ACPI/DSDT does not contain any
method or property other than "_ADR", so it is safe to remove it.
Signed-off-by: Heyi Guo <address@hidden>
Acked-by: "Michael S. Tsirkin" <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 93e41700012525ca198d10c586e024b925779e6d
https://github.com/qemu/qemu/commit/93e41700012525ca198d10c586e024b925779e6d
Author: Heyi Guo <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
arm/virt/acpi: remove _ADR from devices identified by _HID
According to ACPI spec, _ADR should be used for device on a bus that
has a standard enumeration algorithm, but not for device which is on
system bus and must be enumerated by OSPM. And it is not recommended
to contain both _HID and _ADR in a single device.
See ACPI 6.3, section 6.1, top of page 343:
A device object must contain either an _HID object or an _ADR object,
but should not contain both.
(https://uefi.org/sites/default/files/resources/ACPI_6_3_May16.pdf)
Signed-off-by: Heyi Guo <address@hidden>
Acked-by: Igor Mammedov <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: c77b25315941250163d3c226266db584ebf7f3e8
https://github.com/qemu/qemu/commit/c77b25315941250163d3c226266db584ebf7f3e8
Author: Heyi Guo <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
arm/acpi: fix PCI _PRT definition
The address field in each _PRT mapping package should be constructed
with high word for device# and low word for function#, so it is wrong
to use bus_no as the high word. The existing code adds a bunch useless
entries with device #s above 31. Enumerate all possible slots
(i.e. PCI_SLOT_MAX) instead.
Signed-off-by: Heyi Guo <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f0ca15ad8954bad5baf8a7d5f625dd810616b53c
https://github.com/qemu/qemu/commit/f0ca15ad8954bad5baf8a7d5f625dd810616b53c
Author: Heyi Guo <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
arm/acpi: fix duplicated _UID of PCI interrupt link devices
Using _UID of 0 for all PCI interrupt link devices absolutely violates
the spec. Simply increase one by one.
Signed-off-by: Heyi Guo <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b43bd40ba27c3a9ebd246f7294dc8983d96fe7e4
https://github.com/qemu/qemu/commit/b43bd40ba27c3a9ebd246f7294dc8983d96fe7e4
Author: Heyi Guo <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/virt-acpi-build.c
Log Message:
-----------
arm/acpi: simplify the description of PCI _CRS
The original code defines a named object for the resource template but
then returns the resource template object itself; the resulted output
is like below:
Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
......
})
Return (ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
......
})
}
So the named object "RBUF" is actually useless. The more natural way
is to return RBUF instead, or simply drop RBUF definition.
Choose the latter one to simplify the code.
Signed-off-by: Heyi Guo <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 979a89023f40a89c67f68566c26b22b0e903b95e
https://github.com/qemu/qemu/commit/979a89023f40a89c67f68566c26b22b0e903b95e
Author: Heyi Guo <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M tests/data/acpi/virt/DSDT
M tests/data/acpi/virt/DSDT.memhp
M tests/data/acpi/virt/DSDT.numamem
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
virt/acpi: update golden masters for DSDT update
Differences between disassembled ASL files:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of DSDT, Thu Jan 23 16:00:04 2020
+ * Disassembly of DSDT.new, Thu Jan 23 16:47:12 2020
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x0000481E (18462)
+ * Length 0x000014BB (5307)
* Revision 0x02
- * Checksum 0x60
+ * Checksum 0xD1
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -43,7 +43,6 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT",
0x00000001)
0x00000021,
}
})
- Name (_ADR, 0x09000000) // _ADR: Address
}
Device (FLS0)
@@ -668,11 +667,10 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT",
0x00000001)
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
- Name (_ADR, Zero) // _ADR: Address
Name (_UID, "PCI0") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String
Name (_CCA, One) // _CCA: Cache Coherency Attribute
- Name (_PRT, Package (0x0400) // _PRT: PCI Routing Table
+ Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
{
Package (0x04)
{
@@ -1696,7174 +1694,6 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT",
0x00000001)
0x03,
GSI2,
Zero
- },
-
- Package (0x04)
- {
- 0x0020FFFF,
- Zero,
- GSI0,
- Zero
- },
-
- *Omit the other (4 * (256 - 32) - 2) packages*
-
- Package (0x04)
- {
- 0x00FFFFFF,
- 0x03,
- GSI2,
- Zero
}
})
Device (GSI0)
@@ -8892,7 +1722,7 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT",
0x00000001)
Device (GSI1)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) //
_HID: Hardware ID
- Name (_UID, Zero) // _UID: Unique ID
+ Name (_UID, One) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource
Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,
,, )
@@ -8915,7 +1745,7 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT",
0x00000001)
Device (GSI2)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) //
_HID: Hardware ID
- Name (_UID, Zero) // _UID: Unique ID
+ Name (_UID, 0x02) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource
Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,
,, )
@@ -8938,7 +1768,7 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT",
0x00000001)
Device (GSI3)
{
Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) //
_HID: Hardware ID
- Name (_UID, Zero) // _UID: Unique ID
+ Name (_UID, 0x03) // _UID: Unique ID
Name (_PRS, ResourceTemplate () // _PRS: Possible Resource
Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,
,, )
@@ -8965,37 +1795,6 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT",
0x00000001)
Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
{
- Name (RBUF, ResourceTemplate ()
- {
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed,
PosDecode,
- 0x0000, // Granularity
- 0x0000, // Range Minimum
- 0x00FF, // Range Maximum
- 0x0000, // Translation Offset
- 0x0100, // Length
- ,, )
- DWordMemory (ResourceProducer, PosDecode, MinFixed,
MaxFixed, NonCacheable, ReadWrite,
- 0x00000000, // Granularity
- 0x10000000, // Range Minimum
- 0x3EFEFFFF, // Range Maximum
- 0x00000000, // Translation Offset
- 0x2EFF0000, // Length
- ,, , AddressRangeMemory, TypeStatic)
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
EntireRange,
- 0x00000000, // Granularity
- 0x00000000, // Range Minimum
- 0x0000FFFF, // Range Maximum
- 0x3EFF0000, // Translation Offset
- 0x00010000, // Length
- ,, , TypeStatic, DenseTranslation)
- QWordMemory (ResourceProducer, PosDecode, MinFixed,
MaxFixed, NonCacheable, ReadWrite,
- 0x0000000000000000, // Granularity
- 0x0000008000000000, // Range Minimum
- 0x000000FFFFFFFFFF, // Range Maximum
- 0x0000000000000000, // Translation Offset
- 0x0000008000000000, // Length
- ,, , AddressRangeMemory, TypeStatic)
- })
Return (ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed,
PosDecode,
@@ -9080,11 +1879,6 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT",
0x00000001)
})
}
- Device (RP0)
- {
- Name (_ADR, Zero) // _ADR: Address
- }
-
Device (RES0)
{
Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) //
_HID: Hardware ID
@@ -9131,7 +1925,6 @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT",
0x00000001)
Device (PWRB)
{
Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID:
Hardware ID
- Name (_ADR, Zero) // _ADR: Address
Name (_UID, Zero) // _UID: Unique ID
}
}
The differences between the two versions of DSDT.memhp are almost the
same as the above, except for total length and checksum.
DSDT.numamem binary is just the same with DSDT on virt machine, so we
don't show the differences again.
Signed-off-by: Heyi Guo <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: fee7aa46edd76f06c3dc176abb8fd05b365efce6
https://github.com/qemu/qemu/commit/fee7aa46edd76f06c3dc176abb8fd05b365efce6
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Add arm_mmu_idx_is_stage1_of_2
Use a common predicate for querying stage1-ness.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 452ef8cb8c7b06f44a30a3c3a54d3be82c4aef59
https://github.com/qemu/qemu/commit/452ef8cb8c7b06f44a30a3c3a54d3be82c4aef59
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/cpu-param.h
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled
To implement PAN, we will want to swap, for short periods
of time, to a different privileged mmu_idx. In addition,
we cannot do this with flushing alone, because the AT*
instructions have both PAN and PAN-less versions.
Add the ARMMMUIdx*_PAN constants where necessary next to
the corresponding ARMMMUIdx* constant.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 3d6ad6bb466f487bcc861f99e2c9054230df1076
https://github.com/qemu/qemu/commit/3d6ad6bb466f487bcc861f99e2c9054230df1076
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Add isar_feature tests for PAN + ATS1E1
Include definitions for all of the bits in ID_MMFR3.
We already have a definition for ID_AA64MMFR1.PAN.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d8564ee4e5bce87ec1fdf23656df9367eb1bc571
https://github.com/qemu/qemu/commit/d8564ee4e5bce87ec1fdf23656df9367eb1bc571
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Move LOR regdefs to file scope
For static const regdefs, file scope is preferred.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4f9584ed4bba8a57a3cb2fa48a682725005d530a
https://github.com/qemu/qemu/commit/4f9584ed4bba8a57a3cb2fa48a682725005d530a
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/internals.h
M target/arm/translate.c
Log Message:
-----------
target/arm: Split out aarch32_cpsr_valid_mask
Split this helper out of msr_mask in translate.c. At the same time,
transform the negative reductive logic to positive accumulative logic.
It will be usable along the exception paths.
While touching msr_mask, fix up formatting.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f062d1447f2a80e7a5f593b8cb5ac7cab5e16eb0
https://github.com/qemu/qemu/commit/f062d1447f2a80e7a5f593b8cb5ac7cab5e16eb0
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/internals.h
Log Message:
-----------
target/arm: Mask CPSR_J when Jazelle is not enabled
The J bit signals Jazelle mode, and so of course is RES0
when the feature is not enabled.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 437864216d63f052f3cd06ec8861d0e432496424
https://github.com/qemu/qemu/commit/437864216d63f052f3cd06ec8861d0e432496424
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask
CPSR_ERET_MASK was a useless renaming of CPSR_RESERVED.
The function also takes into account bits that the cpu
does not support.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d203cabd1bd12f31c9df0b5737421ba67b96857b
https://github.com/qemu/qemu/commit/d203cabd1bd12f31c9df0b5737421ba67b96857b
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/helper-a64.c
Log Message:
-----------
target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return
Using ~0 as the mask on the aarch64->aarch32 exception return
was not even as correct as the CPSR_ERET_MASK that we had used
on the aarch32->aarch32 exception return.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 70dae0d069c45250bbefd9424089383a8ac239de
https://github.com/qemu/qemu/commit/70dae0d069c45250bbefd9424089383a8ac239de
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Remove CPSR_RESERVED
The only remaining use was in op_helper.c. Use PSTATE_SS
directly, and move the commentary so that it is more obvious
what is going on.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 140845111809cd6fd57ccde93867b48cc56ffc74
https://github.com/qemu/qemu/commit/140845111809cd6fd57ccde93867b48cc56ffc74
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/helper-a64.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Introduce aarch64_pstate_valid_mask
Use this along the exception return path, where we previously
accepted any values.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 220f508f49c5f49fb771d5105f991c19ffede3f7
https://github.com/qemu/qemu/commit/220f508f49c5f49fb771d5105f991c19ffede3f7
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Update MSR access for PAN
For aarch64, there's a dedicated msr (imm, reg) insn.
For aarch32, this is done via msr to cpsr. Writes from el0
are ignored, which is already handled by the CPSR_USER mask.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 66412260cc1bee60a22d96e4ad8569b85745fea4
https://github.com/qemu/qemu/commit/66412260cc1bee60a22d96e4ad8569b85745fea4
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Update arm_mmu_idx_el for PAN
Examine the PAN bit for EL1, EL2, and Secure EL1 to
determine if it applies.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 81636b70c226dc27d7ebc8dedbcec26166d23085
https://github.com/qemu/qemu/commit/81636b70c226dc27d7ebc8dedbcec26166d23085
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Enforce PAN semantics in get_S1prot
If we have a PAN-enforcing mmu_idx, set prot == 0 if user_rw != 0.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4a2696c0d4d80e14a192b28148c6167bc5056f94
https://github.com/qemu/qemu/commit/4a2696c0d4d80e14a192b28148c6167bc5056f94
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Set PAN bit as required on exception entry
The PAN bit is preserved, or set as per SCTLR_ELx.SPAN,
plus several other conditions listed in the ARM ARM.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 04b07d29722192926f467ea5fedf2c3b0996a2a5
https://github.com/qemu/qemu/commit/04b07d29722192926f467ea5fedf2c3b0996a2a5
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement ATS1E1 system registers
This is a minor enhancement over ARMv8.1-PAN.
The *_PAN mmu_idx are used with the existing do_ats_write.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e0fe7309a7c21ef2386de50d37c86aea0d671c08
https://github.com/qemu/qemu/commit/e0fe7309a7c21ef2386de50d37c86aea0d671c08
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable ARMv8.2-ATS1E1 in -cpu max
This includes enablement of ARMv8.1-PAN.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 64761e10af2742a916c08271828890274137b9e8
https://github.com/qemu/qemu/commit/64761e10af2742a916c08271828890274137b9e8
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/kvm64.c
Log Message:
-----------
target/arm: Add ID_AA64MMFR2_EL1
Add definitions for all of the fields, up to ARMv8.5.
Convert the existing RESERVED register to a full register.
Query KVM for the value of the register for the host.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9eeb7a1c9531cb3574bfe2c36eb7624802c3ec00
https://github.com/qemu/qemu/commit/9eeb7a1c9531cb3574bfe2c36eb7624802c3ec00
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Update MSR access to UAO
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7a8014ab871d5320effd737dfe88b2e80f16a509
https://github.com/qemu/qemu/commit/7a8014ab871d5320effd737dfe88b2e80f16a509
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement UAO semantics
We need only override the current condition under which
TBFLAG_A64.UNPRIV is set.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e11f0eb6724571adb812a3ce5269c41586e0262b
https://github.com/qemu/qemu/commit/e11f0eb6724571adb812a3ce5269c41586e0262b
Author: Richard Henderson <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable ARMv8.2-UAO in -cpu max
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: bfdd34f1caa9357ac66fc26973b4eb2d56373f2b
https://github.com/qemu/qemu/commit/bfdd34f1caa9357ac66fc26973b4eb2d56373f2b
Author: Guenter Roeck <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm: ast2400/ast2500: Wire up EHCI controllers
Initialize EHCI controllers on AST2400 and AST2500 using the existing
TYPE_PLATFORM_EHCI. After this change, booting ast2500-evb into Linux
successfully instantiates a USB interface.
ehci-platform 1e6a3000.usb: EHCI Host Controller
ehci-platform 1e6a3000.usb: new USB bus registered, assigned bus number 1
ehci-platform 1e6a3000.usb: irq 21, io mem 0x1e6a3000
ehci-platform 1e6a3000.usb: USB 2.0 started, EHCI 1.00
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.05
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: EHCI Host Controller
Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 917940ce69ef09490f486826f51c90b8c639a1b4
https://github.com/qemu/qemu/commit/917940ce69ef09490f486826f51c90b8c639a1b4
Author: Guenter Roeck <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/aspeed_ast2600.c
Log Message:
-----------
hw/arm: ast2600: Wire up EHCI controllers
Initialize EHCI controllers on AST2600 using the existing
TYPE_PLATFORM_EHCI. After this change, booting ast2600-evb
into Linux successfully instantiates a USB interface after
the necessary changes are made to its devicetree files.
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-platform: EHCI generic platform driver
ehci-platform 1e6a3000.usb: EHCI Host Controller
ehci-platform 1e6a3000.usb: new USB bus registered, assigned bus number 1
ehci-platform 1e6a3000.usb: irq 25, io mem 0x1e6a3000
ehci-platform 1e6a3000.usb: USB 2.0 started, EHCI 1.00
usb usb1: Manufacturer: Linux 5.5.0-09825-ga0802f2d0ef5-dirty ehci_hcd
usb 1-1: new high-speed USB device number 2 using ehci-platform
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: Niek Linnenbank <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8bbc394c552cd003e034640f8e07a496de90e340
https://github.com/qemu/qemu/commit/8bbc394c552cd003e034640f8e07a496de90e340
Author: Chen Qun <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/char/exynos4210_uart.c
Log Message:
-----------
hw/char/exynos4210_uart: Fix memleaks in exynos4210_uart_init
It's easy to reproduce as follow:
virsh qemu-monitor-command vm1 --pretty '{"execute": "device-list-properties",
"arguments":{"typename":"exynos4210.uart"}}'
ASAN shows memory leak stack:
#1 0xfffd896d71cb in g_malloc0 (/lib64/libglib-2.0.so.0+0x571cb)
#2 0xaaad270beee3 in timer_new_full /qemu/include/qemu/timer.h:530
#3 0xaaad270beee3 in timer_new /qemu/include/qemu/timer.h:551
#4 0xaaad270beee3 in timer_new_ns /qemu/include/qemu/timer.h:569
#5 0xaaad270beee3 in exynos4210_uart_init /qemu/hw/char/exynos4210_uart.c:677
#6 0xaaad275c8f4f in object_initialize_with_type /qemu/qom/object.c:516
#7 0xaaad275c91bb in object_new_with_type /qemu/qom/object.c:684
#8 0xaaad2755df2f in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:152
Reported-by: Euler Robot <address@hidden>
Signed-off-by: Chen Qun <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 918c81a53eb18ec4e9979876a39e86610cc565f4
https://github.com/qemu/qemu/commit/918c81a53eb18ec4e9979876a39e86610cc565f4
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Use BCM2708 machine type with pre Device Tree kernels
When booting without device tree, the Linux kernels uses the $R1
register to determine the machine type. The list of values is
registered at [1].
There are two entries for the Raspberry Pi:
- https://www.arm.linux.org.uk/developer/machines/list.php?mid=3138
name: MACH_TYPE_BCM2708
value: 0xc42 (3138)
status: Active, not mainlined
date: 15 Oct 2010
- https://www.arm.linux.org.uk/developer/machines/list.php?mid=4828
name: MACH_TYPE_BCM2835
value: 4828
status: Active, mainlined
date: 6 Dec 2013
QEMU always used the non-mainlined type MACH_TYPE_BCM2708.
The value 0xc43 is registered to 'MX51_GGC' (processor i.MX51), and
0xc44 to 'Western Digital Sharespace NAS' (processor Marvell 88F5182).
The Raspberry Pi foundation bootloader only sets the BCM2708 machine
type, see [2] or [3]:
133 9:
134 mov r0, #0
135 ldr r1, =3138 @ BCM2708 machine id
136 ldr r2, atags @ ATAGS
137 bx r4
U-Boot only uses MACH_TYPE_BCM2708 (see [4]):
25 /*
26 * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
27 * so 2708 has historically been used rather than a dedicated 2835 ID.
28 *
29 * We don't define a machine type for bcm2709/bcm2836 since the RPi
Foundation
30 * chose to use someone else's previously registered machine ID (3139,
MX51_GGC)
31 * rather than obtaining a valid ID:-/
32 *
33 * For the bcm2837, hopefully a machine type is not needed, since everything
34 * is DT.
35 */
While the definition MACH_BCM2709 with value 0xc43 was introduced in
a commit described "Add 2709 platform for Raspberry Pi 2" out of the
mainline Linux kernel, it does not seem used, and the platform is
introduced with Device Tree support anyway (see [5] and [6]).
Remove the unused values (0xc43 introduced in commit 1df7d1f9303aef
"raspi: add raspberry pi 2 machine" and 0xc44 in commit bade58166f4
"raspi: Raspberry Pi 3 support"), keeping only MACH_TYPE_BCM2708.
[1] https://www.arm.linux.org.uk/developer/machines/
[2] https://github.com/raspberrypi/tools/blob/920c7ed2e/armstubs/armstub7.S#L135
[3] https://github.com/raspberrypi/tools/blob/49719d554/armstubs/armstub7.S#L64
[4]
https://gitlab.denx.de/u-boot/u-boot/blob/v2015.04/include/configs/rpi-common.h#L18
[5]
https://github.com/raspberrypi/linux/commit/d9fac63adac#diff-6722037d79570df5b392a49e0e006573R526
[6]
http://lists.infradead.org/pipermail/linux-rpi-kernel/2015-February/001268.html
Cc: Zoltán Baldaszti <address@hidden>
Cc: Pekka Enberg <address@hidden>
Cc: Stephen Warren <address@hidden>
Cc: Kshitij Soni <address@hidden>
Cc: Michael Chan <address@hidden>
Cc: Andrew Baumann <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Niek Linnenbank <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: fc78a990ec1032d8272db49988376f197efac817
https://github.com/qemu/qemu/commit/fc78a990ec1032d8272db49988376f197efac817
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Correct the board descriptions
We hardcode the board revision as 0xa21041 for the raspi2, and
0xa02082 for the raspi3:
166 static void raspi_init(MachineState *machine, int version)
167 {
...
194 int board_rev = version == 3 ? 0xa02082 : 0xa21041;
These revision codes are for the 2B and 3B models, see:
https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md
Correct the board description.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: cd6c9977d3b34d3c5569bec8c5316735b7df5239
https://github.com/qemu/qemu/commit/cd6c9977d3b34d3c5569bec8c5316735b7df5239
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Extract the version from the board revision
The board revision encode the board version. Add a helper
to extract the version, and use it.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: f5bb124ecf34298246b4a776f2cf7545b1170638
https://github.com/qemu/qemu/commit/f5bb124ecf34298246b4a776f2cf7545b1170638
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Extract the RAM size from the board revision
The board revision encode the amount of RAM. Add a helper
to extract the RAM size, and use it.
Since the amount of RAM is fixed (it is impossible to physically
modify to have more or less RAM), do not allow sizes different
than the one anounced by the manufacturer.
Acked-by: Igor Mammedov <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2e664b45f4d9e7449bd977980aa1454b16837713
https://github.com/qemu/qemu/commit/2e664b45f4d9e7449bd977980aa1454b16837713
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Extract the processor type from the board revision
The board revision encode the processor type. Add a helper
to extract the type, and use it.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: cc360632f613ccef6676460b4fb5eaad9e82e267
https://github.com/qemu/qemu/commit/cc360632f613ccef6676460b4fb5eaad9e82e267
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Trivial code movement
There is no point in creating the SoC object before allocating the RAM.
Move the call to keep all the SoC-related calls together.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: cb57df6f7f5481904db987a2afa8aabdc1e1d545
https://github.com/qemu/qemu/commit/cb57df6f7f5481904db987a2afa8aabdc1e1d545
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Make machines children of abstract RaspiMachineClass
QOM'ify RaspiMachineState. Now machines inherit of RaspiMachineClass.
Cc: Igor Mammedov <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: c318c66c67ba143cd32d709cb2eb20eaf8cb9f8f
https://github.com/qemu/qemu/commit/c318c66c67ba143cd32d709cb2eb20eaf8cb9f8f
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Make board_rev a field of RaspiMachineClass
We want to have a common class_init(). The only value that
matters (and changes) is the board revision.
Pass the board_rev as class_data to class_init().
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 13c4e2c087924d62da006858baee20b1ffb44462
https://github.com/qemu/qemu/commit/13c4e2c087924d62da006858baee20b1ffb44462
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Let class_init() directly call raspi_machine_init()
raspi_machine_init() access to board_rev via RaspiMachineClass.
raspi2_init() and raspi3_init() do nothing. Call raspi_machine_init
directly.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 975f3402fad40dc2e530e2a7a91ba7d0c2cd6a1d
https://github.com/qemu/qemu/commit/975f3402fad40dc2e530e2a7a91ba7d0c2cd6a1d
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Set default RAM size to size encoded in board revision
We added a helper to extract the RAM size from the board
revision, and made board_rev a field of RaspiMachineClass.
The class_init() can now use the helper to extract from the
board revision the board-specific amount of RAM.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 98b541e1b219054d4cde3b327f0ba8ef5c8d8ebd
https://github.com/qemu/qemu/commit/98b541e1b219054d4cde3b327f0ba8ef5c8d8ebd
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Extract the board model from the board revision
The board revision encode the model type. Add a helper
to extract the model, and use it.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: a03bde3674e400473717baec599da0a7ee0cf066
https://github.com/qemu/qemu/commit/a03bde3674e400473717baec599da0a7ee0cf066
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Use a unique raspi_machine_class_init() method
With the exception of the ignore_memory_transaction_failures
flag set for the raspi2, both machine_class_init() methods
are now identical. Merge them to keep a unique method.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 759f0f87e34fe63a475d926ea6db88d11d2cd018
https://github.com/qemu/qemu/commit/759f0f87e34fe63a475d926ea6db88d11d2cd018
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Extract the cores count from the board revision
The count of ARM cores is encoded in the board revision. Add a
helper to extract the number of cores, and use it. This will be
helpful when we add the Raspi0/1 that have a single core.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: tweaked commit message as suggested by Igor]
Signed-off-by: Peter Maydell <address@hidden>
Commit: dc7a88d0810ad272bdcd2e0869359af78fdd9114
https://github.com/qemu/qemu/commit/dc7a88d0810ad272bdcd2e0869359af78fdd9114
Author: Peter Maydell <address@hidden>
Date: 2020-02-13 (Thu, 13 Feb 2020)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Implement ARMv8.1-VMID16 extension
The ARMv8.1-VMID16 extension extends the VMID from 8 bits to 16 bits:
* the ID_AA64MMFR1_EL1.VMIDBits field specifies whether the VMID is
8 or 16 bits
* the VMID field in VTTBR_EL2 is extended to 16 bits
* VTCR_EL2.VS lets the guest specify whether to use the full 16 bits,
or use the backwards-compatible 8 bits
For QEMU implementing this is trivial:
* we do not track VMIDs in TLB entries, so we never use the VMID field
* we treat any write to VTTBR_EL2, not just a change to the VMID field
bits, as a "possible VMID change" that causes us to throw away TLB
entries, so that code doesn't need changing
* we allow the guest to read/write the VTCR_EL2.VS bit already
So all that's missing is the ID register part: report that we support
VMID16 in our 'max' CPU.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: bc882694a3c757e7bd95c90e21b048d347ba9244
https://github.com/qemu/qemu/commit/bc882694a3c757e7bd95c90e21b048d347ba9244
Author: Peter Maydell <address@hidden>
Date: 2020-02-14 (Fri, 14 Feb 2020)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M hw/arm/fsl-imx6.c
M hw/arm/raspi.c
M hw/arm/virt-acpi-build.c
M hw/char/exynos4210_uart.c
M hw/misc/imx2_wdt.c
M include/hw/arm/aspeed_soc.h
M include/hw/arm/fsl-imx6.h
M target/arm/cpu-param.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper-a64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/kvm64.c
M target/arm/op_helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
M tests/data/acpi/virt/DSDT
M tests/data/acpi/virt/DSDT.memhp
M tests/data/acpi/virt/DSDT.numamem
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200213'
into staging
target-arm queue:
* i.MX: Fix inverted sense of register bits in watchdog timer
* i.MX: Add support for WDT on i.MX6
* arm/virt: cleanups to ACPI tables
* Implement ARMv8.1-VMID16 extension
* Implement ARMv8.1-PAN
* Implement ARMv8.2-UAO
* Implement ARMv8.2-ATS1E1
* ast2400/2500/2600: Wire up EHCI controllers
* hw/char/exynos4210_uart: Fix memleaks in exynos4210_uart_init
* hw/arm/raspi: Clean up the board code
# gpg: Signature made Thu 13 Feb 2020 14:40:34 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200213: (46 commits)
target/arm: Implement ARMv8.1-VMID16 extension
hw/arm/raspi: Extract the cores count from the board revision
hw/arm/raspi: Use a unique raspi_machine_class_init() method
hw/arm/raspi: Extract the board model from the board revision
hw/arm/raspi: Set default RAM size to size encoded in board revision
hw/arm/raspi: Let class_init() directly call raspi_machine_init()
hw/arm/raspi: Make board_rev a field of RaspiMachineClass
hw/arm/raspi: Make machines children of abstract RaspiMachineClass
hw/arm/raspi: Trivial code movement
hw/arm/raspi: Extract the processor type from the board revision
hw/arm/raspi: Extract the RAM size from the board revision
hw/arm/raspi: Extract the version from the board revision
hw/arm/raspi: Correct the board descriptions
hw/arm/raspi: Use BCM2708 machine type with pre Device Tree kernels
hw/char/exynos4210_uart: Fix memleaks in exynos4210_uart_init
hw/arm: ast2600: Wire up EHCI controllers
hw/arm: ast2400/ast2500: Wire up EHCI controllers
target/arm: Enable ARMv8.2-UAO in -cpu max
target/arm: Implement UAO semantics
target/arm: Update MSR access to UAO
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/517c84cef759...bc882694a3c7
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