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[Qemu-commits] [qemu/qemu] 0999a4: target/arm/monitor: query-cpu-model-e
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 0999a4: target/arm/monitor: query-cpu-model-expansion cras... |
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Date: |
Mon, 10 Feb 2020 04:15:15 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 0999a4ba8718aa96105b978d3567fc7e90244c7e
https://github.com/qemu/qemu/commit/0999a4ba8718aa96105b978d3567fc7e90244c7e
Author: Liang Yan <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/monitor.c
Log Message:
-----------
target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine
type none
Commit e19afd566781 mentioned that target-arm only supports queryable
cpu models 'max', 'host', and the current type when KVM is in use.
The logic works well until using machine type none.
For machine type none, cpu_type will be null if cpu option is not
set by command line, strlen(cpu_type) will terminate process.
So We add a check above it.
This won't affect i386 and s390x since they do not use current_cpu.
Signed-off-by: Liang Yan <address@hidden>
Message-id: address@hidden
Reviewed-by: Andrew Jones <address@hidden>
Tested-by: Andrew Jones <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8fc2ea21f75923b427eba261eb70f4a258f1b4e5
https://github.com/qemu/qemu/commit/8fc2ea21f75923b427eba261eb70f4a258f1b4e5
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Define isar_feature_aa64_vh
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 03c76131bc494366a4357a1d265c5eb5cc820754
https://github.com/qemu/qemu/commit/03c76131bc494366a4357a1d265c5eb5cc820754
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Enable HCR_E2H for VHE
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e2a1a4616c86159eb4c07659a02fff8bb25d3729
https://github.com/qemu/qemu/commit/e2a1a4616c86159eb4c07659a02fff8bb25d3729
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/debug_helper.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Add CONTEXTIDR_EL2
Not all of the breakpoint types are supported, but those that
only examine contextidr are extended to support the new register.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: ed30da8eee6906032b38a84e4807e2142b09d8ec
https://github.com/qemu/qemu/commit/ed30da8eee6906032b38a84e4807e2142b09d8ec
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Add TTBR1_EL2
At the same time, add writefn to TTBR0_EL2 and TCR_EL2.
A later patch will update any ASID therein.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 53d1f85608f83d645491eba6581d1f300dba2384
https://github.com/qemu/qemu/commit/53d1f85608f83d645491eba6581d1f300dba2384
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Update CNTVCT_EL0 for VHE
The virtual offset may be 0 depending on EL, E2H and TGE.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b7e0730de32d7079a1447ecbb5616d89de77b823
https://github.com/qemu/qemu/commit/b7e0730de32d7079a1447ecbb5616d89de77b823
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Split out vae1_tlbmask
No functional change, but unify code sequences.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 90c19cdf1de440d7d9745cf255168999071b3a31
https://github.com/qemu/qemu/commit/90c19cdf1de440d7d9745cf255168999071b3a31
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Split out alle1_tlbmask
No functional change, but unify code sequences.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 527db2be8b5bf3fc915736adc2eaa9b11b294925
https://github.com/qemu/qemu/commit/527db2be8b5bf3fc915736adc2eaa9b11b294925
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Simplify tlb_force_broadcast alternatives
Rather than call to a separate function and re-compute any
parameters for the flush, simply use the correct flush
function directly.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 01b98b686460b3a0fb47125882e4f8d4268ac1b6
https://github.com/qemu/qemu/commit/01b98b686460b3a0fb47125882e4f8d4268ac1b6
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the EL1&0 regime.
The ultimate goal is
-- Non-secure regimes:
ARMMMUIdx_E10_0,
ARMMMUIdx_E20_0,
ARMMMUIdx_E10_1,
ARMMMUIdx_E2,
ARMMMUIdx_E20_2,
-- Secure regimes:
ARMMMUIdx_SE10_0,
ARMMMUIdx_SE10_1,
ARMMMUIdx_SE3,
-- Helper mmu_idx for non-secure EL1&0 stage1 and stage2
ARMMMUIdx_Stage2,
ARMMMUIdx_Stage1_E0,
ARMMMUIdx_Stage1_E1,
The 'S' prefix is reserved for "Secure". Unless otherwise specified,
each mmu_idx represents all stages of translation.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 97fa9350017e647151dd1dc212f1bbca0294dba7
https://github.com/qemu/qemu/commit/97fa9350017e647151dd1dc212f1bbca0294dba7
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2
The EL1&0 regime is the only one that uses 2-stage translation.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2859d7b590760283a7b5aef40b723e9dfd7c98ba
https://github.com/qemu/qemu/commit/2859d7b590760283a7b5aef40b723e9dfd7c98ba
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*
This is part of a reorganization to the set of mmu_idx.
The EL1&0 regime is the only one that uses 2-stage translation.
Spelling out Stage avoids confusion with Secure.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: fba37aedecb82506c62a1f9e81d066b4fd04e443
https://github.com/qemu/qemu/commit/fba37aedecb82506c62a1f9e81d066b4fd04e443
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01]
This is part of a reorganization to the set of mmu_idx.
This emphasizes that they apply to the Secure EL1&0 regime.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 127b2b086303296289099a6fb10bbc51077f1d53
https://github.com/qemu/qemu/commit/127b2b086303296289099a6fb10bbc51077f1d53
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate.c
Log Message:
-----------
target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3
This is part of a reorganization to the set of mmu_idx.
The EL3 regime only has a single stage translation, and
is always secure.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e013b7411339342aac8d986c5d5e329e1baee8e1
https://github.com/qemu/qemu/commit/e013b7411339342aac8d986c5d5e329e1baee8e1
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate.c
Log Message:
-----------
target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2
This is part of a reorganization to the set of mmu_idx.
The non-secure EL2 regime only has a single stage translation;
there is no point in pointing out that the idx is for stage1.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 79cabf1f473ca6e9fa0727f64ed9c2a84a36f0aa
https://github.com/qemu/qemu/commit/79cabf1f473ca6e9fa0727f64ed9c2a84a36f0aa
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Recover 4 bits from TBFLAGs
We had completely run out of TBFLAG bits.
Split A- and M-profile bits into two overlapping buckets.
This results in 4 free bits.
We used to initialize all of the a32 and m32 fields in DisasContext
by assignment, in arm_tr_init_disas_context. Now we only initialize
either the a32 or m32 by assignment, because the bits overlap in
tbflags. So zero the entire structure in gen_intermediate_code.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 506f149815c2168f16ade17893e117419d93f248
https://github.com/qemu/qemu/commit/506f149815c2168f16ade17893e117419d93f248
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits
We are about to expand the number of mmuidx to 10, and so need 4 bits.
For the benefit of reading the number out of -d exec, align it to the
penultimate nibble.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5f09a6dfbfbff4662f52cc3130a2e07044816497
https://github.com/qemu/qemu/commit/5f09a6dfbfbff4662f52cc3130a2e07044816497
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Rearrange ARMMMUIdxBit
Define via macro expansion, so that renumbering of the base ARMMMUIdx
symbols is automatically reflected in the bit definitions.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 25568316b2a7e73d68701042ba6ebdb217205e20
https://github.com/qemu/qemu/commit/25568316b2a7e73d68701042ba6ebdb217205e20
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Tidy ARMMMUIdx m-profile definitions
Replace the magic numbers with the relevant ARM_MMU_IDX_M_* constants.
Keep the definitions short by referencing previous symbols.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b9f6033c1a5fb7da55ed353794db8ec064f78bb2
https://github.com/qemu/qemu/commit/b9f6033c1a5fb7da55ed353794db8ec064f78bb2
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu-param.h
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate.c
Log Message:
-----------
target/arm: Reorganize ARMMMUIdx
Prepare for, but do not yet implement, the EL2&0 regime.
This involves adding the new MMUIdx enumerators and adjusting
some of the MMUIdx related predicates to match.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 339370b90d067345b69585ddf4b668fa01f41d67
https://github.com/qemu/qemu/commit/339370b90d067345b69585ddf4b668fa01f41d67
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Add regime_has_2_ranges
Create a predicate to indicate whether the regime has
both positive and negative addresses.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 6003d9800ee38aa11eefb5cd64ae55abb64bef16
https://github.com/qemu/qemu/commit/6003d9800ee38aa11eefb5cd64ae55abb64bef16
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Update arm_mmu_idx for VHE
Return the indexes for the EL2&0 regime when the appropriate bits
are set within HCR_EL2.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: aaec143212bb70ac9549cf73203d13100bd5c7c2
https://github.com/qemu/qemu/commit/aaec143212bb70ac9549cf73203d13100bd5c7c2
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper-a64.c
M target/arm/helper.c
M target/arm/pauth_helper.c
Log Message:
-----------
target/arm: Update arm_sctlr for VHE
Use the correct sctlr for EL2&0 regime. Due to header ordering,
and where arm_mmu_idx_el is declared, we need to move the function
out of line. Use the function in many more places in order to
select the correct control.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4351cb72fb65926136ab618c9e40c1f5a8813251
https://github.com/qemu/qemu/commit/4351cb72fb65926136ab618c9e40c1f5a8813251
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Update aa64_zva_access for EL2
The comment that we don't support EL2 is somewhat out of date.
Update to include checks against HCR_EL2.TDZ.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 97475a89375d62a7722e04ced9fbdf0b992f4b83
https://github.com/qemu/qemu/commit/97475a89375d62a7722e04ced9fbdf0b992f4b83
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Update ctr_el0_access for EL2
Update to include checks against HCR_EL2.TID2.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8c94b071a09c2183f032febff3112f2b7662156c
https://github.com/qemu/qemu/commit/8c94b071a09c2183f032febff3112f2b7662156c
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu-qom.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Add the hypervisor virtual counter
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5bc8437136fb1e7bc8b566f4f2f7269b0f990fad
https://github.com/qemu/qemu/commit/5bc8437136fb1e7bc8b566f4f2f7269b0f990fad
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Update timer access for VHE
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b4ecf60f7eee88cbfe5700044790cb7494c5dd37
https://github.com/qemu/qemu/commit/b4ecf60f7eee88cbfe5700044790cb7494c5dd37
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Update define_one_arm_cp_reg_with_opaque for VHE
For ARMv8.1, op1 == 5 is reserved for EL2 aliases of
EL1 and EL0 registers.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e2cce18f5c1d0d55328c585c8372cdb096bbf528
https://github.com/qemu/qemu/commit/e2cce18f5c1d0d55328c585c8372cdb096bbf528
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Add VHE system register redirection and aliasing
Several of the EL1/0 registers are redirected to the EL2 version when in
EL2 and HCR_EL2.E2H is set. Many of these registers have side effects.
Link together the two ARMCPRegInfo structures after they have been
properly instantiated. Install common dispatch routines to all of the
relevant registers.
The same set of registers that are redirected also have additional
EL12/EL02 aliases created to access the original register that was
redirected.
Omit the generic timer registers from redirection here, because we'll
need multiple kinds of redirection from both EL0 and EL2.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: bb5972e439dc0ac4d21329a9d97bad6760ec702d
https://github.com/qemu/qemu/commit/bb5972e439dc0ac4d21329a9d97bad6760ec702d
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Add VHE timer register redirection and aliasing
Apart from the wholesale redirection that HCR_EL2.E2H performs
for EL2, there's a separate redirection specific to the timers
that happens for EL0 when running in the EL2&0 regime.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d06dc93340825030b6297c61199a17c0067b0377
https://github.com/qemu/qemu/commit/d06dc93340825030b6297c61199a17c0067b0377
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Flush tlb for ASID changes in EL2&0 translation regime
Since we only support a single ASID, flush the tlb when it changes.
Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between
the two TTBR* registers for the location of the ASID.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 85d0dc9fa205027554372367f6925749a2d2b4c4
https://github.com/qemu/qemu/commit/85d0dc9fa205027554372367f6925749a2d2b4c4
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Flush tlbs for E2&0 translation regime
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d1b31428fd522b725bc053c84b5fbc8764061363
https://github.com/qemu/qemu/commit/d1b31428fd522b725bc053c84b5fbc8764061363
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Update arm_phys_excp_target_el for TGE
The TGE bit routes all asynchronous exceptions to EL2.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: c2ddb7cf963b3bea838266bfca62514dc9750a10
https://github.com/qemu/qemu/commit/c2ddb7cf963b3bea838266bfca62514dc9750a10
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Update {fp,sve}_exception_el for VHE
When TGE+E2H are both set, CPACR_EL1 is ignored.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: a7469a3c1edc7687d7d25967bc2c0280de202bca
https://github.com/qemu/qemu/commit/a7469a3c1edc7687d7d25967bc2c0280de202bca
Author: Alex Bennée <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/pauth_helper.c
Log Message:
-----------
target/arm: check TGE and E2H flags for EL0 pauth traps
According to ARM ARM we should only trap from the EL1&0 regime.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: cc28fc30e333dc2f20ebfde54444697e26cd8f6d
https://github.com/qemu/qemu/commit/cc28fc30e333dc2f20ebfde54444697e26cd8f6d
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate-a64.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Update get_a64_user_mem_index for VHE
The EL2&0 translation regime is affected by Load Register (unpriv).
The code structure used here will facilitate later changes in this
area for implementing UAO and NV.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: cb092fbbaeb7b4e91b3f9c53150c8160f91577c7
https://github.com/qemu/qemu/commit/cb092fbbaeb7b4e91b3f9c53150c8160f91577c7
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE
When VHE is enabled, the exception level below EL2 is not EL1,
but EL0, and so to identify the entry vector offset for exceptions
targeting EL2 we need to look at the width of EL0, not of EL1.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: cd3f80aba0c559a6291f7c3e686422b15381f6b7
https://github.com/qemu/qemu/commit/cd3f80aba0c559a6291f7c3e686422b15381f6b7
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable ARMv8.1-VHE in -cpu max
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 310cedf39dea240a89f90729fd99481ff6158e90
https://github.com/qemu/qemu/commit/310cedf39dea240a89f90729fd99481ff6158e90
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
Log Message:
-----------
target/arm: Move arm_excp_unmasked to cpu.c
This inline function has one user in cpu.c, and need not be exposed
otherwise. Code movement only, with fixups for checkpatch.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: be87955687446be152f366af543c9234eab78a7c
https://github.com/qemu/qemu/commit/be87955687446be152f366af543c9234eab78a7c
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Pass more cpu state to arm_excp_unmasked
Avoid redundant computation of cpu state by passing it in
from the caller, which has already computed it for itself.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 16e07f78df002067bc4bfb115ba1ee0ce278e9e5
https://github.com/qemu/qemu/commit/16e07f78df002067bc4bfb115ba1ee0ce278e9e5
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Use bool for unmasked in arm_excp_unmasked
The value computed is fully boolean; using int8_t is odd.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d63d0ec59d87a698de5ed843288f90a23470cf2e
https://github.com/qemu/qemu/commit/d63d0ec59d87a698de5ed843288f90a23470cf2e
Author: Richard Henderson <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Raise only one interrupt in arm_cpu_exec_interrupt
The fall through organization of this function meant that we
would raise an interrupt, then might overwrite that with another.
Since interrupt prioritization is IMPLEMENTATION DEFINED, we
can recognize these in any order we choose.
Unify the code to raise the interrupt in a block at the end.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: eb87ff05eab2a39bc0fcd8b4ec51433c4e7fbe42
https://github.com/qemu/qemu/commit/eb87ff05eab2a39bc0fcd8b4ec51433c4e7fbe42
Author: Rene Stange <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M hw/dma/bcm2835_dma.c
Log Message:
-----------
bcm2835_dma: Fix the ylen loop in TD mode
In TD (two dimensions) DMA mode ylen has to be increased by one after
reading it from the TXFR_LEN register, because a value of zero has to
result in one run through of the ylen loop. This has been tested on a
real Raspberry Pi 3 Model B+. In the previous implementation the ylen
loop was not passed at all for a value of zero.
Signed-off-by: Rene Stange <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 25437c09d7c46dea4a87dcff6642ce786fe14d28
https://github.com/qemu/qemu/commit/25437c09d7c46dea4a87dcff6642ce786fe14d28
Author: Rene Stange <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M hw/dma/bcm2835_dma.c
Log Message:
-----------
bcm2835_dma: Re-initialize xlen in TD mode
TD (two dimensions) DMA mode did not work, because the xlen variable
has not been re-initialized before each additional ylen run through
in bcm2835_dma_update(). Fix it.
Signed-off-by: Rene Stange <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: fa3236a970b6ea5be3fa3ad258f1a75920ca1ebb
https://github.com/qemu/qemu/commit/fa3236a970b6ea5be3fa3ad258f1a75920ca1ebb
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M docs/arm-cpu-features.rst
Log Message:
-----------
docs/arm-cpu-features: Make kvm-no-adjvtime comment clearer
The bold text sounds like 'knock knock'. Only bolding the
second 'not' makes it easier to read.
Fixes: dea101a1ae
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f3a508eb4e5b486f0d6e8a16dbd8ff4b9dafcd72
https://github.com/qemu/qemu/commit/f3a508eb4e5b486f0d6e8a16dbd8ff4b9dafcd72
Author: Pan Nengyuan <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M hw/timer/armv7m_systick.c
Log Message:
-----------
armv7m_systick: delay timer_new to avoid memleaks
There is a memory leak when we call 'device_list_properties' with typename =
armv7m_systick. It's easy to reproduce as follow:
virsh qemu-monitor-command vm1 --pretty '{"execute":
"device-list-properties", "arguments": {"typename": "armv7m_systick"}}'
This patch delay timer_new to fix this memleaks.
Reported-by: Euler Robot <address@hidden>
Signed-off-by: Pan Nengyuan <address@hidden>
Message-id: address@hidden
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 53b95da1607072bc4727cbdb48a83e4befe282b4
https://github.com/qemu/qemu/commit/53b95da1607072bc4727cbdb48a83e4befe282b4
Author: Pan Nengyuan <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M hw/timer/stm32f2xx_timer.c
Log Message:
-----------
stm32f2xx_timer: delay timer_new to avoid memleaks
There is a memory leak when we call 'device_list_properties' with typename =
stm32f2xx_timer. It's easy to reproduce as follow:
virsh qemu-monitor-command vm1 --pretty '{"execute":
"device-list-properties", "arguments": {"typename": "stm32f2xx_timer"}}'
This patch delay timer_new to fix this memleaks.
Reported-by: Euler Robot <address@hidden>
Signed-off-by: Pan Nengyuan <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Cc: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: af6c91b490e9b1bce7a168f8a9c848f3e60f616e
https://github.com/qemu/qemu/commit/af6c91b490e9b1bce7a168f8a9c848f3e60f616e
Author: Pan Nengyuan <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M hw/arm/stellaris.c
Log Message:
-----------
stellaris: delay timer_new to avoid memleaks
There is a memory leak when we call 'device_list_properties' with typename =
stellaris-gptm. It's easy to reproduce as follow:
virsh qemu-monitor-command vm1 --pretty '{"execute":
"device-list-properties", "arguments": {"typename": "stellaris-gptm"}}'
This patch delay timer_new in realize to fix it.
Reported-by: Euler Robot <address@hidden>
Signed-off-by: Pan Nengyuan <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 93c86fff53a267f657e79ec07dcd04b63882e330
https://github.com/qemu/qemu/commit/93c86fff53a267f657e79ec07dcd04b63882e330
Author: Peter Maydell <address@hidden>
Date: 2020-02-07 (Fri, 07 Feb 2020)
Changed paths:
M docs/arm-cpu-features.rst
M hw/arm/stellaris.c
M hw/dma/bcm2835_dma.c
M hw/timer/armv7m_systick.c
M hw/timer/stm32f2xx_timer.c
M target/arm/cpu-param.h
M target/arm/cpu-qom.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/debug_helper.c
M target/arm/helper-a64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/monitor.c
M target/arm/pauth_helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200207'
into staging
target-arm queue:
* monitor: fix query-cpu-model-expansion crash when using machine type none
* Support emulation of the ARMv8.1-VHE architecture feature
* bcm2835_dma: fix bugs in TD mode handling
* docs/arm-cpu-features: Make kvm-no-adjvtime comment clearer
* stellaris, stm32f2xx_timer, armv7m_systick: fix minor memory leaks
# gpg: Signature made Fri 07 Feb 2020 14:32:28 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200207: (48 commits)
stellaris: delay timer_new to avoid memleaks
stm32f2xx_timer: delay timer_new to avoid memleaks
armv7m_systick: delay timer_new to avoid memleaks
docs/arm-cpu-features: Make kvm-no-adjvtime comment clearer
bcm2835_dma: Re-initialize xlen in TD mode
bcm2835_dma: Fix the ylen loop in TD mode
target/arm: Raise only one interrupt in arm_cpu_exec_interrupt
target/arm: Use bool for unmasked in arm_excp_unmasked
target/arm: Pass more cpu state to arm_excp_unmasked
target/arm: Move arm_excp_unmasked to cpu.c
target/arm: Enable ARMv8.1-VHE in -cpu max
target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE
target/arm: Update get_a64_user_mem_index for VHE
target/arm: check TGE and E2H flags for EL0 pauth traps
target/arm: Update {fp,sve}_exception_el for VHE
target/arm: Update arm_phys_excp_target_el for TGE
target/arm: Flush tlbs for E2&0 translation regime
target/arm: Flush tlb for ASID changes in EL2&0 translation regime
target/arm: Add VHE timer register redirection and aliasing
target/arm: Add VHE system register redirection and aliasing
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/42ccca1bd945...93c86fff53a2
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