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[Qemu-commits] [qemu/qemu] b1c8c5: ppc/pnv: use QEMU unit definition MiB


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] b1c8c5: ppc/pnv: use QEMU unit definition MiB
Date: Mon, 03 Feb 2020 02:45:18 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: b1c8c522f457e3f7f30a2c169ef1ebab87f98ded
      
https://github.com/qemu/qemu/commit/b1c8c522f457e3f7f30a2c169ef1ebab87f98ded
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/ppc/pnv_pnor.c

  Log Message:
  -----------
  ppc/pnv: use QEMU unit definition MiB

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3cf4aac0deca8fd58d16dcd64d25821f1521df2b
      
https://github.com/qemu/qemu/commit/3cf4aac0deca8fd58d16dcd64d25821f1521df2b
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/ppc/pnv_pnor.c

  Log Message:
  -----------
  ppc/pnv: improve error logging when a PNOR update fails

Print out the offset at which the error occured.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 79a87336508b7c4c0047f92e0fab681359b816d4
      
https://github.com/qemu/qemu/commit/79a87336508b7c4c0047f92e0fab681359b816d4
  Author: Igor Mammedov <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/ppc/virtex_ml507.c

  Log Message:
  -----------
  ppc:virtex_ml507: remove unused arguments

Signed-off-by: Igor Mammedov <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b2ce76a0730e48e60633a698cd876d55917ac9bc
      
https://github.com/qemu/qemu/commit/b2ce76a0730e48e60633a698cd876d55917ac9bc
  Author: Thomas Huth <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M .gitmodules
    M MAINTAINERS
    M Makefile
    M docs/interop/firmware.json
    M hw/ppc/ppc.c
    M hw/ppc/prep.c
    M include/hw/ppc/ppc.h
    M pc-bios/README
    R pc-bios/ppc_rom.bin
    M qemu-deprecated.texi
    M qemu-doc.texi
    R roms/openhackware
    M tests/qtest/boot-order-test.c
    M tests/qtest/cdrom-test.c
    M tests/qtest/endianness-test.c

  Log Message:
  -----------
  hw/ppc/prep: Remove the deprecated "prep" machine and the OpenHackware BIOS

It's been deprecated since QEMU v3.1. The 40p machine should be
used nowadays instead.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Hervé Poussineau <address@hidden>
Signed-off-by: Thomas Huth <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6e0552a3a7d4e340a06372d79a27e4d89812d241
      
https://github.com/qemu/qemu/commit/6e0552a3a7d4e340a06372d79a27e4d89812d241
  Author: Fabiano Rosas <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M target/ppc/kvm.c

  Log Message:
  -----------
  target/ppc: Clarify the meaning of return values in kvm_handle_debug

The kvm_handle_debug function can return 0 to go back into the guest
or return 1 to notify the gdbstub thread and pass control to GDB.

Signed-off-by: Fabiano Rosas <address@hidden>
Message-Id: <address@hidden>
Tested-by: Leonardo Bras <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: cbd0d7f36322ff8e2c9b625672ab1dafe0dc1712
      
https://github.com/qemu/qemu/commit/cbd0d7f36322ff8e2c9b625672ab1dafe0dc1712
  Author: Greg Kurz <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/ppc/spapr_hcall.c

  Log Message:
  -----------
  spapr: Fail CAS if option vector table cannot be parsed

Most of the option vector helpers have assertions to check their
arguments aren't null. The guest can provide an arbitrary address
for the CAS structure that would result in such null arguments.
Fail CAS with H_PARAMETER and print a warning instead of aborting
QEMU.

Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5ba7ba1da096de0b70f65c08df5584a4878012e7
      
https://github.com/qemu/qemu/commit/5ba7ba1da096de0b70f65c08df5584a4878012e7
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M target/ppc/excp_helper.c
    M target/ppc/helper.h
    M target/ppc/misc_helper.c
    M target/ppc/translate.c
    M target/ppc/translate_init.inc.c

  Log Message:
  -----------
  target/ppc: Add privileged message send facilities

The Processor Control facility for POWER8 processors and later
provides a mechanism for the hypervisor to send messages to other
threads in the system (msgsnd instruction) and cause hypervisor-level
exceptions. Privileged non-hypervisor programs can also send messages
(msgsndp instruction) but are restricted to the threads of the same
subprocessor and cause privileged-level exceptions.

The Directed Privileged Doorbell Exception State (DPDES) register
reflects the state of pending privileged doorbell exceptions and can
be used to modify that state. The register can be used to read and
modify the state of privileged doorbell exceptions for all threads of
a subprocessor and thus is a shared facility for that subprocessor.
The register can be read/written by the hypervisor and read by the
supervisor if enabled in the HFSCR, otherwise a hypervisor facility
unavailable exception is generated.

The privileged message send and clear instructions (msgsndp & msgclrp)
are used to generate and clear the presence of a directed privileged
doorbell exception, respectively. The msgsndp instruction can be used
to target any thread of the current subprocessor, msgclrp acts on the
thread issuing the instruction. These instructions are privileged, but
will generate a hypervisor facility unavailable exception if not
enabled in the HFSCR and executed in privileged non-hypervisor
state. The HV facility unavailable exception will be addressed in
other patch.

Add and implement this register and instructions by reading or
modifying the pending interrupt state of the cpu.

Note that TCG only supports one thread per core and so we only need to
worry about the cpu making the access.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 493028d8d798f4ac7b933c91598605acd7e61c7e
      
https://github.com/qemu/qemu/commit/493028d8d798f4ac7b933c91598605acd7e61c7e
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/excp_helper.c
    M target/ppc/misc_helper.c

  Log Message:
  -----------
  target/ppc: add support for Hypervisor Facility Unavailable Exception

The privileged message send and clear instructions (msgsndp & msgclrp)
are privileged, but will generate a hypervisor facility unavailable
exception if not enabled in the HFSCR and executed in privileged
non-hypervisor state.

Add checks when accessing the DPDES register and when using the
msgsndp and msgclrp isntructions.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 12b3868eadf0d5c5ada24f7036c55de7943575a9
      
https://github.com/qemu/qemu/commit/12b3868eadf0d5c5ada24f7036c55de7943575a9
  Author: Greg Kurz <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/ppc/spapr_hcall.c

  Log Message:
  -----------
  spapr: Don't allow multiple active vCPUs at CAS

According to the description of "ibm,client-architecture-support" that
can found in LoPAPR "B.6.2.3 Root Node Methods":

If multiple partition processors or threads are active at the time of
the ibm,client-architecture-support method call, or an error is detected
in the format of the ibm,architecture.vec structure, the err? boolean
shall be TRUE; else FALSE.

We certainly don't want to temper with the platform or with the PCR of
the other vCPUs if they happen to be active. Ensure we have only one
active vCPU and fail CAS otherwise. This is just for conformance and
robustness, it doesn't fix any known bugs.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a9ec49af3b2a5a83004d1766bf7a4b4f63f7c8a6
      
https://github.com/qemu/qemu/commit/a9ec49af3b2a5a83004d1766bf7a4b4f63f7c8a6
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M target/ppc/mmu-radix64.c

  Log Message:
  -----------
  ppc/pnv: Add support for HRMOR on Radix host

When in HV mode, if EA[0] is 0, the Hypervisor Offset Real Mode
Register controls the access.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 59942f0ebbdae67640bfa964c7745e88a80c35a0
      
https://github.com/qemu/qemu/commit/59942f0ebbdae67640bfa964c7745e88a80c35a0
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/ppc/pnv_core.c

  Log Message:
  -----------
  ppc/pnv: remove useless "core-pir" property alias.

Commit 158e17a65e1a ("ppc/pnv: Link "chip" property to PnvCore::chip
pointer") introduced some cleanups of the PnvCore realize handler.
Let's continue by reworking a bit the interface of the PnvCore
handlers for the CPU threads. These changes make the "core-pir"
property alias unused. Remove it.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 08c3f3a734dae32497d526e26522d75f85d6368e
      
https://github.com/qemu/qemu/commit/08c3f3a734dae32497d526e26522d75f85d6368e
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/ppc/pnv.c
    M hw/ppc/pnv_core.c
    M hw/ppc/pnv_lpc.c
    M include/hw/ppc/pnv.h
    M include/hw/ppc/pnv_core.h

  Log Message:
  -----------
  ppc/pnv: Add support for "hostboot" mode

When the "hb-mode" option is activated on the powernv machine, the
firmware is mapped at 0x8000000 and the HRMOR of the HW threads are
set to the same address.

The PNOR mapping on the FW address space of the LPC bus is left enabled
to let the firmware load any other images required to boot the host.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3688d73b6e2b7b3fb71ed9fb6e38fd05d39de05b
      
https://github.com/qemu/qemu/commit/3688d73b6e2b7b3fb71ed9fb6e38fd05d39de05b
  Author: Stefan Berger <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/tpm/tpm_tis.c
    M hw/tpm/tpm_util.c
    M hw/tpm/tpm_util.h
    M hw/tpm/trace-events

  Log Message:
  -----------
  tpm: Move tpm_tis_show_buffer to tpm_util.c

Signed-off-by: Stefan Berger <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 864674fa29ab61681b8c72c3c41251e985daabed
      
https://github.com/qemu/qemu/commit/864674fa29ab61681b8c72c3c41251e985daabed
  Author: Stefan Berger <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/ppc/spapr_vio.c
    M include/hw/ppc/spapr_vio.h

  Log Message:
  -----------
  spapr: Implement get_dt_compatible() callback

For devices that cannot be statically initialized, implement a
get_dt_compatible() callback that allows us to ask the device for
the 'compatible' value.

Signed-off-by: Stefan Berger <address@hidden>
Reviewed-by: Marc-André Lureau <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3676bc69b358d84a6b32d9cd44325048659a32a2
      
https://github.com/qemu/qemu/commit/3676bc69b358d84a6b32d9cd44325048659a32a2
  Author: Stefan Berger <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M docs/specs/tpm.txt
    M hw/tpm/Kconfig
    M hw/tpm/Makefile.objs
    A hw/tpm/tpm_spapr.c
    M hw/tpm/trace-events
    M include/sysemu/tpm.h
    M qapi/tpm.json

  Log Message:
  -----------
  tpm_spapr: Support TPM for ppc64 using CRQ based interface

Implement support for TPM on ppc64 by implementing the vTPM CRQ interface
as a frontend. It can use the tpm_emulator driver backend with the external
swtpm.

The Linux vTPM driver for ppc64 works with this emulation.

This TPM emulator also handles the TPM 2 case.

Signed-off-by: Stefan Berger <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
[dwg: Use device_class_set_props(), tweak Kconfig]
Signed-off-by: David Gibson <address@hidden>


  Commit: ee9a8129d3d975271d4efed1b37b7dac956e7bf5
      
https://github.com/qemu/qemu/commit/ee9a8129d3d975271d4efed1b37b7dac956e7bf5
  Author: Stefan Berger <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/tpm/tpm_spapr.c
    M hw/tpm/trace-events

  Log Message:
  -----------
  tpm_spapr: Support suspend and resume

Extend the tpm_spapr frontend with VM suspend and resume support.

Signed-off-by: Stefan Berger <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Marc-André Lureau <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 942e7954c845a842b820b3cf6b7e7bb73d788284
      
https://github.com/qemu/qemu/commit/942e7954c845a842b820b3cf6b7e7bb73d788284
  Author: Stefan Berger <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/tpm/Kconfig

  Log Message:
  -----------
  hw/ppc/Kconfig: Enable TPM_SPAPR as part of PSERIES config

Signed-off-by: Stefan Berger <address@hidden>
Reviewed-by: Marc-André Lureau <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
[dwg: Use default in Kconfig rather than select to avoid breaking
 Windows host build]
Signed-off-by: David Gibson <address@hidden>


  Commit: 6e8a3ff6ed88c353b30a356411694cb3fea9c607
      
https://github.com/qemu/qemu/commit/6e8a3ff6ed88c353b30a356411694cb3fea9c607
  Author: Marc-André Lureau <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M docs/specs/index.rst
    A docs/specs/tpm.rst
    R docs/specs/tpm.txt

  Log Message:
  -----------
  docs/specs/tpm: reST-ify TPM documentation

Signed-off-by: Marc-André Lureau <address@hidden>
Reviewed-by: Stefan Berger <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4f9924c4d4cf9c039e247c5cdbbf71bce4e573c3
      
https://github.com/qemu/qemu/commit/4f9924c4d4cf9c039e247c5cdbbf71bce4e573c3
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/pci-host/Makefile.objs
    A hw/pci-host/pnv_phb4.c
    A hw/pci-host/pnv_phb4_pec.c
    M hw/ppc/Kconfig
    M hw/ppc/pnv.c
    A include/hw/pci-host/pnv_phb4.h
    A include/hw/pci-host/pnv_phb4_regs.h
    M include/hw/pci/pcie_port.h
    M include/hw/ppc/pnv.h
    M include/hw/ppc/pnv_xscom.h

  Log Message:
  -----------
  ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge

These changes introduces models for the PCIe Host Bridge (PHB4) of the
POWER9 processor. It includes the PowerBus logic interface (PBCQ),
IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI
and LSI interrupt sources as found on a POWER9 system using the XIVE
interrupt controller.

POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs. By default,

  * PEC0 provides 1 PHB  (PHB0)
  * PEC1 provides 2 PHBs (PHB1 and PHB2)
  * PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)

Each PEC has a set  "global" registers and some "per-stack" (per-PHB)
registers. Those are organized in two XSCOM ranges, the "Nest" range
and the "PCI" range, each range contains both some "PEC" registers and
some "per-stack" registers.

No default device layout is provided and PCI devices can be added on
any of the available PCIe Root Port (pcie.0 .. 2 of a Power9 chip)
with address 0x0 as the firwware (skiboot) only accepts a single
device per root port. To run a simple system with a network and a
storage adapters, use a command line options such as :

  -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0
  -netdev 
bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0

  -device megasas,id=scsi0,bus=pcie.1,addr=0x0
  -drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none
  -device 
scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2

If more are needed, include a bridge.

Multi chip is supported, each chip adding its set of PHB4 controllers
and its PCI busses. The model doesn't emulate the EEH error handling.

This model is not ready for hotplug yet.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[ clg: - numerous cleanups
       - commit log
       - fix for broken LSI support
       - PHB pic printinfo
       - large QOM rework ]
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
[dwg: Use device_class_set_props()]
Signed-off-by: David Gibson <address@hidden>


  Commit: 9ae1329ee2fee95f201ca219090d7c742eaf6a90
      
https://github.com/qemu/qemu/commit/9ae1329ee2fee95f201ca219090d7c742eaf6a90
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/intc/xics.c
    M hw/pci-host/Makefile.objs
    A hw/pci-host/pnv_phb3.c
    A hw/pci-host/pnv_phb3_msi.c
    A hw/pci-host/pnv_phb3_pbcq.c
    M hw/ppc/pnv.c
    A include/hw/pci-host/pnv_phb3.h
    A include/hw/pci-host/pnv_phb3_regs.h
    M include/hw/ppc/pnv.h
    M include/hw/ppc/pnv_xscom.h
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridge

This is a model of the PCIe Host Bridge (PHB3) found on a POWER8
processor. It includes the PowerBus logic interface (PBCQ), IOMMU
support, a single PCIe Gen.3 Root Complex, and support for MSI and LSI
interrupt sources as found on a POWER8 system using the XICS interrupt
controller.

The POWER8 processor comes in different flavors: Venice, Murano,
Naple, each having a different number of PHBs. To make things simpler,
the models provides 3 PHB3 per chip. Some platforms, like the
Firestone, can also couple PHBs on the first chip to provide more
bandwidth but this is too specific to model in QEMU.

XICS requires some adjustment to support the PHB3 MSI. The changes are
provided here but they could be decoupled in prereq patches.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
[dwg: Use device_class_set_props()]
Signed-off-by: David Gibson <address@hidden>


  Commit: 23a782eb6670624f993a66a3c49866fe3cff4727
      
https://github.com/qemu/qemu/commit/23a782eb6670624f993a66a3c49866fe3cff4727
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-02-02 (Sun, 02 Feb 2020)

  Changed paths:
    M hw/pci-host/pnv_phb3.c
    M hw/pci-host/pnv_phb3_pbcq.c
    M hw/pci-host/pnv_phb4.c
    M hw/pci-host/pnv_phb4_pec.c
    M hw/ppc/pnv_core.c
    M hw/ppc/pnv_homer.c
    M hw/ppc/pnv_lpc.c
    M hw/ppc/pnv_occ.c

  Log Message:
  -----------
  ppc/pnv: change the PowerNV machine devices to be non user creatable

The PowerNV machine emulates an OpenPOWER system and the PowerNV chip
devices are models of the internal logic of the POWER processor. They
can not be instantiated by the user on the QEMU command line.

The PHB3/PHB4 devices could be an exception in the future after some
rework on how the device tree is built. For the moment, exclude them
also.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Tested-by: Thomas Huth <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 37965dfe4dffa3ac49438337417608e7f346b58a
      
https://github.com/qemu/qemu/commit/37965dfe4dffa3ac49438337417608e7f346b58a
  Author: David Gibson <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c

  Log Message:
  -----------
  spapr: Enable DD2.3 accelerated count cache flush in pseries-5.0 machine

For POWER9 DD2.2 cpus, the best current Spectre v2 indirect branch
mitigation is "count cache disabled", which is configured with:
    -machine cap-ibs=fixed-ccd
However, this option isn't available on DD2.3 CPUs with KVM, because they
don't have the count cache disabled.

For POWER9 DD2.3 cpus, it is "count cache flush with assist", configured
with:
    -machine cap-ibs=workaround,cap-ccf-assist=on
However this option isn't available on DD2.2 CPUs with KVM, because they
don't have the special CCF assist instruction this relies on.

On current machine types, we default to "count cache flush w/o assist",
that is:
    -machine cap-ibs=workaround,cap-ccf-assist=off
This runs, with mitigation on both DD2.2 and DD2.3 host cpus, but has a
fairly significant performance impact.

It turns out we can do better.  The special instruction that CCF assist
uses to trigger a count cache flush is a no-op on earlier CPUs, rather than
trapping or causing other badness.  It doesn't, of itself, implement the
mitigation, but *if* we have count-cache-disabled, then the count cache
flush is unnecessary, and so using the count cache flush mitigation is
harmless.

Therefore for the new pseries-5.0 machine type, enable cap-ccf-assist by
default.  Along with that, suppress throwing an error if cap-ccf-assist
is selected but KVM doesn't support it, as long as KVM *is* giving us
count-cache-disabled.  To allow TCG to work out of the box, even though it
doesn't implement the ccf flush assist, downgrade the error in that case to
a warning.  This matches several Spectre mitigations where we allow TCG
to operate for debugging, since we don't really make guarantees about TCG
security properties anyway.

While we're there, make the TCG warning for this case match that for other
mitigations.

Signed-off-by: David Gibson <address@hidden>
Tested-by: Michael Ellerman <address@hidden>


  Commit: 254581039e9fd5e72e4ecbbcd881f8c85c164031
      
https://github.com/qemu/qemu/commit/254581039e9fd5e72e4ecbbcd881f8c85c164031
  Author: BALATON Zoltan <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M target/ppc/cpu.h

  Log Message:
  -----------
  target/ppc/cpu.h: Put macro parameter in parentheses

Fix PPC_INPUT macro to work with more complex expressions by
protecting its argument with parentheses.

Signed-off-by: BALATON Zoltan <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 19e067e032232b098a999dab15c6f0c8039114bd
      
https://github.com/qemu/qemu/commit/19e067e032232b098a999dab15c6f0c8039114bd
  Author: Aravinda Prasad <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M cpus.c
    M include/qemu/main-loop.h

  Log Message:
  -----------
  Wrapper function to wait on condition for the main loop mutex

Introduce a wrapper function to wait on condition for
the main loop mutex. This function atomically releases
the main loop mutex and causes the calling thread to
block on the condition. This wrapper is required because
qemu_global_mutex is a static variable.

Signed-off-by: Aravinda Prasad <address@hidden>
Signed-off-by: Ganesh Goudar <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9d953ce44722eeb10d99c814478065bebbf7e1f6
      
https://github.com/qemu/qemu/commit/9d953ce44722eeb10d99c814478065bebbf7e1f6
  Author: Aravinda Prasad <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M include/hw/ppc/spapr.h
    M target/ppc/kvm.c
    M target/ppc/kvm_ppc.h

  Log Message:
  -----------
  ppc: spapr: Introduce FWNMI capability

Introduce fwnmi an spapr capability and add a helper function
which tries to enable it, which would be used by following patch
of the series. This patch by itself does not change the existing
behavior.

Signed-off-by: Aravinda Prasad <address@hidden>
[eliminate cap_ppc_fwnmi, add fwnmi cap to migration state
 and reprhase the commit message]
Signed-off-by: Ganesh Goudar <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9ac703ac5f9e830ab96d38dc77061bd4be76cf60
      
https://github.com/qemu/qemu/commit/9ac703ac5f9e830ab96d38dc77061bd4be76cf60
  Author: Aravinda Prasad <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_events.c
    M include/hw/ppc/spapr.h
    M target/ppc/kvm.c
    M target/ppc/kvm_ppc.h
    M target/ppc/trace-events

  Log Message:
  -----------
  target/ppc: Handle NMI guest exit

Memory error such as bit flips that cannot be corrected
by hardware are passed on to the kernel for handling.
If the memory address in error belongs to guest then
the guest kernel is responsible for taking suitable action.
Patch [1] enhances KVM to exit guest with exit reason
set to KVM_EXIT_NMI in such cases. This patch handles
KVM_EXIT_NMI exit.

[1] https://www.spinics.net/lists/kvm-ppc/msg12637.html
    (e20bbd3d and related commits)

Signed-off-by: Aravinda Prasad <address@hidden>
Signed-off-by: Ganesh Goudar <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
[dwg: #ifdefs to fix compile for 32-bit target]
Signed-off-by: David Gibson <address@hidden>


  Commit: 81fe70e443ef7e3b5e8f2e30336029ed5b968741
      
https://github.com/qemu/qemu/commit/81fe70e443ef7e3b5e8f2e30336029ed5b968741
  Author: Aravinda Prasad <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_rtas.c
    M include/hw/ppc/spapr.h
    M target/ppc/kvm.c

  Log Message:
  -----------
  target/ppc: Build rtas error log upon an MCE

Upon a machine check exception (MCE) in a guest address space,
KVM causes a guest exit to enable QEMU to build and pass the
error to the guest in the PAPR defined rtas error log format.

This patch builds the rtas error log, copies it to the rtas_addr
and then invokes the guest registered machine check handler. The
handler in the guest takes suitable action(s) depending on the type
and criticality of the error. For example, if an error is
unrecoverable memory corruption in an application inside the
guest, then the guest kernel sends a SIGBUS to the application.
For recoverable errors, the guest performs recovery actions and
logs the error.

Signed-off-by: Aravinda Prasad <address@hidden>
[Assume SLOF has allocated enough room for rtas error log]
Signed-off-by: Ganesh Goudar <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f03496bc123df4d5a595fd4aa2113786c313e41e
      
https://github.com/qemu/qemu/commit/f03496bc123df4d5a595fd4aa2113786c313e41e
  Author: Aravinda Prasad <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M hw/ppc/spapr_caps.c
    M hw/ppc/spapr_rtas.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  ppc: spapr: Handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS calls

This patch adds support in QEMU to handle "ibm,nmi-register"
and "ibm,nmi-interlock" RTAS calls.

The machine check notification address is saved when the
OS issues "ibm,nmi-register" RTAS call.

This patch also handles the case when multiple processors
experience machine check at or about the same time by
handling "ibm,nmi-interlock" call. In such cases, as per
PAPR, subsequent processors serialize waiting for the first
processor to issue the "ibm,nmi-interlock" call. The second
processor that also received a machine check error waits
till the first processor is done reading the error log.
The first processor issues "ibm,nmi-interlock" call
when the error log is consumed.

Signed-off-by: Aravinda Prasad <address@hidden>
[Register fwnmi RTAS calls in core_rtas_register_types()
 where other RTAS calls are registered]
Signed-off-by: Ganesh Goudar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2500fb423adb17995485de0b4d507cf2f09e3a7f
      
https://github.com/qemu/qemu/commit/2500fb423adb17995485de0b4d507cf2f09e3a7f
  Author: Aravinda Prasad <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_rtas.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  migration: Include migration support for machine check handling

This patch includes migration support for machine check
handling. Especially this patch blocks VM migration
requests until the machine check error handling is
complete as these errors are specific to the source
hardware and is irrelevant on the target hardware.

Signed-off-by: Aravinda Prasad <address@hidden>
[Do not set FWNMI cap in post_load, now its done in .apply hook]
Signed-off-by: Ganesh Goudar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e0aeef7a3532a7abe921ea96c6a1e974f2ab1fa1
      
https://github.com/qemu/qemu/commit/e0aeef7a3532a7abe921ea96c6a1e974f2ab1fa1
  Author: Aravinda Prasad <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  ppc: spapr: Activate the FWNMI functionality

This patch sets the default value of SPAPR_CAP_FWNMI_MCE
to SPAPR_CAP_ON for machine type 5.0.

Signed-off-by: Aravinda Prasad <address@hidden>
Signed-off-by: Ganesh Goudar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: bb99b391896f3c7a477777e3d47a2524fd795357
      
https://github.com/qemu/qemu/commit/bb99b391896f3c7a477777e3d47a2524fd795357
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M target/ppc/mem_helper.c

  Log Message:
  -----------
  target/ppc: Use probe_access for LSW, STSW

Use a minimum number of mmu lookups for the contiguous bytes
that are accessed.  If the lookup succeeds, we can finish the
operation with host addresses only.

Reported-by: Howard Spoelstra <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Tested-by: Howard Spoelstra <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2ca2ef49940de375696074f36c977af9fd414e25
      
https://github.com/qemu/qemu/commit/2ca2ef49940de375696074f36c977af9fd414e25
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M target/ppc/mem_helper.c

  Log Message:
  -----------
  target/ppc: Use probe_access for LMW, STMW

Use a minimum number of mmu lookups for the contiguous bytes
that are accessed.  If the lookup succeeds, we can finish the
operation with host addresses only.

Reported-by: Howard Spoelstra <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Tested-by: Howard Spoelstra <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1cbddf6d944e13efe95e3d4a7726e474e4bac252
      
https://github.com/qemu/qemu/commit/1cbddf6d944e13efe95e3d4a7726e474e4bac252
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M target/ppc/mem_helper.c

  Log Message:
  -----------
  target/ppc: Remove redundant mask in DCBZ

The value of addr has already been masked, just above.

Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Tested-by: Howard Spoelstra <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4dcf078f094d436866ef793aa25c96fba85ac8d0
      
https://github.com/qemu/qemu/commit/4dcf078f094d436866ef793aa25c96fba85ac8d0
  Author: Richard Henderson <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M target/ppc/mem_helper.c

  Log Message:
  -----------
  target/ppc: Use probe_write for DCBZ

Using probe_write instead of tlb_vaddr_to_host means that we
process watchpoints and notdirty pages more efficiently.

Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Tested-by: Howard Spoelstra <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 63d57c8f91d0d0e62fc4d91db6340a662b36a3c0
      
https://github.com/qemu/qemu/commit/63d57c8f91d0d0e62fc4d91db6340a662b36a3c0
  Author: Greg Kurz <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M tests/qtest/boot-serial-test.c
    M tests/qtest/libqos/libqos-spapr.h
    M tests/qtest/prom-env-test.c
    M tests/qtest/pxe-test.c

  Log Message:
  -----------
  tests: Silence various warnings with pseries

Some default features of the pseries machine are only available with
KVM. Warnings are printed when the pseries machine is used with another
accelerator:

qemu-system-ppc64: warning: TCG doesn't support requested feature,
cap-ccf-assist=on
qemu-system-ppc64: warning: Firmware Assisted Non-Maskable
Interrupts(FWNMI) not supported in TCG
qemu-system-ppc64: warning: TCG doesn't support requested feature,
cap-ccf-assist=on
qemu-system-ppc64: warning: Firmware Assisted Non-Maskable
Interrupts(FWNMI) not supported in TCG
qemu-system-ppc64: warning: TCG doesn't support requested feature,
cap-ccf-assist=on
qemu-system-ppc64: warning: Firmware Assisted Non-Maskable
Interrupts(FWNMI) not supported in TCG

This is annoying for CI since it usually runs without KVM. We already
disable features that emit similar warnings thanks to properties of
the pseries machine, but this is open-coded in various
places. Consolidate the set of properties in a single place. Extend it
to silence the above warnings. And use it in the various tests that
start pseries machines.

Reported-by: Peter Maydell <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
[dwg: Correct minor grammatical error]
Signed-off-by: David Gibson <address@hidden>


  Commit: 035b21977ce1791a630c5cbf46e482e54552e05b
      
https://github.com/qemu/qemu/commit/035b21977ce1791a630c5cbf46e482e54552e05b
  Author: Peter Maydell <address@hidden>
  Date:   2020-02-03 (Mon, 03 Feb 2020)

  Changed paths:
    M .gitmodules
    M MAINTAINERS
    M Makefile
    M cpus.c
    M docs/interop/firmware.json
    M docs/specs/index.rst
    A docs/specs/tpm.rst
    R docs/specs/tpm.txt
    M hw/intc/xics.c
    M hw/pci-host/Makefile.objs
    A hw/pci-host/pnv_phb3.c
    A hw/pci-host/pnv_phb3_msi.c
    A hw/pci-host/pnv_phb3_pbcq.c
    A hw/pci-host/pnv_phb4.c
    A hw/pci-host/pnv_phb4_pec.c
    M hw/ppc/Kconfig
    M hw/ppc/pnv.c
    M hw/ppc/pnv_core.c
    M hw/ppc/pnv_homer.c
    M hw/ppc/pnv_lpc.c
    M hw/ppc/pnv_occ.c
    M hw/ppc/pnv_pnor.c
    M hw/ppc/ppc.c
    M hw/ppc/prep.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_hcall.c
    M hw/ppc/spapr_rtas.c
    M hw/ppc/spapr_vio.c
    M hw/ppc/virtex_ml507.c
    M hw/tpm/Kconfig
    M hw/tpm/Makefile.objs
    A hw/tpm/tpm_spapr.c
    M hw/tpm/tpm_tis.c
    M hw/tpm/tpm_util.c
    M hw/tpm/tpm_util.h
    M hw/tpm/trace-events
    A include/hw/pci-host/pnv_phb3.h
    A include/hw/pci-host/pnv_phb3_regs.h
    A include/hw/pci-host/pnv_phb4.h
    A include/hw/pci-host/pnv_phb4_regs.h
    M include/hw/pci/pcie_port.h
    M include/hw/ppc/pnv.h
    M include/hw/ppc/pnv_core.h
    M include/hw/ppc/pnv_xscom.h
    M include/hw/ppc/ppc.h
    M include/hw/ppc/spapr.h
    M include/hw/ppc/spapr_vio.h
    M include/hw/ppc/xics.h
    M include/qemu/main-loop.h
    M include/sysemu/tpm.h
    M pc-bios/README
    R pc-bios/ppc_rom.bin
    M qapi/tpm.json
    M qemu-deprecated.texi
    M qemu-doc.texi
    R roms/openhackware
    M target/ppc/cpu.h
    M target/ppc/excp_helper.c
    M target/ppc/helper.h
    M target/ppc/kvm.c
    M target/ppc/kvm_ppc.h
    M target/ppc/mem_helper.c
    M target/ppc/misc_helper.c
    M target/ppc/mmu-radix64.c
    M target/ppc/trace-events
    M target/ppc/translate.c
    M target/ppc/translate_init.inc.c
    M tests/qtest/boot-order-test.c
    M tests/qtest/boot-serial-test.c
    M tests/qtest/cdrom-test.c
    M tests/qtest/endianness-test.c
    M tests/qtest/libqos/libqos-spapr.h
    M tests/qtest/prom-env-test.c
    M tests/qtest/pxe-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200203' into 
staging

ppc patch queue 2020-02093

This pull request supersedes ppc-for-5.0-20200131.  The only changes
are one extra patch to suppress some irritating warnings during tests
under TCG, and an extra Tested-by in one of the other patches.

Here's the next batch of patches for ppc and associated machine types.
Highlights includes:
 * Remove the deprecated "prep" machine type and its OpenHackware
   firmware
 * Add TCG emulation of the msgsndp etc. supervisor privileged
   doorbell instructions
 * Allow "pnv" machine type to run Hostboot style firmwares
 * Add a virtual TPM device for spapr machines
 * Implement devices for POWER8 PHB3 and POWER9 PHB4 host bridges for
   the pnv machine type
 * Use faster Spectre mitigation by default for POWER9 DD2.3 machines
 * Introduce Firmware Assisted NMI dump facility for spapr machines
 * Fix a performance regression with load/store multiple instructions
   in TCG

as well as some other assorted cleanups and fixes.

# gpg: Signature made Mon 03 Feb 2020 03:30:24 GMT
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>" [full]
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>" [full]
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>" 
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-5.0-20200203: (35 commits)
  tests: Silence various warnings with pseries
  target/ppc: Use probe_write for DCBZ
  target/ppc: Remove redundant mask in DCBZ
  target/ppc: Use probe_access for LMW, STMW
  target/ppc: Use probe_access for LSW, STSW
  ppc: spapr: Activate the FWNMI functionality
  migration: Include migration support for machine check handling
  ppc: spapr: Handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS calls
  target/ppc: Build rtas error log upon an MCE
  target/ppc: Handle NMI guest exit
  ppc: spapr: Introduce FWNMI capability
  Wrapper function to wait on condition for the main loop mutex
  target/ppc/cpu.h: Put macro parameter in parentheses
  spapr: Enable DD2.3 accelerated count cache flush in pseries-5.0 machine
  ppc/pnv: change the PowerNV machine devices to be non user creatable
  ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridge
  ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge
  docs/specs/tpm: reST-ify TPM documentation
  hw/ppc/Kconfig: Enable TPM_SPAPR as part of PSERIES config
  tpm_spapr: Support suspend and resume
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/28db64fce555...035b21977ce1



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