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[Qemu-commits] [qemu/qemu] 870c03: hw/misc: Add the STM32F4xx Sysconfig
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 870c03: hw/misc: Add the STM32F4xx Sysconfig device |
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Date: |
Fri, 17 Jan 2020 10:15:14 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 870c034da0be2207e1b535cb6897958556fa0380
https://github.com/qemu/qemu/commit/870c034da0be2207e1b535cb6897958556fa0380
Author: Alistair Francis <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M default-configs/arm-softmmu.mak
M hw/arm/Kconfig
M hw/misc/Kconfig
M hw/misc/Makefile.objs
A hw/misc/stm32f4xx_syscfg.c
M hw/misc/trace-events
A include/hw/misc/stm32f4xx_syscfg.h
Log Message:
-----------
hw/misc: Add the STM32F4xx Sysconfig device
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e64d8c83f929d4a0b077b7c460d09c429c6fca57
https://github.com/qemu/qemu/commit/e64d8c83f929d4a0b077b7c460d09c429c6fca57
Author: Alistair Francis <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M hw/arm/Kconfig
M hw/misc/Kconfig
M hw/misc/Makefile.objs
A hw/misc/stm32f4xx_exti.c
M hw/misc/trace-events
A include/hw/misc/stm32f4xx_exti.h
Log Message:
-----------
hw/misc: Add the STM32F4xx EXTI device
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 529fc5fd3e18ace8f739afd02dc0953354f39442
https://github.com/qemu/qemu/commit/529fc5fd3e18ace8f739afd02dc0953354f39442
Author: Alistair Francis <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M MAINTAINERS
M hw/arm/Makefile.objs
A hw/arm/stm32f405_soc.c
A include/hw/arm/stm32f405_soc.h
Log Message:
-----------
hw/arm: Add the STM32F4xx SoC
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 60d6c4278a6976ababe351e3de05fcd370158351
https://github.com/qemu/qemu/commit/60d6c4278a6976ababe351e3de05fcd370158351
Author: Alistair Francis <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M MAINTAINERS
M hw/arm/Makefile.objs
A hw/arm/netduinoplus2.c
Log Message:
-----------
hw/arm: Add the Netduino Plus 2
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: c5ce3153f30f3181648b5a6c4efc39505ee201cc
https://github.com/qemu/qemu/commit/c5ce3153f30f3181648b5a6c4efc39505ee201cc
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
tests/boot_linux_console: Add initrd test for the CubieBoard
This test boots a Linux kernel on a CubieBoard and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://docs.armbian.com/Developer-Guide_Build-Preparation/
The cpio image used comes from the linux-build-test project:
https://github.com/groeck/linux-build-test
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ avocado --show=console run -t machine:cubieboard
tests/acceptance/boot_linux_console.py
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (address@hidden) (gcc version 7.2.1
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [410fc080] revision 0 (ARMv7), cr=50c5387d
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing
instruction cache
console: OF: fdt: Machine model: Cubietech Cubieboard
[...]
console: Boot successful.
console: cat /proc/cpuinfo
console: / # cat /proc/cpuinfo
console: processor : 0
console: model name : ARMv7 Processor rev 0 (v7l)
console: BogoMIPS : 832.51
[...]
console: Hardware : Allwinner sun4i/sun5i Families
console: Revision : 0000
console: Serial : 0000000000000000
console: cat /proc/iomem
console: / # cat /proc/iomem
console: 01c00000-01c0002f : system-control@1c00000
console: 01c02000-01c02fff : dma-controller@1c02000
console: 01c05000-01c05fff : spi@1c05000
console: 01c0b080-01c0b093 : mdio@1c0b080
console: 01c0c000-01c0cfff : lcd-controller@1c0c000
console: 01c0d000-01c0dfff : lcd-controller@1c0d000
console: 01c0f000-01c0ffff : mmc@1c0f000
[...]
PASS (54.35 s)
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Wainer dos Santos Moschetta <address@hidden>
Tested-by: Wainer dos Santos Moschetta <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e33ee3097f705bd7d3ae14a177e12a4b16055970
https://github.com/qemu/qemu/commit/e33ee3097f705bd7d3ae14a177e12a4b16055970
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
tests/boot_linux_console: Add a SD card test for the CubieBoard
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://docs.armbian.com/Developer-Guide_Build-Preparation/
The cpio image used comes from the linux-build-test project:
https://github.com/groeck/linux-build-test
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ avocado --show=console run -t machine:cubieboard
tests/acceptance/boot_linux_console.py
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (address@hidden) (gcc version 7.2.1
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
[...]
console: ahci-sunxi 1c18000.sata: Linked as a consumer to regulator.4
console: ahci-sunxi 1c18000.sata: controller can't do 64bit DMA, forcing 32bit
console: ahci-sunxi 1c18000.sata: AHCI 0001.0000 32 slots 1 ports 1.5 Gbps
0x1 impl platform mode
console: ahci-sunxi 1c18000.sata: flags: ncq only
console: scsi host0: ahci-sunxi
console: ata1: SATA max UDMA/133 mmio [mem 0x01c18000-0x01c18fff] port 0x100
irq 27
console: of_cfs_init
console: of_cfs_init: OK
console: vcc3v0: disabling
console: vcc5v0: disabling
console: usb1-vbus: disabling
console: usb2-vbus: disabling
console: ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
console: ata1.00: ATA-7: QEMU HARDDISK, 2.5+, max UDMA/100
console: ata1.00: 40960 sectors, multi 16: LBA48 NCQ (depth 32)
console: ata1.00: applying bridge limits
console: ata1.00: configured for UDMA/100
console: scsi 0:0:0:0: Direct-Access ATA QEMU HARDDISK 2.5+ PQ: 0
ANSI: 5
console: sd 0:0:0:0: Attached scsi generic sg0 type 0
console: sd 0:0:0:0: [sda] 40960 512-byte logical blocks: (21.0 MB/20.0 MiB)
console: sd 0:0:0:0: [sda] Write Protect is off
console: sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't
support DPO or FUA
console: sd 0:0:0:0: [sda] Attached SCSI disk
console: EXT4-fs (sda): mounting ext2 file system using the ext4 subsystem
console: EXT4-fs (sda): mounted filesystem without journal. Opts: (null)
console: VFS: Mounted root (ext2 filesystem) readonly on device 8:0.
[...]
console: cat /proc/partitions
console: / # cat /proc/partitions
console: major minor #blocks name
console: 1 0 4096 ram0
console: 1 1 4096 ram1
console: 1 2 4096 ram2
console: 1 3 4096 ram3
console: 8 0 20480 sda
console: reboot
console: / # reboot
[...]
console: sd 0:0:0:0: [sda] Synchronizing SCSI cache
console: reboot: Restarting system
PASS (48.39 s)
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7f0ec9893cc8c99e7ee928fdc66bb3046f3e4cd4
https://github.com/qemu/qemu/commit/7f0ec9893cc8c99e7ee928fdc66bb3046f3e4cd4
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M hw/arm/allwinner-a10.c
M include/hw/arm/allwinner-a10.h
Log Message:
-----------
hw/arm/allwinner-a10: Move SoC definitions out of header
These definitions are specific to the A10 SoC and don't need
to be exported to the different Allwinner peripherals.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Commit: f8a865d36dc1578eb8a4f7c896c4f46f4b82ca45
https://github.com/qemu/qemu/commit/f8a865d36dc1578eb8a4f7c896c4f46f4b82ca45
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M hw/arm/allwinner-a10.c
M include/hw/arm/allwinner-a10.h
Log Message:
-----------
hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios()
By calling qdev_pass_gpios() we don't need to hold a copy of the
IRQs from the INTC into the SoC state.
Instead of filling an array of qemu_irq and passing it around, we
can now directly call qdev_get_gpio_in() on the SoC.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Commit: af4ba4ed13b2bbfd2d33527741810a5905a11310
https://github.com/qemu/qemu/commit/af4ba4ed13b2bbfd2d33527741810a5905a11310
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M hw/arm/allwinner-a10.c
Log Message:
-----------
hw/arm/allwinner-a10: Remove local qemu_irq variables
We won't reuse the CPU IRQ/FIQ variables. Simplify by calling
qdev_get_gpio_in() in place.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Commit: 21bf9b06cb6d07c6cc437dfd47b47b28c2bb79db
https://github.com/qemu/qemu/commit/21bf9b06cb6d07c6cc437dfd47b47b28c2bb79db
Author: Masahiro Yamada <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
According to the specification "Semihosting for AArch32 and Aarch64",
the SYS_OPEN operation should return:
- A nonzero handle if the call is successful
- -1 if the call is not successful
So, it should never return 0.
Prior to commit 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting
code hand out its own file descriptors"), the guest fd matched to the
host fd. It returned a nonzero handle on success since the fd 0 is
already used for stdin.
Now that the guest fd is the index of guestfd_array, it starts from 0.
I noticed this issue particularly because Trusted Firmware-A built with
PLAT=qemu is no longer working. Its io_semihosting driver only handles
a positive return value as a valid filehandle.
Basically, there are two ways to fix this:
- Use (guestfd - 1) as the index of guestfs_arrary. We need to insert
increment/decrement to convert the guestfd and the array index back
and forth.
- Keep using guestfd as the index of guestfs_array. The first entry
of guestfs_array is left unused.
I thought the latter is simpler. We end up with wasting a small piece
of memory for the unused first entry of guestfd_array, but this is
probably not a big deal.
Fixes: 35e9a0a8ce4b ("target/arm/arm-semi: Make semihosting code hand out its
own file descriptors")
Cc: address@hidden
Signed-off-by: Masahiro Yamada <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f03965490e4e4223903e79a4ec97139ccdd48e1b
https://github.com/qemu/qemu/commit/f03965490e4e4223903e79a4ec97139ccdd48e1b
Author: Martin Kaiser <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M hw/arm/fsl-imx25.c
M hw/misc/Makefile.objs
A hw/misc/imx_rngc.c
M include/hw/arm/fsl-imx25.h
A include/hw/misc/imx_rngc.h
Log Message:
-----------
i.MX: add an emulation for RNGC
Add an emulation for the RNGC random number generator and the compatible
RNGB variant. These peripherals are included (at least) in imx25 and
imx35 chipsets.
The emulation supports the initial self test, reseeding the prng and
reading random numbers.
Signed-off-by: Martin Kaiser <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 855532912b0e1bf803ae393e5b0c7e80948cd6a4
https://github.com/qemu/qemu/commit/855532912b0e1bf803ae393e5b0c7e80948cd6a4
Author: Jeff Kubascik <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M target/arm/op_helper.c
Log Message:
-----------
target/arm: adjust program counter for wfi exception in AArch32
The wfi instruction can be configured to be trapped by a higher exception
level, such as the EL2 hypervisor. When the instruction is trapped, the
program counter should contain the address of the wfi instruction that
caused the exception. The program counter is adjusted for this in the wfi op
helper function.
However, this correction is done to env->pc, which only applies to AArch64
mode. For AArch32, the program counter is stored in env->regs[15]. This
adds an if-else statement to modify the correct program counter location
based on the the current CPU mode.
Signed-off-by: Jeff Kubascik <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: ef1255212a721e3ebc2be4bec9426bda9d2ee308
https://github.com/qemu/qemu/commit/ef1255212a721e3ebc2be4bec9426bda9d2ee308
Author: Jeff Kubascik <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
arm/gicv3: update virtual irq state after IAR register read
The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the
register activates the highest priority pending interrupt and provides its
interrupt ID. Activating an interrupt can change the CPU's virtual interrupt
state - this change makes sure the virtual irq state is updated.
Signed-off-by: Jeff Kubascik <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 30d544839e278dc76017b9a42990c41e84a34377
https://github.com/qemu/qemu/commit/30d544839e278dc76017b9a42990c41e84a34377
Author: Jeff Kubascik <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M target/arm/tlb_helper.c
Log Message:
-----------
target/arm: Return correct IL bit in merge_syn_data_abort
The IL bit is set for 32-bit instructions, thus passing false
with the is_16bit parameter to syn_data_abort_with_iss() makes
a syn mask that always has the IL bit set.
Pass is_16bit as true to make the initial syn mask have IL=0,
so that the final IL value comes from or'ing template_syn.
Cc: address@hidden
Fixes: aaa1f954d4ca ("target-arm: A64: Create Instruction Syndromes for Data
Aborts")
Signed-off-by: Jeff Kubascik <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[rth: Extracted this as a self-contained bug fix from a larger patch]
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 1a1fbc6cbb34c26d43d8360c66c1d21681af14a9
https://github.com/qemu/qemu/commit/1a1fbc6cbb34c26d43d8360c66c1d21681af14a9
Author: Richard Henderson <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Set ISSIs16Bit in make_issinfo
During the conversion to decodetree, the setting of
ISSIs16Bit got lost. This causes the guest os to
incorrectly adjust trapping memory operations.
Cc: address@hidden
Fixes: 46beb58efbb8a2a32 ("target/arm: Convert T16, load (literal)")
Reported-by: Jeff Kubascik <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7fb38daf256bd1bcbcb5ea556422283d0d55a1b1
https://github.com/qemu/qemu/commit/7fb38daf256bd1bcbcb5ea556422283d0d55a1b1
Author: Peter Maydell <address@hidden>
Date: 2020-01-17 (Fri, 17 Jan 2020)
Changed paths:
M MAINTAINERS
M default-configs/arm-softmmu.mak
M hw/arm/Kconfig
M hw/arm/Makefile.objs
M hw/arm/allwinner-a10.c
M hw/arm/fsl-imx25.c
A hw/arm/netduinoplus2.c
A hw/arm/stm32f405_soc.c
M hw/intc/arm_gicv3_cpuif.c
M hw/misc/Kconfig
M hw/misc/Makefile.objs
A hw/misc/imx_rngc.c
A hw/misc/stm32f4xx_exti.c
A hw/misc/stm32f4xx_syscfg.c
M hw/misc/trace-events
M include/hw/arm/allwinner-a10.h
M include/hw/arm/fsl-imx25.h
A include/hw/arm/stm32f405_soc.h
A include/hw/misc/imx_rngc.h
A include/hw/misc/stm32f4xx_exti.h
A include/hw/misc/stm32f4xx_syscfg.h
M target/arm/arm-semi.c
M target/arm/op_helper.c
M target/arm/tlb_helper.c
M target/arm/translate.c
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20200117-1' into staging
Add model of the Netduino Plus 2 board
Some allwinner-a10 code cleanup
New test cases for cubieboard
target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
i.MX: add an emulation for RNGC device
target/arm: adjust program counter for wfi exception in AArch32
arm/gicv3: update virtual irq state after IAR register read
Set IL bit correctly for syndrome information for data aborts
# gpg: Signature made Fri 17 Jan 2020 14:27:40 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20200117-1:
target/arm: Set ISSIs16Bit in make_issinfo
target/arm: Return correct IL bit in merge_syn_data_abort
arm/gicv3: update virtual irq state after IAR register read
target/arm: adjust program counter for wfi exception in AArch32
i.MX: add an emulation for RNGC
target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
hw/arm/allwinner-a10: Remove local qemu_irq variables
hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios()
hw/arm/allwinner-a10: Move SoC definitions out of header
tests/boot_linux_console: Add a SD card test for the CubieBoard
tests/boot_linux_console: Add initrd test for the CubieBoard
hw/arm: Add the Netduino Plus 2
hw/arm: Add the STM32F4xx SoC
hw/misc: Add the STM32F4xx EXTI device
hw/misc: Add the STM32F4xx Sysconfig device
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/bc65450ebb9b...7fb38daf256b
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