[Qemu-commits] [qemu/qemu] 97a254: target/openrisc: Fix FPCSR mask to allow setting DZF

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 97a254b3f03a184136e381c6d9fd80475e1795ac
      
https://github.com/qemu/qemu/commit/97a254b3f03a184136e381c6d9fd80475e1795ac
  Author: Stafford Horne <address@hidden>
  Date:   2020-01-16 (Thu, 16 Jan 2020)

  Changed paths:
    M target/openrisc/fpu_helper.c

  Log Message:
  -----------
  target/openrisc: Fix FPCSR mask to allow setting DZF

The mask used when setting FPCSR allows setting bits 10 to 1.  However,
OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
Flag (DZF).  This seems like an off-by-one bug.

This was found when testing the GLIBC test suite which has test cases to
set and clear all bits.

Signed-off-by: Stafford Horne <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 43ed232fbf65fc594e496b944129a480b2f75b5e
      
https://github.com/qemu/qemu/commit/43ed232fbf65fc594e496b944129a480b2f75b5e
  Author: Peter Maydell <address@hidden>
  Date:   2020-01-17 (Fri, 17 Jan 2020)

  Changed paths:
    M target/openrisc/fpu_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20200116' into 
staging

Fix FPSCR masking

# gpg: Signature made Fri 17 Jan 2020 00:51:41 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Richard Henderson <address@hidden>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-or1k-20200116:
  target/openrisc: Fix FPCSR mask to allow setting DZF

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/cbf01142b2ae...43ed232fbf65