[Qemu-commits] [qemu/qemu] cf7bed: target/arm: Add support for cortex-m7 CPU

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: cf7beda5072e106ddce875c1996446540c5fe239
      
https://github.com/qemu/qemu/commit/cf7beda5072e106ddce875c1996446540c5fe239
  Author: Christophe Lyon <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Add support for cortex-m7 CPU

This is derived from cortex-m4 description, adding DP support and FPv5
instructions with the corresponding flags in isar and mvfr2.

Checked that it could successfully execute
vrinta.f32 s15, s15
while cortex-m4 emulation rejects it with "illegal instruction".

Signed-off-by: Christophe Lyon <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1625073289b7940477031d3e98ea8c829a699df5
      
https://github.com/qemu/qemu/commit/1625073289b7940477031d3e98ea8c829a699df5
  Author: David Gibson <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/intc/exynos4210_gic.c

  Log Message:
  -----------
  exynos4210_gic: Suppress gcc9 format-truncation warnings

exynos4210_gic_realize() prints the number of cpus into some temporary
buffers, but it only allows 3 bytes space for it.  That's plenty:
existing machines will only ever set this value to EXYNOS4210_NCPUS
(2).  But the compiler can't always figure that out, so some[*] gcc9
versions emit -Wformat-truncation warnings.

We can fix that by hinting the constraint to the compiler with a
suitably placed assert().

[*] The bizarre thing here, is that I've long gotten these warnings
    compiling in a 32-bit x86 container as host - Fedora 30 with
    gcc-9.2.1-1.fc30.i686 - but it compiles just fine on my normal
    x86_64 host - Fedora 30 with and gcc-9.2.1-1.fc30.x86_64.

Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
[PMM: deleted stray blank line]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6054fc73e8f4acaafa63b4616e39414e53bce9a9
      
https://github.com/qemu/qemu/commit/6054fc73e8f4acaafa63b4616e39414e53bce9a9
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/i2c/aspeed_i2c.c
    M include/hw/i2c/aspeed_i2c.h

  Log Message:
  -----------
  aspeed/i2c: Add support for pool buffer transfers

The Aspeed I2C controller can operate in different transfer modes :

  - Byte Buffer mode, using a dedicated register to transfer a
    byte. This is what the model supports today.

  - Pool Buffer mode, using an internal SRAM to transfer multiple
    bytes in the same command sequence.

Each SoC has different SRAM characteristics. On the AST2400, 2048
bytes of SRAM are available at offset 0x800 of the controller AHB
window. The pool buffer can be configured from 1 to 256 bytes per bus.

On the AST2500, the SRAM is at offset 0x200 and the pool buffer is of
16 bytes per bus.

On the AST2600, the SRAM is at offset 0xC00 and the pool buffer is of
32 bytes per bus. It can be splitted in two for TX and RX but the
current model does not add support for it as it it unused by known
drivers.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Tested-by: Jae Hyun Yoo <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: aab90b1cacb8b808d4f00c9709595c50b9d1f7a2
      
https://github.com/qemu/qemu/commit/aab90b1cacb8b808d4f00c9709595c50b9d1f7a2
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/i2c/aspeed_i2c.c
    M include/hw/i2c/aspeed_i2c.h

  Log Message:
  -----------
  aspeed/i2c: Check SRAM enablement on AST2500

The SRAM must be enabled before using the Buffer Pool mode or the DMA
mode. This is not required on other SoCs.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Tested-by: Jae Hyun Yoo <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 95b56e173e20267778965a2bfd1afd517f7342c4
      
https://github.com/qemu/qemu/commit/95b56e173e20267778965a2bfd1afd517f7342c4
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: Add a DRAM memory region at the SoC level

Currently, we link the DRAM memory region to the FMC model (for DMAs)
through a property alias at the SoC level. The I2C model will need a
similar region for DMA support, add a DRAM region property at the SoC
level for both model to use.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Tested-by: Jae Hyun Yoo <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 545d6bef7097129040bddc86fe09326ee0a14aae
      
https://github.com/qemu/qemu/commit/545d6bef7097129040bddc86fe09326ee0a14aae
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    M hw/i2c/aspeed_i2c.c
    M include/hw/i2c/aspeed_i2c.h

  Log Message:
  -----------
  aspeed/i2c: Add support for DMA transfers

The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
transfers to and from DRAM.

A pair of registers defines the buffer address and the length of the
DMA transfer. The address should be aligned on 4 bytes and the maximum
length should not exceed 4K. The receive or transmit DMA transfer can
then be initiated with specific bits in the Command/Status register of
the controller.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Tested-by: Jae Hyun Yoo <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 66cc84a1a3f9a15e0d89ec332d74e3f8012f989a
      
https://github.com/qemu/qemu/commit/66cc84a1a3f9a15e0d89ec332d74e3f8012f989a
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/i2c/aspeed_i2c.c
    M hw/i2c/trace-events

  Log Message:
  -----------
  aspeed/i2c: Add trace events

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Tested-by: Jae Hyun Yoo <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d3ff9e69b70da720dd701b7badb0bd285ce8b34b
      
https://github.com/qemu/qemu/commit/d3ff9e69b70da720dd701b7badb0bd285ce8b34b
  Author: Joel Stanley <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/misc/aspeed_sdmc.c

  Log Message:
  -----------
  aspeed/sdmc: Make ast2600 default 1G

Most boards have this much.

Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 310b5bc69213684b5c2429494c04b3300d9a3150
      
https://github.com/qemu/qemu/commit/310b5bc69213684b5c2429494c04b3300d9a3150
  Author: Joel Stanley <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/misc/aspeed_scu.c

  Log Message:
  -----------
  aspeed/scu: Fix W1C behavior

This models the clock write one to clear registers, and fixes up some
incorrect behavior in all of the write to clear registers.

There was also a typo in one of the register definitions.

Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: checkpatch.pl fixes ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: aabf1de4b7a2fb14797946f8eb970d391cecf0d8
      
https://github.com/qemu/qemu/commit/aabf1de4b7a2fb14797946f8eb970d391cecf0d8
  Author: Joel Stanley <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/watchdog/wdt_aspeed.c

  Log Message:
  -----------
  watchdog/aspeed: Improve watchdog timeout message

Users benefit from knowing which watchdog timer has expired. The address
of the watchdog's registers unambiguously indicates which has expired,
so log that.

Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 28c80f15fc9c4c1ee980e87e693374f196aa20fe
      
https://github.com/qemu/qemu/commit/28c80f15fc9c4c1ee980e87e693374f196aa20fe
  Author: Joel Stanley <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/watchdog/wdt_aspeed.c
    M include/hw/watchdog/wdt_aspeed.h

  Log Message:
  -----------
  watchdog/aspeed: Fix AST2600 frequency behaviour

The AST2600 control register sneakily changed the meaning of bit 4
without anyone noticing. It no longer controls the 1MHz vs APB clock
select, and instead always runs at 1MHz.

The AST2500 was always 1MHz too, but it retained bit 4, making it read
only. We can model both using the same fixed 1MHz calculation.

Fixes: 6b2b2a703cad ("hw: wdt_aspeed: Add AST2600 support")
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 673b1f86504bb3df0417d013f97a0832490facef
      
https://github.com/qemu/qemu/commit/673b1f86504bb3df0417d013f97a0832490facef
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: Restore default AHB window mapping at reset

The current model only restores the Segment Register values but leaves
the previous CS mapping behind. Introduce a helper setting the
register value and mapping the region at the requested address. Use
this helper when a Segment register is set and at reset.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2175eacfcd0806f502a12457c1d49ed01b75b797
      
https://github.com/qemu/qemu/commit/2175eacfcd0806f502a12457c1d49ed01b75b797
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: Do not map disabled segment on the AST2600

The segments can be disabled on the AST2600 (zero register value).
CS0 is open by default but not the other CS. This is closing the
access to the flash device in user mode and forbids scanning.

In the model, check the segment size and disable the associated region
when the value is zero.

Fixes: bcaa8ddd081c ("aspeed/smc: Add AST2600 support")
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f286f04c21aba0f751ede4f5c99228a09e40c90b
      
https://github.com/qemu/qemu/commit/f286f04c21aba0f751ede4f5c99228a09e40c90b
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/ssi/aspeed_smc.c
    M include/hw/ssi/aspeed_smc.h

  Log Message:
  -----------
  aspeed/smc: Add AST2600 timings registers

Each CS has its own Read Timing Compensation Register on newer SoCs.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: baa4732bc10b3fd7c304ec7087e87b721ad891cf
      
https://github.com/qemu/qemu/commit/baa4732bc10b3fd7c304ec7087e87b721ad891cf
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/arm/aspeed.c
    M include/hw/arm/aspeed.h

  Log Message:
  -----------
  aspeed: Remove AspeedBoardConfig array and use AspeedMachineClass

AspeedBoardConfig is a redundant way to define class attributes and it
complexifies the machine definition and initialization.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 63ceb818a43391f6631efeb51fe6e0029c582497
      
https://github.com/qemu/qemu/commit/63ceb818a43391f6631efeb51fe6e0029c582497
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Add support for the tacoma-bmc board

The Tacoma BMC board is replacement board for the BMC of the OpenPOWER
Witherspoon system. It uses a AST2600 SoC instead of a AST2500 and the
I2C layout is the same as it controls the same main board. Used for HW
bringup.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 15cea92d9e8afd4472147e54efe2eef0b7754dcd
      
https://github.com/qemu/qemu/commit/15cea92d9e8afd4472147e54efe2eef0b7754dcd
  Author: PanNengyuan <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/gpio/aspeed_gpio.c

  Log Message:
  -----------
  gpio: fix memory leak in aspeed_gpio_init()

Address Sanitizer shows memory leak in hw/gpio/aspeed_gpio.c:875

Reported-by: Euler Robot <address@hidden>
Signed-off-by: PanNengyuan <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2ec11f2320f6146321574c73b9cd6196f861eb10
      
https://github.com/qemu/qemu/commit/2ec11f2320f6146321574c73b9cd6196f861eb10
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    M hw/timer/aspeed_timer.c
    M hw/watchdog/wdt_aspeed.c

  Log Message:
  -----------
  aspeed: Change the "scu" property definition

The Aspeed Watchdog and Timer models have a link pointing to the SCU
controller model of the machine.

Change the "scu" property definition so that it explicitly sets the
pointer. The property isn't optional : not being able to set the link
is a bug and QEMU should rather abort than exit in this case.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ccb88bf220b041f04e946d3a2b619dd2bc30951b
      
https://github.com/qemu/qemu/commit/ccb88bf220b041f04e946d3a2b619dd2bc30951b
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/arm/aspeed_ast2600.c
    M hw/net/ftgmac100.c

  Log Message:
  -----------
  aspeed: Change the "nic" property definition

The Aspeed MII model has a link pointing to its associated FTGMAC100
NIC in the machine.

Change the "nic" property definition so that it explicitly sets the
pointer. The property isn't optional : not being able to set the link
is a bug and QEMU should rather abort than exit in this case.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 630fcd4d2ba37050329e0adafdc552d656ebe2f3
      
https://github.com/qemu/qemu/commit/630fcd4d2ba37050329e0adafdc552d656ebe2f3
  Author: Marc Zyngier <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Honor HCR_EL2.TID2 trapping requirements

HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1,
CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU
completely ignores it, making it impossible for hypervisors to
virtualize the cache hierarchy.

Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set.

Signed-off-by: Marc Zyngier <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 93fbc983b29a2eb84e2f6065929caf14f99c3681
      
https://github.com/qemu/qemu/commit/93fbc983b29a2eb84e2f6065929caf14f99c3681
  Author: Marc Zyngier <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Honor HCR_EL2.TID1 trapping requirements

HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1
(and their 32bit equivalents) as well as TCMTR, TLBTR are trapped
to EL2. QEMU ignores it, making it harder for a hypervisor to
virtualize the HW (though to be fair, no known hypervisor actually
cares).

Do the right thing by trapping to EL2 if HCR_EL2.TID1 is set.

Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Marc Zyngier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9ca1d776cb49c09b09579d9edd0447542970c834
      
https://github.com/qemu/qemu/commit/9ca1d776cb49c09b09579d9edd0447542970c834
  Author: Marc Zyngier <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-vfp.inc.c
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Handle trapping to EL2 of AArch32 VMRS instructions

HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, introduce a new TCG helper function that
checks for these control bits before executing the VMRC instruction.

Tested with a hacked-up version of KVM/arm64 that sets the control
bits for 32bit guests.

Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Marc Zyngier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: move helper declaration to helper.h; make it
 TCG_CALL_NO_WG]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5bb0a20b74ad17dee5dae38e3b8b70b383ee7c2d
      
https://github.com/qemu/qemu/commit/5bb0a20b74ad17dee5dae38e3b8b70b383ee7c2d
  Author: Marc Zyngier <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/op_helper.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Handle AArch32 CP15 trapping via HSTR_EL2

HSTR_EL2 offers a way to trap ranges of CP15 system register
accesses to EL2, and it looks like this register is completely
ignored by QEMU.

To avoid adding extra .accessfn filters all over the place (which
would have a direct performance impact), let's add a new TB flag
that gets set whenever HSTR_EL2 is non-zero and that QEMU translates
a context where this trap has a chance to apply, and only generate
the extra access check if the hypervisor is actively using this feature.

Tested with a hand-crafted KVM guest accessing CBAR.

Signed-off-by: Marc Zyngier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: use is_a64(); fix comment syntax]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f96f3d5f09973ef40f164cf2d5fd98ce5498b82a
      
https://github.com/qemu/qemu/commit/f96f3d5f09973ef40f164cf2d5fd98ce5498b82a
  Author: Marc Zyngier <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add support for missing Jazelle system registers

QEMU lacks the minimum Jazelle implementation that is required
by the architecture (everything is RAZ or RAZ/WI). Add it
together with the HCR_EL2.TID0 trapping that goes with it.

Signed-off-by: Marc Zyngier <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: moved ARMCPRegInfo array to file scope, marked it
 'static global', moved new condition down in
 register_cp_regs_for_features() to go with other feature
 things rather than up with the v6/v7/v8 stuff]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c7f8c43daf6556078e51de98aa13f069e505985
      
https://github.com/qemu/qemu/commit/0c7f8c43daf6556078e51de98aa13f069e505985
  Author: Niek Linnenbank <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M target/arm/arm-powerctl.c

  Log Message:
  -----------
  arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on()

This change ensures that the FPU can be accessed in Non-Secure mode
when the CPU core is reset using the arm_set_cpu_on() function call.
The NSACR.{CP11,CP10} bits define the exception level required to
access the FPU in Non-Secure mode. Without these bits set, the CPU
will give an undefined exception trap on the first FPU access for the
secondary cores under Linux.

This is necessary because in this power-control codepath QEMU
is effectively emulating a bit of EL3 firmware, and has to set
the CPU up as the EL3 firmware would.

Fixes: fc1120a7f5
Cc: address@hidden
Signed-off-by: Niek Linnenbank <address@hidden>
[PMM: added clarifying para to commit message]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9e70492b4389d4355ae9c9ee2ba6286cfdadc257
      
https://github.com/qemu/qemu/commit/9e70492b4389d4355ae9c9ee2ba6286cfdadc257
  Author: Beata Michalska <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M include/exec/exec-all.h

  Log Message:
  -----------
  tcg: cputlb: Add probe_read

Add probe_read alongside the write probing equivalent.

Signed-off-by: Beata Michalska <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 61c490e25e081af39ff40556f6c1229b8b011585
      
https://github.com/qemu/qemu/commit/61c490e25e081af39ff40556f6c1229b8b011585
  Author: Beata Michalska <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M exec.c
    M include/exec/memory.h
    M include/exec/ram_addr.h
    M include/qemu/cutils.h
    M memory.c
    M util/cutils.c

  Log Message:
  -----------
  Memory: Enable writeback for given memory region

Add an option to trigger memory writeback to sync given memory region
with the corresponding backing store, case one is available.
This extends the support for persistent memory, allowing syncing on-demand.

Signed-off-by: Beata Michalska <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bd108a44bc29cb648dd930564996b0128e66ac01
      
https://github.com/qemu/qemu/commit/bd108a44bc29cb648dd930564996b0128e66ac01
  Author: Beata Michalska <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M migration/ram.c

  Log Message:
  -----------
  migration: ram: Switch to ram block writeback

Switch to ram block writeback for pmem migration.

Signed-off-by: Beata Michalska <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Acked-by: Dr. David Alan Gilbert <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0d57b49992200a926c4436eead97ecfc8cc710be
      
https://github.com/qemu/qemu/commit/0d57b49992200a926c4436eead97ecfc8cc710be
  Author: Beata Michalska <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M linux-user/elfload.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add support for DC CVAP & DC CVADP ins

ARMv8.2 introduced support for Data Cache Clean instructions
to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence)
- DV CVADP. Both specify conceptual points in a memory system where all writes
that are to reach them are considered persistent.
The support provided considers both to be actually the same so there is no
distinction between the two. If none is available (there is no backing store
for given memory) both will result in Data Cache Clean up to the point of
coherency. Otherwise sync for the specified range shall be performed.

Signed-off-by: Beata Michalska <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 48ba18e6d3f3908600ed4393a5eaf15bf31404fd
      
https://github.com/qemu/qemu/commit/48ba18e6d3f3908600ed4393a5eaf15bf31404fd
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  hw/arm/sbsa-ref: Simplify by moving the gic in the machine state

Make the gic a field in the machine state, and instead of filling
an array of qemu_irq and passing it around, directly call
qdev_get_gpio_in() on the gic field.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f3635813977cfde33f0bb76bb1a169410e6cdbac
      
https://github.com/qemu/qemu/commit/f3635813977cfde33f0bb76bb1a169410e6cdbac
  Author: Heyi Guo <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    M tests/data/acpi/virt/DSDT
    M tests/data/acpi/virt/DSDT.memhp
    M tests/data/acpi/virt/DSDT.numamem

  Log Message:
  -----------
  hw/arm/acpi: simplify AML bit and/or statement

The last argument of AML bit and/or statement is the target variable,
so we don't need to use a NULL target and then an additional store
operation; using just aml_and() or aml_or() statement is enough.

Also update tests/data/acpi/virt/DSDT* to pass "make check".

Cc: Shannon Zhao <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Igor Mammedov <address@hidden>
Suggested-by: Igor Mammedov <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Signed-off-by: Heyi Guo <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e04c13cdcf5befd9d08df38d4d34494a802cdf63
      
https://github.com/qemu/qemu/commit/e04c13cdcf5befd9d08df38d4d34494a802cdf63
  Author: Heyi Guo <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    M tests/data/acpi/virt/DSDT
    M tests/data/acpi/virt/DSDT.memhp
    M tests/data/acpi/virt/DSDT.numamem

  Log Message:
  -----------
  hw/arm/acpi: enable SHPC native hot plug

After the introduction of generic PCIe root port and PCIe-PCI bridge,
we will also have SHPC controller on ARM, so just enable SHPC native
hot plug.

Also update tests/data/acpi/virt/DSDT* to pass "make check".

Cc: Shannon Zhao <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Igor Mammedov <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Signed-off-by: Heyi Guo <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b8b69f4c45894ea05a9c334e76178679ec084565
      
https://github.com/qemu/qemu/commit/b8b69f4c45894ea05a9c334e76178679ec084565
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M hw/arm/virt.c
    M include/hw/arm/virt.h

  Log Message:
  -----------
  hw/arm/virt: Simplify by moving the gic in the machine state

Make the gic a field in the machine state, and instead of filling
an array of qemu_irq and passing it around, directly call
qdev_get_gpio_in() on the gic field.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f80741d107673f162e3b097fc76a1590036cc9d1
      
https://github.com/qemu/qemu/commit/f80741d107673f162e3b097fc76a1590036cc9d1
  Author: Alex Bennée <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: ensure we use current exception state after SCR update

A write to the SCR can change the effective EL by droppping the system
from secure to non-secure mode. However if we use a cached current_el
from before the change we'll rebuild the flags incorrectly. To fix
this we introduce the ARM_CP_NEWEL CP flag to indicate the new EL
should be used when recomputing the flags.

Signed-off-by: Alex Bennée <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Cc: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 856ffa6465ad38a31603223eb057a253114ceaea
      
https://github.com/qemu/qemu/commit/856ffa6465ad38a31603223eb057a253114ceaea
  Author: Peter Maydell <address@hidden>
  Date:   2019-12-16 (Mon, 16 Dec 2019)

  Changed paths:
    M exec.c
    M hw/arm/aspeed.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    M hw/arm/sbsa-ref.c
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/gpio/aspeed_gpio.c
    M hw/i2c/aspeed_i2c.c
    M hw/i2c/trace-events
    M hw/intc/exynos4210_gic.c
    M hw/misc/aspeed_scu.c
    M hw/misc/aspeed_sdmc.c
    M hw/net/ftgmac100.c
    M hw/ssi/aspeed_smc.c
    M hw/timer/aspeed_timer.c
    M hw/watchdog/wdt_aspeed.c
    M include/exec/exec-all.h
    M include/exec/memory.h
    M include/exec/ram_addr.h
    M include/hw/arm/aspeed.h
    M include/hw/arm/aspeed_soc.h
    M include/hw/arm/virt.h
    M include/hw/i2c/aspeed_i2c.h
    M include/hw/ssi/aspeed_smc.h
    M include/hw/watchdog/wdt_aspeed.h
    M include/qemu/cutils.h
    M linux-user/elfload.c
    M memory.c
    M migration/ram.c
    M target/arm/arm-powerctl.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/op_helper.c
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vfp_helper.c
    M tests/data/acpi/virt/DSDT
    M tests/data/acpi/virt/DSDT.memhp
    M tests/data/acpi/virt/DSDT.numamem
    M util/cutils.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20191216-1' into staging

target-arm queue:
 * Add support for Cortex-M7 CPU
 * exynos4210_gic: Suppress gcc9 format-truncation warnings
 * aspeed: Various minor bug fixes and improvements
 * aspeed: Add support for the tacoma-bmc board
 * Honour HCR_EL32.TID1 and .TID2 trapping requirements
 * Handle trapping to EL2 of AArch32 VMRS instructions
 * Handle AArch32 CP15 trapping via HSTR_EL2
 * Add support for missing Jazelle system registers
 * arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on
 * Add support for DC CVAP & DC CVADP instructions
 * Fix assertion when SCR.NS is changed in Secure-SVC &c
 * enable SHPC native hot plug in arm ACPI

# gpg: Signature made Mon 16 Dec 2019 11:08:07 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20191216-1: (34 commits)
  target/arm: ensure we use current exception state after SCR update
  hw/arm/virt: Simplify by moving the gic in the machine state
  hw/arm/acpi: enable SHPC native hot plug
  hw/arm/acpi: simplify AML bit and/or statement
  hw/arm/sbsa-ref: Simplify by moving the gic in the machine state
  target/arm: Add support for DC CVAP & DC CVADP ins
  migration: ram: Switch to ram block writeback
  Memory: Enable writeback for given memory region
  tcg: cputlb: Add probe_read
  arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on()
  target/arm: Add support for missing Jazelle system registers
  target/arm: Handle AArch32 CP15 trapping via HSTR_EL2
  target/arm: Handle trapping to EL2 of AArch32 VMRS instructions
  target/arm: Honor HCR_EL2.TID1 trapping requirements
  target/arm: Honor HCR_EL2.TID2 trapping requirements
  aspeed: Change the "nic" property definition
  aspeed: Change the "scu" property definition
  gpio: fix memory leak in aspeed_gpio_init()
  aspeed: Add support for the tacoma-bmc board
  aspeed: Remove AspeedBoardConfig array and use AspeedMachineClass
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/7697ac55fcc6...856ffa6465ad