[Qemu-commits] [qemu/qemu] 9c0fb2: RISC-V: virt: This is a "sifive, test1" test finisher

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9c0fb20c4bd50a99c3c6f6d515e05eaf8dd87fa4
      
https://github.com/qemu/qemu/commit/9c0fb20c4bd50a99c3c6f6d515e05eaf8dd87fa4
  Author: Palmer Dabbelt <address@hidden>
  Date:   2019-11-25 (Mon, 25 Nov 2019)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  RISC-V: virt: This is a "sifive,test1" test finisher

The test finisher implements the reset command, which means it's a
"sifive,test1" device.  This is a backwards compatible change, so it's
also a "sifive,test0" device.  I copied the odd idiom for adding a
two-string compatible field from the ARM virt board.

Fixes: 9a2551ed6f ("riscv: sifive_test: Add reset functionality")
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 6478dd745dca49d63250500cd1aeca1c41cd6f89
      
https://github.com/qemu/qemu/commit/6478dd745dca49d63250500cd1aeca1c41cd6f89
  Author: Zhuang, Siwei (Data61, Kensington NSW) <address@hidden>
  Date:   2019-11-25 (Mon, 25 Nov 2019)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()

This patch adds an optional function pointer, "sym_cb", to
riscv_load_kernel() which provides the possibility to access the symbol
table during kernel loading.

The pointer is ignored, if supplied with Image or uImage file.

The Spike board requires the access to locate the HTIF symbols.

Fixes: 0ac24d56c5e7 ("hw/riscv: Split out the boot functions")
Buglink: https://bugs.launchpad.net/qemu/+bug/1835827
Signed-off-by: Siwei Zhuang <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 4ecc984210ca1bf508a96a550ec8a93a5f833f6c
      
https://github.com/qemu/qemu/commit/4ecc984210ca1bf508a96a550ec8a93a5f833f6c
  Author: Peter Maydell <address@hidden>
  Date:   2019-11-26 (Tue, 26 Nov 2019)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' 
into staging

RISC-V Patches for 4.2-rc3

This tag contains two patches that I'd like to target for 4.2-rc3:

* A fix to the DT entry for the SiFive test finisher.
* A fix to the spike board's HTIF interface.

This passes "make check" and boots OE for me.

# gpg: Signature made Mon 25 Nov 2019 20:51:13 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.2-rc3:
  hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()
  RISC-V: virt: This is a "sifive,test1" test finisher

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/a5f80c16f204...4ecc984210ca