[Qemu-commits] [qemu/qemu] 83ad95: pl031: Expose RTCICR as proper WC register

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 83ad95957c7e66f2685fb38c9675949d3bf478eb
      
https://github.com/qemu/qemu/commit/83ad95957c7e66f2685fb38c9675949d3bf478eb
  Author: Alexander Graf <address@hidden>
  Date:   2019-11-19 (Tue, 19 Nov 2019)

  Changed paths:
    M hw/rtc/pl031.c

  Log Message:
  -----------
  pl031: Expose RTCICR as proper WC register

The current PL031 RTCICR register implementation always clears the
IRQ pending status on a register write, regardless of the value the
guest writes.

To justify that behavior, it references the ARM926EJ-S Development
Chip Reference Manual (DDI0287B) and indicates that said document
states that any write clears the internal IRQ state.  It is indeed
true that in section 11.1 this document says:

  "The interrupt is cleared by writing any data value to the
   interrupt clear register RTCICR".

However, later in section 11.2.2 it contradicts itself by saying:

  "Writing 1 to bit 0 of RTCICR clears the RTCINTR flag."

The latter statement matches the PL031 TRM (DDI0224C), which says:

  "Writing 1 to bit position 0 clears the corresponding interrupt.
   Writing 0 has no effect."

Let's assume that the self-contradictory DDI0287B is in error, and
follow the reference manual for the device itself, by making the
register write-one-to-clear.

Reported-by: Hendrik Borghorst <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Message-id: address@hidden
[PMM: updated commit message to note that DDI0287B says two
 conflicting things]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6e553f2a1b8450c9e9721fb60e3ef134492a4a39
      
https://github.com/qemu/qemu/commit/6e553f2a1b8450c9e9721fb60e3ef134492a4a39
  Author: Richard Henderson <address@hidden>
  Date:   2019-11-19 (Tue, 19 Nov 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller

Coverity reports, in sve_zcr_get_valid_len,

"Subtract operation overflows on operands
arm_cpu_vq_map_next_smaller(cpu, start_vq + 1U) and 1U"

First, the aarch32 stub version of arm_cpu_vq_map_next_smaller,
returning 0, does exactly what Coverity reports.  Remove it.

Second, the aarch64 version of arm_cpu_vq_map_next_smaller has
a set of asserts, but they don't cover the case in question.
Further, there is a fair amount of extra arithmetic needed to
convert from the 0-based zcr register, to the 1-base vq form,
to the 0-based bitmap, and back again.  This can be simplified
by leaving the value in the 0-based form.

Finally, use test_bit to simplify the common case, where the
length in the zcr registers is in fact a supported length.

Reported-by: Coverity (CID 1407217)
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3a6606c7aa1e6e687e435c1eae929a396bd866e3
      
https://github.com/qemu/qemu/commit/3a6606c7aa1e6e687e435c1eae929a396bd866e3
  Author: Sai Pavan Boddu <address@hidden>
  Date:   2019-11-19 (Tue, 19 Nov 2019)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  ssi: xilinx_spips: Skip spi bus update for a few register writes

A few configuration register writes need not update the spi bus state, so just
return after the register write.

Signed-off-by: Sai Pavan Boddu <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Tested-by: Francisco Iglesias <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6623d214451ec4f784d1c82c51c655a01fed1b06
      
https://github.com/qemu/qemu/commit/6623d214451ec4f784d1c82c51c655a01fed1b06
  Author: Linus Ziegert <address@hidden>
  Date:   2019-11-19 (Tue, 19 Nov 2019)

  Changed paths:
    M hw/net/cadence_gem.c

  Log Message:
  -----------
  net/cadence_gem: Set PHY autonegotiation restart status

The Linux kernel PHY driver sets AN_RESTART in the BMCR of the
PHY when autonegotiation is started.
Recently the kernel started to read back the PHY's AN_RESTART
bit and now checks whether the autonegotiation is complete and
the bit was cleared [1]. Otherwise the link status is down.

The emulated PHY needs to clear AN_RESTART immediately to inform
the kernel driver about the completion of autonegotiation phase.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c36757eb9dee

Signed-off-by: Linus Ziegert <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 655b02646dc175dc10666459b0a1e4346fc8d46a
      
https://github.com/qemu/qemu/commit/655b02646dc175dc10666459b0a1e4346fc8d46a
  Author: Richard Henderson <address@hidden>
  Date:   2019-11-19 (Tue, 19 Nov 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Do not reject rt == rt2 for strexd

There was too much cut and paste between ldrexd and strexd,
as ldrexd does prohibit two output registers the same.

Fixes: af288228995
Reported-by: Michael Goffioul <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Robert Foley <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d46ad79efac7aaf9f0eb9f5a96a576e9f39200e0
      
https://github.com/qemu/qemu/commit/d46ad79efac7aaf9f0eb9f5a96a576e9f39200e0
  Author: Richard Henderson <address@hidden>
  Date:   2019-11-19 (Tue, 19 Nov 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Relax r13 restriction for ldrex/strex for v8.0

Armv8-A removes UNPREDICTABLE for R13 for these cases.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: changed ENABLE_ARCH_8 checks to check a new bool 'v8a',
 since these cases are still UNPREDICTABLE for v8M]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 04c9c81b8fa2ee33f59a26265700fae6fc646062
      
https://github.com/qemu/qemu/commit/04c9c81b8fa2ee33f59a26265700fae6fc646062
  Author: Richard Henderson <address@hidden>
  Date:   2019-11-19 (Tue, 19 Nov 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY

Simply moving the non-stub helper_v7m_mrs/msr outside of
!CONFIG_USER_ONLY is not an option, because of all of the
other system-mode helpers that are called.

But we can split out a few subroutines to handle the few
EL0 accessible registers without duplicating code.

Reported-by: Christophe Lyon <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: deleted now-redundant comment; added a default case
 to switch in v7m_msr helper]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9263dec8ef9a5723d87724c5d1de86a2d5f8ba29
      
https://github.com/qemu/qemu/commit/9263dec8ef9a5723d87724c5d1de86a2d5f8ba29
  Author: Peter Maydell <address@hidden>
  Date:   2019-11-19 (Tue, 19 Nov 2019)

  Changed paths:
    M hw/net/cadence_gem.c
    M hw/rtc/pl031.c
    M hw/ssi/xilinx_spips.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/m_helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191119' 
into staging

target-arm queue:
 * Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
 * Relax r13 restriction for ldrex/strex for v8.0
 * Do not reject rt == rt2 for strexd
 * net/cadence_gem: Set PHY autonegotiation restart status
 * ssi: xilinx_spips: Skip spi bus update for a few register writes
 * pl031: Expose RTCICR as proper WC register

# gpg: Signature made Tue 19 Nov 2019 13:30:35 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20191119:
  target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
  target/arm: Relax r13 restriction for ldrex/strex for v8.0
  target/arm: Do not reject rt == rt2 for strexd
  net/cadence_gem: Set PHY autonegotiation restart status
  ssi: xilinx_spips: Skip spi bus update for a few register writes
  target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller
  pl031: Expose RTCICR as proper WC register

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/6e5d4999c761...9263dec8ef9a