[Qemu-commits] [qemu/qemu] f480f6: remove unnecessary ifdef TARGET_RISCV64

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: f480f6e8c5ca9a27c046e3a273a4693d2475bdc2
      
https://github.com/qemu/qemu/commit/f480f6e8c5ca9a27c046e3a273a4693d2475bdc2
  Author: hiroyuki.obinata <address@hidden>
  Date:   2019-11-14 (Thu, 14 Nov 2019)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  remove unnecessary ifdef TARGET_RISCV64

Signed-off-by: Hiroyuki Obinata <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 7ec5d3030b9293ab631dd653f64bc933b6c82e65
      
https://github.com/qemu/qemu/commit/7ec5d3030b9293ab631dd653f64bc933b6c82e65
  Author: Alistair Francis <address@hidden>
  Date:   2019-11-14 (Thu, 14 Nov 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Remove atomic accesses to MIP CSR

Instead of relying on atomics to access the MIP register let's update
our helper function to instead just lock the IO mutex thread before
writing. This follows the same concept as used in PPC for handling
interrupts

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 3158add2bd12b5db812b8362bebbaba1e9d4d265
      
https://github.com/qemu/qemu/commit/3158add2bd12b5db812b8362bebbaba1e9d4d265
  Author: Alistair Francis <address@hidden>
  Date:   2019-11-14 (Thu, 14 Nov 2019)

  Changed paths:
    M pc-bios/opensbi-riscv32-virt-fw_jump.bin
    M pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
    M pc-bios/opensbi-riscv64-virt-fw_jump.bin
    M roms/opensbi

  Log Message:
  -----------
  opensbi: Upgrade from v0.4 to v0.5

This release has:
    Lot of critical fixes
    Hypervisor extension support
    SBI v0.2 base extension support
    Debug prints support
    Handle traps when doing unpriv load/store
    Allow compiling without FP support
    Use git describe to generate boot-time banner
    Andes AE350 platform support

ShortLog:

Anup Patel (14):
      platform: sifive/fu540: Move FDT further up
      lib: Allow compiling without FP support
      lib: Introduce sbi_dprintf() API
      lib: Use sbi_dprintf() for invalid CSRs
      lib: Handle traps when doing unpriv load/store in get_insn()
      lib: Delegate supervisor ecall to HS-mode when H extension available
      lib: Extend sbi_hart_switch_mode() to support hypervisor extension
      lib: Extend sbi_trap_redirect() for hypervisor extension
      lib: Redirect WFI trapped from VS/VU mode to HS-mode
      include: Extend get_insn() to read instruction from VS/VU mode
      lib: Emulate HTIMEDELTA CSR for platforms not having TIME CSR
      Makefile: Minor fix in OPENSBI_VERSION_GIT
      lib: Fix coldboot race condition observed on emulators/simulators
      include: Bump-up version to 0.5

Atish Patra (16):
      lib: Provide an atomic exchange function unsigned long
      lib: Fix race conditions in tlb fifo access.
      platform: Remove the ipi_sync method from all platforms.
      lib: Fix timer for 32 bit
      lib: Support atomic swap instructions
      lib: Upgrade to full flush if size is at least threshold
      docs: Update the fu540 platform guide as per U-Boot documents.
      lib: Change tlb range flush threshold to 4k page instead of 1G
      lib: provide a platform specific tlb range flush threshold
      lib: Fix tlb flush range limit value
      Test: Move test payload related code out of interface header
      lib: Align error codes as per SBI specification.
      lib: Rename existing SBI implementation as 0.1.
      lib: Remove redundant variable assignment
      lib: Implement SBI v0.2
      lib: Provide a platform hook to implement vendor specific SBI extensions.

Bin Meng (6):
      platform: sifive: fu540: Use standard value string for cpu node status
      README: Document 32-bit / 64-bit images build
      treewide: Use conventional names for 32-bit and 64-bit
      platform: sifive: fu540: Expand FDT size before any patching
      firmware: Use macro instead of magic number for boot status
      docs: platform: Update descriptions for qemu/sifive_u support

Damien Le Moal (4):
      kendryte/k210: Use sifive UART driver
      kendryte/k210: remove sysctl code
      README: Update license information
      kendryte/k210: remove unused file

Georg Kotheimer (1):
      utils: Use cpu_to_fdt32() when writing to fdt

Jacob Garber (4):
      lib: Use bitwise & instead of boolean &&
      lib: Use correct type for return value
      lib: Prevent unintended sign extensions
      lib: Correct null pointer check

Lukas Auer (1):
      firmware: do not use relocated _boot_status before it is valid

Nylon Chen (3):
      firmware: Fix the loop condition of _wait_relocate_copy_done section
      platform: Add Andes AE350 initial support
      scripts: Add AE350 to platform list in the binary archive script

Palmer Dabbelt (1):
      Include `git describe` in OpenSBI

Zong Li (1):
      Write MSIP by using memory-mapped control register

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 6911fde41006b2afe3510755c4cff259ca56c1d9
      
https://github.com/qemu/qemu/commit/6911fde41006b2afe3510755c4cff259ca56c1d9
  Author: Alistair Francis <address@hidden>
  Date:   2019-11-14 (Thu, 14 Nov 2019)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  riscv/virt: Increase flash size

Coreboot developers have requested that they have at least 32MB of flash
to load binaries. We currently have 32MB of flash, but it is split in
two to allow loading two flash binaries. Let's increase the flash size
from 32MB to 64MB to ensure we have a single region that is 32MB.

No QEMU release has include flash in the RISC-V virt machine, so this
isn't a breaking change.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 19bef037fe096b17edda103fd513ce6451da23c8
      
https://github.com/qemu/qemu/commit/19bef037fe096b17edda103fd513ce6451da23c8
  Author: Peter Maydell <address@hidden>
  Date:   2019-11-15 (Fri, 15 Nov 2019)

  Changed paths:
    M hw/riscv/virt.c
    M pc-bios/opensbi-riscv32-virt-fw_jump.bin
    M pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
    M pc-bios/opensbi-riscv64-virt-fw_jump.bin
    M roms/opensbi
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc2' 
into staging

RISC-V Fixes for 4.2-rc2

This contains a handful of patches that I'd like to target for 4.2:

* OpenSBI upgrade to 0.5
* Increase in the flash size of the virt board.
* A non-functional cleanup.
* A cleanup to our MIP handling that avoids atomics.

This passes "make check" and boots OpenEmbedded for me.

# gpg: Signature made Thu 14 Nov 2019 18:39:27 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.2-rc2:
  riscv/virt: Increase flash size
  opensbi: Upgrade from v0.4 to v0.5
  target/riscv: Remove atomic accesses to MIP CSR
  remove unnecessary ifdef TARGET_RISCV64

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e10bf1fe00ec...19bef037fe09