[Qemu-commits] [qemu/qemu] e6e03d: riscv: Skip checking CSR privilege level in debugg...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: e6e03dcffd3583f6fd8148108e65d514b8382c2c
      
https://github.com/qemu/qemu/commit/e6e03dcffd3583f6fd8148108e65d514b8382c2c
  Author: Bin Meng <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  riscv: Skip checking CSR privilege level in debugger mode

If we are in debugger mode, skip the CSR privilege level checking
so that we can read/write all CSRs. Otherwise we get:

(gdb) p/x $mtvec
Could not fetch register "mtvec"; remote failure reply 'E14'

when the hart is currently in S-mode.

Reported-by: Zong Li <address@hidden>
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: aacb578fad214383e6803cba35d6e1bce71f4a3f
      
https://github.com/qemu/qemu/commit/aacb578fad214383e6803cba35d6e1bce71f4a3f
  Author: Palmer Dabbelt <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  RISC-V: Handle bus errors in the page table walker

We directly access physical memory while walking the page tables on
RISC-V, but while doing so we were using cpu_ld*() which does not report
bus errors.  This patch converts the page table walker over to use
address_space_ld*(), which allows bus errors to be detected.

Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 37207e12245e0c5737a20b736b66b257ecf75d02
      
https://github.com/qemu/qemu/commit/37207e12245e0c5737a20b736b66b257ecf75d02
  Author: Palmer Dabbelt <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  RISC-V: Implement cpu_do_transaction_failed

This converts our port over from cpu_do_unassigned_access to
cpu_do_transaction_failed, as cpu_do_unassigned_access has been
deprecated.

Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 7ae05377b85fff9d4f68271fc415a43018836b4b
      
https://github.com/qemu/qemu/commit/7ae05377b85fff9d4f68271fc415a43018836b4b
  Author: Bin Meng <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/spike.h
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  riscv: hw: Drop "clock-frequency" property of cpu nodes

The "clock-frequency" property of cpu nodes isn't required. Drop it.

This is to keep in sync with Linux kernel commit below:
https://patchwork.kernel.org/patch/11133031/

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: c3a28b5d04f3b177befa1235e95e7bb09023f859
      
https://github.com/qemu/qemu/commit/c3a28b5d04f3b177befa1235e95e7bb09023f859
  Author: Bin Meng <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sifive_u: Add ethernet0 to the aliases node

U-Boot expects this alias to be in place in order to fix up the mac
address of the ethernet node.

This is to keep in sync with Linux kernel commit below:
https://patchwork.kernel.org/patch/11133033/

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 2921343b3df93e4848034ec615c01ee221212c3a
      
https://github.com/qemu/qemu/commit/2921343b3df93e4848034ec615c01ee221212c3a
  Author: Giuseppe Musacchio <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M linux-user/riscv/cpu_loop.c
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  linux-user/riscv: Propagate fault address

The CPU loop tagged all the queued signals as QEMU_SI_KILL while it was
filling the `_sigfault` part of `siginfo`: this caused QEMU to copy the
wrong fields over to the userspace program.

Make sure the fault address recorded by the MMU is is stored in the CPU
environment structure.

In case of memory faults store the exception address into `siginfo`.

Signed-off-by: Giuseppe Musacchio <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a6902ef0e3a83ea3dcf54f1919d485d4cf148506
      
https://github.com/qemu/qemu/commit/a6902ef0e3a83ea3dcf54f1919d485d4cf148506
  Author: Alistair Francis <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv/sifive_u: Add L2-LIM cache memory

On reset only a single L2 cache way is enabled, the others are exposed
as memory that can be used by early boot firmware. This L2 region is
generally disabled using the WayEnable register at a later stage in the
boot process. To allow firmware to target QEMU and the HiFive Unleashed
let's add the L2 LIM (LooselyIntegrated Memory).

Ideally we would want to adjust the size of this chunk of memory as the
L2 Cache Controller WayEnable register is incremented. Unfortunately I
don't see a nice way to handle reducing or blocking out the L2 LIM while
still allowing it be re returned to all enabled from a reset.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 1b3a230870a9f9ef2bfb674e27e4935cdcb44aa5
      
https://github.com/qemu/qemu/commit/1b3a230870a9f9ef2bfb674e27e4935cdcb44aa5
  Author: Alistair Francis <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv/sifive_u: Add QSPI memory region

The HiFive Unleashed uses is25wp256 SPI NOR flash. There is currently no
model of this in QEMU, so to allow boot firmware developers to use QEMU
to target the Unleashed let's add a chunk of memory to represent the QSPI0
memory mapped flash. This can be targeted using QEMU's -device loader
command line option.

In the future we can look at adding a model for the is25wp256 flash.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 687caef13d084b829156c7784a62d4c07316ae47
      
https://github.com/qemu/qemu/commit/687caef13d084b829156c7784a62d4c07316ae47
  Author: Alistair Francis <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv/sifive_u: Manually define the machine

Instead of using the DEFINE_MACHINE() macro to define the machine let's
do it manually. This allows us to specify machine properties.

This patch is no functional change.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: fc41ae230e73df1822558a08a790a39c934e142d
      
https://github.com/qemu/qemu/commit/fc41ae230e73df1822558a08a790a39c934e142d
  Author: Alistair Francis <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv/sifive_u: Add the start-in-flash property

Add a property that when set to true QEMU will jump from the ROM code to
the start of flash memory instead of DRAM which is the default
behaviour.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: cdfc19e456c7bb6dc7c308a7bc0bb22f3969843f
      
https://github.com/qemu/qemu/commit/cdfc19e456c7bb6dc7c308a7bc0bb22f3969843f
  Author: Alistair Francis <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  riscv/virt: Manually define the machine

Instead of using the DEFINE_MACHINE() macro to define the machine let's
do it manually. This allows us to use the machine object to create
RISCVVirtState. This is required to add children and aliases to the
machine.

This patch is no functional change.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 71eb522c406342c3cefa7a2837c7417eeb430ae1
      
https://github.com/qemu/qemu/commit/71eb522c406342c3cefa7a2837c7417eeb430ae1
  Author: Alistair Francis <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M hw/riscv/Kconfig
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  riscv/virt: Add the PFlash CFI01 device

Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash
from the ARM Virt board and the implementation is based on the ARM Virt
board. This allows users to specify flash files from the command line.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 2738b3b555efaf206b814677966e8e3510c64a8a
      
https://github.com/qemu/qemu/commit/2738b3b555efaf206b814677966e8e3510c64a8a
  Author: Alistair Francis <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  riscv/virt: Jump to pflash if specified

If the user supplied pflash to QEMU then change the reset code to jump
to the pflash base address instead of the DRAM base address.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a555ad1399c9eda9da0c5f8e40acd94d87957054
      
https://github.com/qemu/qemu/commit/a555ad1399c9eda9da0c5f8e40acd94d87957054
  Author: Jonathan Behrens <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M target/riscv/gdbstub.c

  Log Message:
  -----------
  target/riscv: Tell gdbstub the correct number of CSRs

If the number of registers reported to the gdbstub code does not match the
number in the associated XML file, then the register numbers used by the stub
may get out of sync with a remote GDB instance.

Signed-off-by: Jonathan Behrens <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ab9056ff9bdb3f95db6e7a666d10522d289f14ec
      
https://github.com/qemu/qemu/commit/ab9056ff9bdb3f95db6e7a666d10522d289f14ec
  Author: Jonathan Behrens <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M configure
    A gdb-xml/riscv-32bit-virtual.xml
    A gdb-xml/riscv-64bit-virtual.xml
    M target/riscv/gdbstub.c

  Log Message:
  -----------
  target/riscv: Expose "priv" register for GDB for reads

This patch enables a debugger to read the current privilege level via a virtual
"priv" register. When compiled with CONFIG_USER_ONLY the register is still
visible but always reports the value zero.

Signed-off-by: Jonathan Behrens <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 81d2929c41d32af138f3562f5a7b309f6eac7ca7
      
https://github.com/qemu/qemu/commit/81d2929c41d32af138f3562f5a7b309f6eac7ca7
  Author: Jonathan Behrens <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M target/riscv/gdbstub.c

  Log Message:
  -----------
  target/riscv: Make the priv register writable by GDB

Currently only PRV_U, PRV_S and PRV_M are supported, so this patch ensures that
the privilege mode is set to one of them. Once support for the H-extension is
added, this code will also need to properly update the virtualization status
when switching between VU/VS-modes and M-mode.

Signed-off-by: Jonathan Behrens <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 3aa9004f09c80290e119cd7b93dfca73ab418883
      
https://github.com/qemu/qemu/commit/3aa9004f09c80290e119cd7b93dfca73ab418883
  Author: Alistair Francis <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  riscv/boot: Fix possible memory leak

Coverity (CID 1405786) thinks that there is a possible memory leak as
we don't guarantee that the memory allocated from riscv_find_firmware()
is freed. This is a false positive, but let's tidy up the code to fix
the warning.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 9667e53573f907d4fcd6accff1c8fe525544b749
      
https://github.com/qemu/qemu/commit/9667e53573f907d4fcd6accff1c8fe525544b749
  Author: Dayeol Lee <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: PMP violation due to wrong size parameter

riscv_cpu_tlb_fill() uses the `size` parameter to check PMP violation
using pmp_hart_has_privs().
However, if the size is unknown (=0), the ending address will be
`addr - 1` as it is `addr + size - 1` in `pmp_hart_has_privs()`.
This always causes a false PMP violation on the starting address of the
range, as `addr - 1` is not in the range.

In order to fix, we just assume that all bytes from addr to the end of
the page will be accessed if the size is unknown.

Signed-off-by: Dayeol Lee <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: b13197b1a8b7ca201f114c4da704d3ed671228ab
      
https://github.com/qemu/qemu/commit/b13197b1a8b7ca201f114c4da704d3ed671228ab
  Author: Peter Maydell <address@hidden>
  Date:   2019-10-28 (Mon, 28 Oct 2019)

  Changed paths:
    M configure
    A gdb-xml/riscv-32bit-virtual.xml
    A gdb-xml/riscv-64bit-virtual.xml
    M hw/riscv/Kconfig
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/spike.h
    M include/hw/riscv/virt.h
    M linux-user/riscv/cpu_loop.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/gdbstub.c
    M target/riscv/pmp.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-sf2' 
into staging

RISC-V Patches for the 4.2 Soft Freeze, Part 2

This patch set contains a handful of small fixes for RISC-V targets that
I'd like to target for the 4.2 soft freeze.  They include:

* A fix to allow the debugger to access the state of all privilege
  modes, as opposed to just the currently executing one.
* A pair of cleanups to implement cpu_do_transaction_failed.
* Fixes to the device tree.
* The addition of various memory regions to make the sifive_u machine
  more closely match the HiFive Unleashed board.
* Fixes to our GDB interface to allow CSRs to be accessed.
* A fix to a memory leak pointed out by coverity.
* A fix that prevents PMP checks from firing incorrectly.

This passes "make chcek" and boots Open Embedded for me.

# gpg: Signature made Mon 28 Oct 2019 15:47:52 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.2-sf2:
  target/riscv: PMP violation due to wrong size parameter
  riscv/boot: Fix possible memory leak
  target/riscv: Make the priv register writable by GDB
  target/riscv: Expose "priv" register for GDB for reads
  target/riscv: Tell gdbstub the correct number of CSRs
  riscv/virt: Jump to pflash if specified
  riscv/virt: Add the PFlash CFI01 device
  riscv/virt: Manually define the machine
  riscv/sifive_u: Add the start-in-flash property
  riscv/sifive_u: Manually define the machine
  riscv/sifive_u: Add QSPI memory region
  riscv/sifive_u: Add L2-LIM cache memory
  linux-user/riscv: Propagate fault address
  riscv: sifive_u: Add ethernet0 to the aliases node
  riscv: hw: Drop "clock-frequency" property of cpu nodes
  RISC-V: Implement cpu_do_transaction_failed
  RISC-V: Handle bus errors in the page table walker
  riscv: Skip checking CSR privilege level in debugger mode

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/aaffb8533598...b13197b1a8b7