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[Qemu-commits] [qemu/qemu] 878b2b: xive: Make some device types not user
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 878b2b: xive: Make some device types not user creatable |
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Date: |
Thu, 24 Oct 2019 09:09:32 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 878b2b48ee49a24488ddf8654a59a568c864c815
https://github.com/qemu/qemu/commit/878b2b48ee49a24488ddf8654a59a568c864c815
Author: Greg Kurz <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
xive: Make some device types not user creatable
Some device types of the XIVE model are exposed to the QEMU command
line:
$ ppc64-softmmu/qemu-system-ppc64 -device help | grep xive
name "xive-end-source", desc "XIVE END Source"
name "xive-source", desc "XIVE Interrupt Source"
name "xive-tctx", desc "XIVE Interrupt Thread Context"
These are internal devices that shouldn't be instantiable by the
user. By the way, they can't be because their respective realize
functions expect link properties that can't be set from the command
line:
qemu-system-ppc64: -device xive-source: required link 'xive' not found:
Property '.xive' not found
qemu-system-ppc64: -device xive-end-source: required link 'xive' not found:
Property '.xive' not found
qemu-system-ppc64: -device xive-tctx: required link 'cpu' not found:
Property '.cpu' not found
Hide them by setting dc->user_creatable to false in their respective
class init functions.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
[dwg: Folded comment update into base patch]
Signed-off-by: David Gibson <address@hidden>
Commit: e6144bf912a69b747be43f490a815871dca4f1ed
https://github.com/qemu/qemu/commit/e6144bf912a69b747be43f490a815871dca4f1ed
Author: Greg Kurz <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/xics.c
Log Message:
-----------
xics: Make some device types not user creatable
Some device types of the XICS model are exposed to the QEMU command
line:
$ ppc64-softmmu/qemu-system-ppc64 -device help | grep ic[sp]
name "icp"
name "ics"
name "ics-spapr"
name "pnv-icp", desc "PowerNV ICP"
These are internal devices that shouldn't be instantiable by the
user. By the way, they can't be because their respective realize
functions expect link properties that can't be set from the command
line:
qemu-system-ppc64: -device icp: required link 'xics' not found:
Property '.xics' not found
qemu-system-ppc64: -device ics: required link 'xics' not found:
Property '.xics' not found
qemu-system-ppc64: -device ics-spapr: required link 'xics' not found:
Property '.xics' not found
qemu-system-ppc64: -device pnv-icp: required link 'xics' not found:
Property '.xics' not found
Hide them by setting dc->user_creatable to false in the base class
"icp" and "ics" init functions.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Message-Id: <address@hidden>
[dwg: Folded reason comment into base patch]
Signed-off-by: David Gibson <address@hidden>
Commit: 8d745875c28528a30155bfa0ca992e2202d08b96
https://github.com/qemu/qemu/commit/8d745875c28528a30155bfa0ca992e2202d08b96
Author: Stefan Brankovic <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
target/ppc: Fix for optimized vsl/vsr instructions
In previous implementation, invocation of TCG shift function could request
shift of TCG variable by 64 bits when variable 'sh' is 0, which is not
supported in TCG (values can be shifted by 0 to 63 bits). This patch fixes
this by using two separate invocation of TCG shift functions, with maximum
shift amount of 32.
Name of variable 'shifted' is changed to 'carry' so variable naming
is similar to old helper implementation.
Variables 'avrA' and 'avrB' are replaced with variable 'avr'.
Fixes: 4e6d0920e7547e6af4bbac5ffe9adfe6ea621822
Reported-by: "Paul A. Clark" <address@hidden>
Reported-by: Mark Cave-Ayland <address@hidden>
Suggested-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Brankovic <address@hidden>
Message-Id: <address@hidden>
Tested-by: Paul A. Clarke <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 106695ab1231c7883a1ea6c543434f5c74476f54
https://github.com/qemu/qemu/commit/106695ab1231c7883a1ea6c543434f5c74476f54
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/xive.c
M include/hw/ppc/xive_regs.h
Log Message:
-----------
ppc/pnv: Improve trigger data definition
The trigger data is used for both triggers of a HW source interrupts,
PHB, PSI, and triggers for rerouting interrupts between interrupt
controllers.
When an interrupt is rerouted, the trigger data follows an "END
trigger" format. In that case, the remote IC needs EAS containing an
END index to perform a lookup of an END.
An END trigger, bit0 of word0 set to '1', is defined as :
|0123|4567|0123|4567|0123|4567|0123|4567|
W0 E=1 |1P--|BLOC| END IDX |
W1 E=1 |M | END DATA |
An EAS is defined as :
|0123|4567|0123|4567|0123|4567|0123|4567|
W0 |V---|BLOC| END IDX |
W1 |M | END DATA |
The END trigger adds an extra 'PQ' bit, bit1 of word0 set to '1',
signaling that the PQ bits have been checked. That bit is unused in
the initial EAS definition.
When a HW device performs the trigger, the trigger data follows an
"EAS trigger" format because the trigger data in that case contains an
EAS index which the IC needs to look for.
An EAS trigger, bit0 of word0 set to '0', is defined as :
|0123|4567|0123|4567|0123|4567|0123|4567|
W0 E=0 |0P--|---- ---- ---- ---- ---- ---- ----|
W1 E=0 |BLOC| EAS INDEX |
There is also a 'PQ' bit, bit1 of word0 to '1', signaling that the
PQ bits have been checked.
Introduce these new trigger bits and rename the XIVE_SRCNO macros in
XIVE_EAS to reflect better the nature of the data.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 06d26eeb47de96c0fa0cc1d5e95124b0a809b3ac
https://github.com/qemu/qemu/commit/06d26eeb47de96c0fa0cc1d5e95124b0a809b3ac
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/pnv_psi.c
Log Message:
-----------
ppc/pnv: Use address_space_stq_be() when triggering an interrupt from PSI
Include the XIVE_TRIGGER_PQ bit in the trigger data which is how
hardware signals to the IC that the PQ bits of the interrupt source
have been checked.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 29cb4187497dcc6be80c9cd2a87764be89d940f6
https://github.com/qemu/qemu/commit/29cb4187497dcc6be80c9cd2a87764be89d940f6
Author: Greg Kurz <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Set VSMT to smp_threads by default
Support for setting VSMT is available in KVM since linux-4.13. Most distros
that support KVM on POWER already have it. It thus seem reasonable enough
to have the default machine to set VSMT to smp_threads.
This brings contiguous VCPU ids and thus brings their upper bound down to
the machine's max_cpus. This is especially useful for XIVE KVM devices,
which may thus allocate only one VP descriptor per VCPU.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 150e25f85baa7b7952ddd1bdfd7ff7801213ce51
https://github.com/qemu/qemu/commit/150e25f85baa7b7952ddd1bdfd7ff7801213ce51
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr, xics, xive: Introduce SpaprInterruptController QOM interface
The SpaprIrq structure is used to represent ths spapr machine's irq
backend. Except that it kind of conflates two concepts: one is the
backend proper - a specific interrupt controller that we might or
might not be using, the other is the irq configuration which covers
the layout of irq space and which interrupt controllers are allowed.
This leads to some pretty confusing code paths for the "dual"
configuration where its hooks redirect to other SpaprIrq structures
depending on the currently active irq controller.
To clean this up, we start by introducing a new
SpaprInterruptController QOM interface to represent strictly an
interrupt controller backend, not counting anything configuration
related. We implement this interface in the XICs and XIVE interrupt
controllers, and in future we'll move relevant methods from SpaprIrq
into it.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: ebd6be089b4c87554362b516c3ba530217d3f3db
https://github.com/qemu/qemu/commit/ebd6be089b4c87554362b516c3ba530217d3f3db
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr, xics, xive: Move cpu_intc_create from SpaprIrq to
SpaprInterruptController
This method essentially represents code which belongs to the interrupt
controller, but needs to be called on all possible intcs, rather than
just the currently active one. The "dual" version therefore calls
into the xics and xive versions confusingly.
Handle this more directly, by making it instead a method on the intc
backend, and always calling it on every backend that exists.
While we're there, streamline the error reporting a bit.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 0b0e52b1317f2a51704cbf32047864869763dea3
https://github.com/qemu/qemu/commit/0b0e52b1317f2a51704cbf32047864869763dea3
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_xive.h
Log Message:
-----------
spapr, xics, xive: Move irq claim and free from SpaprIrq to
SpaprInterruptController
These methods, like cpu_intc_create, really belong to the interrupt
controller, but need to be called on all possible intcs.
Like cpu_intc_create, therefore, make them methods on the intc and
always call it for all existing intcs.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 81106ddd1aee5c06e390eaffb07f857f925628f4
https://github.com/qemu/qemu/commit/81106ddd1aee5c06e390eaffb07f857f925628f4
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr: Formalize notion of active interrupt controller
spapr now has the mechanism of constructing both XICS and XIVE instances of
the SpaprInterruptController interface. However, only one of the interrupt
controllers will actually be active at any given time, depending on feature
negotiation with the guest. This is handled in the current code via
spapr_irq_current() which checks the OV5 vector from feature negotiation to
determine the current backend.
Determining the active controller at the point we need it like this
can be pretty confusing, because it makes it very non obvious at what
points the active controller can change. This can make it difficult
to reason about the code and where a change of active controller could
appear in sequence with other events.
Make this mechanism more explicit by adding an 'active_intc' pointer
and an explicit spapr_irq_update_active_intc() function to update it
from the CAS state. We also add hooks on the intc backend which will
get called when it is activated or deactivated.
For now we just introduce the switch and hooks, later patches will
actually start using them.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 7bcdbcca2f498b8c93f33241488305a3694a941c
https://github.com/qemu/qemu/commit/7bcdbcca2f498b8c93f33241488305a3694a941c
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr, xics, xive: Move set_irq from SpaprIrq to SpaprInterruptController
This method depends only on the active irq controller. Now that we've
formalized the notion of active controller we can dispatch directly through
that, rather than dispatching via SpaprIrq with the dual version having
to do a second conditional dispatch.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 328d8eb24db8ec415260ee7243adf2e3d7e81bad
https://github.com/qemu/qemu/commit/328d8eb24db8ec415260ee7243adf2e3d7e81bad
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr, xics, xive: Move print_info from SpaprIrq to SpaprInterruptController
This method depends only on the active irq controller. Now that we've
formalized the notion of active controller we can dispatch directly
through that, rather than dispatching via SpaprIrq with the dual
version having to do a second conditional dispatch.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 05289273c06de4bc6ece85a8bf672e588e34f36b
https://github.com/qemu/qemu/commit/05289273c06de4bc6ece85a8bf672e588e34f36b
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xics_spapr.h
Log Message:
-----------
spapr, xics, xive: Move dt_populate from SpaprIrq to SpaprInterruptController
This method depends only on the active irq controller. Now that we've
formalized the notion of active controller we can dispatch directly
through that, rather than dispatching via SpaprIrq with the dual
version having to do a second conditional dispatch.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 98a39a7927b510fcdd29f8237b67368a66121c84
https://github.com/qemu/qemu/commit/98a39a7927b510fcdd29f8237b67368a66121c84
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/spapr_xive_kvm.c
M hw/intc/xics_kvm.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xics_spapr.h
Log Message:
-----------
spapr, xics, xive: Match signatures for XICS and XIVE KVM connect routines
Both XICS and XIVE have routines to connect and disconnect KVM with
similar but not identical signatures. This adjusts them to match
exactly, which will be useful for further cleanups later.
While we're there, we add an explicit return value to the connect path
to streamline error reporting in the callers. We remove error
reporting the disconnect path. In the XICS case this wasn't used at
all. In the XIVE case the only error case was if the KVM device was
set up, but KVM didn't have the capability to do so which is pretty
obviously impossible.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 0a17e0c39f73080e6d5c4d9a2033a5bd475c416c
https://github.com/qemu/qemu/commit/0a17e0c39f73080e6d5c4d9a2033a5bd475c416c
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr: Remove SpaprIrq::init_kvm hook
This hook is a bit odd. The only caller is spapr_irq_init_kvm(), but
it explicitly takes an SpaprIrq *, so it's never really called through the
current SpaprIrq. Essentially this is just a way of passing through a
function pointer so that spapr_irq_init_kvm() can handle some
configuration and error handling logic without duplicating it between the
xics and xive reset paths.
So, make it just take that function pointer. Because of earlier reworks
to the KVM connect/disconnect code in the xics and xive backends we can
also eliminate some wrapper functions and streamline error handling a bit.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 567192d486cc3073eb097246acc98b200fa3d198
https://github.com/qemu/qemu/commit/567192d486cc3073eb097246acc98b200fa3d198
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr, xics, xive: Move SpaprIrq::reset hook logic into activate/deactivate
It turns out that all the logic in the SpaprIrq::reset hooks (and some in
the SpaprIrq::post_load hooks) isn't really related to resetting the irq
backend (that's handled by the backends' own reset routines). Rather its
about getting the backend ready to be the active interrupt controller or
stopping being the active interrupt controller - reset (and post_load) is
just the only time that changes at present.
To make this flow clearer, move the logic into the explicit backend
activate and deactivate hooks.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 605994e5b7d17dcc275465b4f89816d29105b238
https://github.com/qemu/qemu/commit/605994e5b7d17dcc275465b4f89816d29105b238
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_xive.h
Log Message:
-----------
spapr, xics, xive: Move SpaprIrq::post_load hook to backends
The remaining logic in the post_load hook really belongs to the interrupt
controller backends, and just needs to be called on the active controller
(after the active controller is set to the right thing based on the
incoming migration in the generic spapr_irq_post_load() logic).
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 8cbe71ecb8c1336b5ef96d64771608e02d88d4e3
https://github.com/qemu/qemu/commit/8cbe71ecb8c1336b5ef96d64771608e02d88d4e3
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_irq.c
M hw/ppc/spapr_pci.c
M include/hw/pci-host/spapr.h
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr: Remove SpaprIrq::nr_msis
The nr_msis value we use here has to line up with whether we're using
legacy or modern irq allocation. Therefore it's safer to derive it based
on legacy_irq_allocation rather than having SpaprIrq contain a canned
value.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 54255c1f65e69a3f50121f2e37b89a84de2737a5
https://github.com/qemu/qemu/commit/54255c1f65e69a3f50121f2e37b89a84de2737a5
Author: David Gibson <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr: Move SpaprIrq::nr_xirqs to SpaprMachineClass
For the benefit of peripheral device allocation, the number of available
irqs really wants to be the same on a given machine type version,
regardless of what irq backends we are using. That's the case now, but
only because we make sure the different SpaprIrq instances have the same
value except for the special legacy one.
Since this really only depends on machine type version, move the value to
SpaprMachineClass instead of SpaprIrq. This also puts the code to set it
to the lower value on old machine types right next to setting
legacy_irq_allocation, which needs to go hand in hand.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: cb97526aa47e0590a04bf90579b76584fbc0d79f
https://github.com/qemu/qemu/commit/cb97526aa47e0590a04bf90579b76584fbc0d79f
Author: Alexey Kardashevskiy <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
pseries: Update SLOF firmware image
This aims v4.2 and fixes:
1. full FDT rendering;
2. gcc9 -Waddress-of-packed-member.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 47c8c915b1628360d4d7d483e421e49b6bcfc371
https://github.com/qemu/qemu/commit/47c8c915b1628360d4d7d483e421e49b6bcfc371
Author: Greg Kurz <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Don't request to unplug the same core twice
We must not call spapr_drc_detach() on a detached DRC otherwise bad things
can happen, ie. QEMU hangs or crashes. This is easily demonstrated with
a CPU hotplug/unplug loop using QMP.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 90f8db52bb7ea387ff45ac12bb73935b7fc27794
https://github.com/qemu/qemu/commit/90f8db52bb7ea387ff45ac12bb73935b7fc27794
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr: move CPU reset after presenter creation
This change prepares ground for future changes which will reset the
interrupt presenter in the reset handler of the sPAPR and PowerNV
cores.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d1f2b4691a268306a319ea76f67421431f529a07
https://github.com/qemu/qemu/commit/d1f2b4691a268306a319ea76f67421431f529a07
Author: Greg Kurz <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr_cpu_core: Implement DeviceClass::reset
Since vCPUs aren't plugged into a bus, we manually register a reset
handler for each vCPU. We also call this handler at realize time
to ensure hot plugged vCPUs are reset before being exposed to the
guest. This results in vCPUs being reset twice at machine reset.
It doesn't break anything but it is slightly suboptimal and above
all confusing.
The hotplug path in device_set_realized() already knows how to reset
a hotplugged device if the device reset handler is present. Implement
one for sPAPR CPU cores that resets all vCPUs under a core.
While here rename spapr_cpu_reset() to spapr_reset_vcpu() for
consistency with spapr_realize_vcpu() and spapr_unrealize_vcpu().
Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
[clg: add documentation on the reset helper usage ]
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: fa06541b5d24897a4833dfb2fe03635f07f36527
https://github.com/qemu/qemu/commit/fa06541b5d24897a4833dfb2fe03635f07f36527
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/pnv_core.c
Log Message:
-----------
ppc/pnv: Introduce a PnvCore reset handler
in which individual CPUs are reset. It will ease the introduction of
future change reseting the interrupt presenter from the CPU reset
handler.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: aa5ac64b2394712b6269d0b15ba06c9c564dee92
https://github.com/qemu/qemu/commit/aa5ac64b2394712b6269d0b15ba06c9c564dee92
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_core.h
Log Message:
-----------
ppc/pnv: Add a PnvChip pointer to PnvCore
We will use it to reset the interrupt presenter from the CPU reset
handler.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d49e8a9b46e4594223806ae622af462ff7bfa158
https://github.com/qemu/qemu/commit/d49e8a9b46e4594223806ae622af462ff7bfa158
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xics.c
M hw/intc/xics_spapr.c
M hw/intc/xive.c
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/pnv.h
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/xics.h
M include/hw/ppc/xive.h
Log Message:
-----------
ppc: Reset the interrupt presenter from the CPU reset handler
On the sPAPR machine and PowerNV machine, the interrupt presenters are
created by a machine handler at the core level and are reset
independently. This is not consistent and it raises issues when it
comes to handle hot-plugged CPUs. In that case, the presenters are not
reset. This is less of an issue in XICS, although a zero MFFR could
be a concern, but in XIVE, the OS CAM line is not set and this breaks
the presenting algorithm. The current code has workarounds which need
a global cleanup.
Extend the sPAPR IRQ backend and the PowerNV Chip class with a new
cpu_intc_reset() handler called by the CPU reset handler and remove
the XiveTCTX reset handler which is now redundant.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 00d6f4db604113a88afa0b823aaa50b6d91afb9f
https://github.com/qemu/qemu/commit/00d6f4db604113a88afa0b823aaa50b6d91afb9f
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/ppc/pnv_core.c
Log Message:
-----------
ppc/pnv: Fix naming of routines realizing the CPUs
The 'vcpu' suffix is inherited from the sPAPR machine. Use better
names for PowerNV.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 97c00c54449b4ff349f85c6ce409dadd1b935a7d
https://github.com/qemu/qemu/commit/97c00c54449b4ff349f85c6ce409dadd1b935a7d
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/spapr_xive.c
M include/hw/ppc/spapr_xive.h
Log Message:
-----------
spapr/xive: Set the OS CAM line at reset
When a Virtual Processor is scheduled to run on a HW thread, the
hypervisor pushes its identifier in the OS CAM line. When running with
kernel_irqchip=off, QEMU needs to emulate the same behavior.
Set the OS CAM line when the interrupt presenter of the sPAPR core is
reset. This will also cover the case of hot-plugged CPUs.
This change also has the benefit to remove the use of CPU_FOREACH()
which can be unsafe.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 58560ad254fbda71d4daa6622d71683190070ee2
https://github.com/qemu/qemu/commit/58560ad254fbda71d4daa6622d71683190070ee2
Author: Peter Maydell <address@hidden>
Date: 2019-10-24 (Thu, 24 Oct 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/spapr_xive.c
M hw/intc/spapr_xive_kvm.c
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/intc/xive.c
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M hw/ppc/pnv_psi.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_irq.c
M hw/ppc/spapr_pci.c
M include/hw/pci-host/spapr.h
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_core.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xics.h
M include/hw/ppc/xics_spapr.h
M include/hw/ppc/xive.h
M include/hw/ppc/xive_regs.h
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20191024' into
staging
ppc patch queue 2019-10-24
Last pull request before soft freeze.
* Lots of fixes and cleanups for spapr interrupt controllers
* More SLOF updates to fix problems with full FDT rendering at CAS
time (alas, more yet are to come)
* A few other assorted changes
This isn't quite as well tested as I usually try to do before a pull
request. But I've been sick and running into some other difficulties,
and wanted to get this sent out before heading towards KVM forum.
# gpg: Signature made Thu 24 Oct 2019 09:14:31 BST
# gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>" [full]
# gpg: aka "David Gibson (Red Hat) <address@hidden>" [full]
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>" [full]
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-4.2-20191024: (28 commits)
spapr/xive: Set the OS CAM line at reset
ppc/pnv: Fix naming of routines realizing the CPUs
ppc: Reset the interrupt presenter from the CPU reset handler
ppc/pnv: Add a PnvChip pointer to PnvCore
ppc/pnv: Introduce a PnvCore reset handler
spapr_cpu_core: Implement DeviceClass::reset
spapr: move CPU reset after presenter creation
spapr: Don't request to unplug the same core twice
pseries: Update SLOF firmware image
spapr: Move SpaprIrq::nr_xirqs to SpaprMachineClass
spapr: Remove SpaprIrq::nr_msis
spapr, xics, xive: Move SpaprIrq::post_load hook to backends
spapr, xics, xive: Move SpaprIrq::reset hook logic into activate/deactivate
spapr: Remove SpaprIrq::init_kvm hook
spapr, xics, xive: Match signatures for XICS and XIVE KVM connect routines
spapr, xics, xive: Move dt_populate from SpaprIrq to SpaprInterruptController
spapr, xics, xive: Move print_info from SpaprIrq to SpaprInterruptController
spapr, xics, xive: Move set_irq from SpaprIrq to SpaprInterruptController
spapr: Formalize notion of active interrupt controller
spapr, xics, xive: Move irq claim and free from SpaprIrq to
SpaprInterruptController
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/81c1f71eeb87...58560ad254fb
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