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[Qemu-commits] [qemu/qemu] 42281e: tcg/ppc: Introduce Altivec registers
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 42281e: tcg/ppc: Introduce Altivec registers |
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Date: |
Thu, 17 Oct 2019 10:16:31 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 42281ec646f906aaa63e28daf2f6ba7ca2dd7caf
https://github.com/qemu/qemu/commit/42281ec646f906aaa63e28daf2f6ba7ca2dd7caf
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Introduce Altivec registers
Altivec supports 32 128-bit vector registers, whose names are
by convention v0 through v31.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 1838905eb3a6283b14b67e71bc1576d6b75ceadc
https://github.com/qemu/qemu/commit/1838905eb3a6283b14b67e71bc1576d6b75ceadc
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Introduce macro VX4()
Introduce macro VX4() used for encoding Altivec instructions.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: b82f769cc16b4ee7b628e7a923d3b09eb1d85a80
https://github.com/qemu/qemu/commit/b82f769cc16b4ee7b628e7a923d3b09eb1d85a80
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()
Introduce macros VRT(), VRA(), VRB(), VRC() used for encoding
elements of Altivec instructions.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 7d9dae0a102bc41ea031b358b47c243c5bc6ced9
https://github.com/qemu/qemu/commit/7d9dae0a102bc41ea031b358b47c243c5bc6ced9
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Create TCGPowerISA and have_isa
Introduce an enum to hold base < 2.06 < 3.00. Use macros to
preserve the existing have_isa_2_06 and have_isa_3_00 predicates.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 4e33fe0137b51947f00d210dbd43b4f5b65956ae
https://github.com/qemu/qemu/commit/4e33fe0137b51947f00d210dbd43b4f5b65956ae
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Replace HAVE_ISA_2_06
This is identical to have_isa_2_06, so replace it.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 63922f467a200dabc43be3eaf7edbec800365bb5
https://github.com/qemu/qemu/commit/63922f467a200dabc43be3eaf7edbec800365bb5
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Replace HAVE_ISEL macro with a variable
Previously we've been hard-coding knowledge that Power7 has ISEL, but
it was an optional instruction before that. Use the AT_HWCAP2 bit,
when present, to properly determine support.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 4b06c216826b7e4763afbecde12d3c79aecc6ce7
https://github.com/qemu/qemu/commit/4b06c216826b7e4763afbecde12d3c79aecc6ce7
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
A tcg/ppc/tcg-target.opc.h
Log Message:
-----------
tcg/ppc: Enable tcg backend vector compilation
Introduce all of the flags required to enable tcg backend vector support,
and a runtime flag to indicate the host supports Altivec instructions.
For now, do not actually set have_isa_altivec to true, because we have not
yet added all of the code to actually generate all of the required insns.
However, we must define these flags in order to disable ifndefs that create
stub versions of the functions added here.
The change to tcg_out_movi works around a buglet in tcg.c wherein if we
do not define tcg_out_dupi_vec we get a declared but not defined Werror,
but if we only declare it we get a defined but not used Werror. We need
to this change to tcg_out_movi eventually anyway, so it's no biggie.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 6ef14d7ebe81062c5cc6f1e9bd97f7882078521a
https://github.com/qemu/qemu/commit/6ef14d7ebe81062c5cc6f1e9bd97f7882078521a
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Add support for load/store/logic/comparison
Add various bits and peaces related mostly to load and store
operations. In that context, logic, compare, and splat Altivec
instructions are used, and, therefore, the support for emitting
them is included in this patch too.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: e2382972829f93104cece078e7ed4d6323189288
https://github.com/qemu/qemu/commit/e2382972829f93104cece078e7ed4d6323189288
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Add support for vector maximum/minimum
Add support for vector maximum/minimum using Altivec instructions
VMAXSB, VMAXSH, VMAXSW, VMAXUB, VMAXUH, VMAXUW, and
VMINSB, VMINSH, VMINSW, VMINUB, VMINUH, VMINUW.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: d67508117db474971dfd3fe29714ec4d15cf2393
https://github.com/qemu/qemu/commit/d67508117db474971dfd3fe29714ec4d15cf2393
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Add support for vector add/subtract
Add support for vector add/subtract using Altivec instructions:
VADDUBM, VADDUHM, VADDUWM, VSUBUBM, VSUBUHM, VSUBUWM.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: e9d1a53ae6d3a276f0d50090f80d923b9ee74631
https://github.com/qemu/qemu/commit/e9d1a53ae6d3a276f0d50090f80d923b9ee74631
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Add support for vector saturated add/subtract
Add support for vector saturated add/subtract using Altivec
instructions:
VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and
VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: dabae0971b64da3e44451e9a2a975c5bc260cf2a
https://github.com/qemu/qemu/commit/dabae0971b64da3e44451e9a2a975c5bc260cf2a
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Support vector shift by immediate
For Altivec, this is done via vector shift by vector,
and loading the immediate into a register.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: d9897efa1fd3174eca5268ba017aa39242e5ddc5
https://github.com/qemu/qemu/commit/d9897efa1fd3174eca5268ba017aa39242e5ddc5
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
M tcg/ppc/tcg-target.opc.h
Log Message:
-----------
tcg/ppc: Support vector multiply
For Altivec, this is always an expansion.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 597cf978926ca3a745482a11096de8d433c6be1c
https://github.com/qemu/qemu/commit/597cf978926ca3a745482a11096de8d433c6be1c
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Support vector dup2
This is only used for 32-bit hosts.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 68f340d4cd9f0423039e4706a6602673d7ca9101
https://github.com/qemu/qemu/commit/68f340d4cd9f0423039e4706a6602673d7ca9101
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Enable Altivec detection
Now that we have implemented the required tcg operations,
we can enable detection of host vector support.
Tested-by: Mark Cave-Ayland <address@hidden> (PPC32)
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 47c906ae6f54fa10b3f072863d8993e790a14439
https://github.com/qemu/qemu/commit/47c906ae6f54fa10b3f072863d8993e790a14439
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Update vector support for VSX
The VSX instruction set instructions include double-word loads and
stores, double-word load and splat, double-word permute, and bit
select. All of which require multiple operations in the Altivec
instruction set.
Because the VSX registers map %vsr32 to %vr0, and we have no current
intention or need to use vector registers outside %vr0-%vr19, force
on the {ax,bx,cx,tx} bits within the added VSX insns so that we don't
have to otherwise modify the VR[TABC] macros.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Commit: 64ff1c6d21745f2be89c76604391ae454f8490d0
https://github.com/qemu/qemu/commit/64ff1c6d21745f2be89c76604391ae454f8490d0
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Update vector support for v2.07 Altivec
These new instructions are conditional only on MSR.VEC and
are thus part of the Altivec instruction set, and not VSX.
This includes lots of double-word arithmetic and a few extra
logical operations.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: b2dda6400c1ef10b7918a7775997575b174062b3
https://github.com/qemu/qemu/commit/b2dda6400c1ef10b7918a7775997575b174062b3
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Update vector support for v2.07 VSX
These new instructions are conditional only on MSR.VSX and
are thus part of the VSX instruction set, and not Altivec.
This includes double-word loads and stores.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 7097312d37d3021cac9bb30a7f8c4660d2a25cd0
https://github.com/qemu/qemu/commit/7097312d37d3021cac9bb30a7f8c4660d2a25cd0
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Update vector support for v2.07 FP
These new instructions are conditional on MSR.FP when TX=0 and
MSR.VEC when TX=1. Since we only care about the Altivec registers,
and force TX=1, we can consider these to be Altivec instructions.
Since Altivec is true for any use of vector types, we only need
test have_isa_2_07.
This includes moves to and from the integer registers.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: d7cd6a2f251c54c989fa35858beafe4a25c789af
https://github.com/qemu/qemu/commit/d7cd6a2f251c54c989fa35858beafe4a25c789af
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Update vector support for v3.00 Altivec
These new instructions are conditional only on MSR.VEC and
are thus part of the Altivec instruction set, and not VSX.
This includes negation and compare not equal.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 6e11cde15074a9b218d89bfb9bbf8ac6f7a881c5
https://github.com/qemu/qemu/commit/6e11cde15074a9b218d89bfb9bbf8ac6f7a881c5
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Update vector support for v3.00 load/store
These new instructions are a mix of those like LXSD that are
only conditional only on MSR.VEC and those like LXV that are
conditional on MSR.VEC for TX=1. Thus, in the end, we can
consider all of these as Altivec instructions.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: b7ce3cff21e1c944a17ddfc088545d8662a278a7
https://github.com/qemu/qemu/commit/b7ce3cff21e1c944a17ddfc088545d8662a278a7
Author: Richard Henderson <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: Update vector support for v3.00 dup/dupi
These new instructions are conditional on MSR.VEC for TX=1,
so we can consider these Altivec instructions.
Tested-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: e8f22f76845e08ec838d5198a8c25d207ba52ff0
https://github.com/qemu/qemu/commit/e8f22f76845e08ec838d5198a8c25d207ba52ff0
Author: Alex Bennée <address@hidden>
Date: 2019-10-14 (Mon, 14 Oct 2019)
Changed paths:
M cpus.c
Log Message:
-----------
cpus: kick all vCPUs when running thread=single
qemu_cpu_kick is used for a number of reasons including to indicate
there is work to be done. However when thread=single the old
qemu_cpu_kick_rr_cpu only advanced the vCPU to the next executing one
which can lead to a hang in the case that:
a) the kick is from outside the vCPUs (e.g. iothread)
b) the timers are paused (i.e. iothread calling run_on_cpu)
To avoid this lets split qemu_cpu_kick_rr into two functions. One for
the timer which continues to advance to the next timeslice and another
for all other kicks.
Message-Id: <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: f22f553efffd083ff624be116726f843a39f1148
https://github.com/qemu/qemu/commit/f22f553efffd083ff624be116726f843a39f1148
Author: Peter Maydell <address@hidden>
Date: 2019-10-17 (Thu, 17 Oct 2019)
Changed paths:
M cpus.c
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
A tcg/ppc/tcg-target.opc.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20191013' into staging
Host vector support for tcg/ppc.
Fix thread=single cpu kicking.
# gpg: Signature made Mon 14 Oct 2019 15:11:55 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "address@hidden"
# gpg: Good signature from "Richard Henderson <address@hidden>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20191013: (23 commits)
cpus: kick all vCPUs when running thread=single
tcg/ppc: Update vector support for v3.00 dup/dupi
tcg/ppc: Update vector support for v3.00 load/store
tcg/ppc: Update vector support for v3.00 Altivec
tcg/ppc: Update vector support for v2.07 FP
tcg/ppc: Update vector support for v2.07 VSX
tcg/ppc: Update vector support for v2.07 Altivec
tcg/ppc: Update vector support for VSX
tcg/ppc: Enable Altivec detection
tcg/ppc: Support vector dup2
tcg/ppc: Support vector multiply
tcg/ppc: Support vector shift by immediate
tcg/ppc: Add support for vector saturated add/subtract
tcg/ppc: Add support for vector add/subtract
tcg/ppc: Add support for vector maximum/minimum
tcg/ppc: Add support for load/store/logic/comparison
tcg/ppc: Enable tcg backend vector compilation
tcg/ppc: Replace HAVE_ISEL macro with a variable
tcg/ppc: Replace HAVE_ISA_2_06
tcg/ppc: Create TCGPowerISA and have_isa
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/39b68bc4f108...f22f553efffd
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