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[Qemu-commits] [qemu/qemu] f363d0: linux headers: update against v5.4-rc
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] f363d0: linux headers: update against v5.4-rc1 |
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Date: |
Tue, 15 Oct 2019 11:36:08 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: f363d039e883ce6eb2a4fd09b04a38cbb6c95d43
https://github.com/qemu/qemu/commit/f363d039e883ce6eb2a4fd09b04a38cbb6c95d43
Author: Eric Auger <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M include/standard-headers/asm-x86/bootparam.h
M include/standard-headers/asm-x86/kvm_para.h
M include/standard-headers/linux/ethtool.h
M include/standard-headers/linux/pci_regs.h
A include/standard-headers/linux/virtio_fs.h
M include/standard-headers/linux/virtio_ids.h
A include/standard-headers/linux/virtio_iommu.h
M include/standard-headers/linux/virtio_pmem.h
M linux-headers/asm-arm/kvm.h
M linux-headers/asm-arm/unistd-common.h
M linux-headers/asm-arm64/kvm.h
M linux-headers/asm-generic/mman-common.h
M linux-headers/asm-generic/mman.h
M linux-headers/asm-generic/unistd.h
M linux-headers/asm-mips/mman.h
M linux-headers/asm-mips/unistd_n32.h
M linux-headers/asm-mips/unistd_n64.h
M linux-headers/asm-mips/unistd_o32.h
M linux-headers/asm-powerpc/mman.h
M linux-headers/asm-powerpc/unistd_32.h
M linux-headers/asm-powerpc/unistd_64.h
M linux-headers/asm-s390/kvm.h
M linux-headers/asm-s390/unistd_32.h
M linux-headers/asm-s390/unistd_64.h
M linux-headers/asm-x86/kvm.h
M linux-headers/asm-x86/unistd.h
M linux-headers/asm-x86/unistd_32.h
M linux-headers/asm-x86/unistd_64.h
M linux-headers/asm-x86/unistd_x32.h
M linux-headers/linux/kvm.h
M linux-headers/linux/psp-sev.h
M linux-headers/linux/vfio.h
Log Message:
-----------
linux headers: update against v5.4-rc1
Update the headers against commit:
0f1a7b3fac05 ("timer-of: don't use conditional expression
with mixed 'void' types")
Signed-off-by: Eric Auger <address@hidden>
Acked-by: Marc Zyngier <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f6530926e2310147a7844a3e663230d47b3d7333
https://github.com/qemu/qemu/commit/f6530926e2310147a7844a3e663230d47b3d7333
Author: Eric Auger <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/intc/arm_gic_kvm.c
M target/arm/cpu.c
M target/arm/kvm.c
M target/arm/kvm_arm.h
Log Message:
-----------
intc/arm_gic: Support IRQ injection for more than 256 vpus
Host kernels that expose the KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 capability
allow injection of interrupts along with vcpu ids larger than 255.
Let's encode the vpcu id on 12 bits according to the upgraded KVM_IRQ_LINE
ABI when needed.
Given that we have two callsites that need to assemble
the value for kvm_set_irq(), a new helper routine, kvm_arm_set_irq
is introduced.
Without that patch qemu exits with "kvm_set_irq: Invalid argument"
message.
Signed-off-by: Eric Auger <address@hidden>
Reported-by: Zenghui Yu <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Acked-by: Marc Zyngier <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: fff9f5558d0e0813d4f80bfe1602acf225eca4fd
https://github.com/qemu/qemu/commit/fff9f5558d0e0813d4f80bfe1602acf225eca4fd
Author: Eric Auger <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/kvm.c
Log Message:
-----------
ARM: KVM: Check KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 for smp_cpus > 256
Host kernel within [4.18, 5.3] report an erroneous KVM_MAX_VCPUS=512
for ARM. The actual capability to instantiate more than 256 vcpus
was fixed in 5.4 with the upgrade of the KVM_IRQ_LINE ABI to support
vcpu id encoded on 12 bits instead of 8 and a redistributor consuming
a single KVM IO device instead of 2.
So let's check this capability when attempting to use more than 256
vcpus within any ARM kvm accelerated machine.
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Acked-by: Marc Zyngier <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b01422622b7c7293196fdaf1dbb4f495af44ecf9
https://github.com/qemu/qemu/commit/b01422622b7c7293196fdaf1dbb4f495af44ecf9
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/musicpal.c
M hw/core/ptimer.c
M hw/dma/xilinx_axidma.c
M hw/m68k/mcf5206.c
M hw/m68k/mcf5208.c
M hw/net/fsl_etsec/etsec.c
M hw/net/lan9118.c
M hw/timer/allwinner-a10-pit.c
M hw/timer/altera_timer.c
M hw/timer/arm_mptimer.c
M hw/timer/arm_timer.c
M hw/timer/cmsdk-apb-dualtimer.c
M hw/timer/cmsdk-apb-timer.c
M hw/timer/digic-timer.c
M hw/timer/etraxfs_timer.c
M hw/timer/exynos4210_mct.c
M hw/timer/exynos4210_pwm.c
M hw/timer/exynos4210_rtc.c
M hw/timer/grlib_gptimer.c
M hw/timer/imx_epit.c
M hw/timer/imx_gpt.c
M hw/timer/lm32_timer.c
M hw/timer/milkymist-sysctl.c
M hw/timer/mss-timer.c
M hw/timer/puv3_ost.c
M hw/timer/sh_timer.c
M hw/timer/slavio_timer.c
M hw/timer/xilinx_timer.c
M hw/watchdog/cmsdk-apb-watchdog.c
M include/hw/ptimer.h
M tests/ptimer-test.c
Log Message:
-----------
ptimer: Rename ptimer_init() to ptimer_init_with_bh()
Currently the ptimer design uses a QEMU bottom-half as its
mechanism for calling back into the device model using the
ptimer when the timer has expired. Unfortunately this design
is fatally flawed, because it means that there is a lag
between the ptimer updating its own state and the device
callback function updating device state, and guest accesses
to device registers between the two can return inconsistent
device state.
We want to replace the bottom-half design with one where
the guest device's callback is called either immediately
(when the ptimer triggers by timeout) or when the device
model code closes a transaction-begin/end section (when the
ptimer triggers because the device model changed the
ptimer's count value or other state). As the first step,
rename ptimer_init() to ptimer_init_with_bh(), to free up
the ptimer_init() name for the new API. We can then convert
all the ptimer users away from ptimer_init_with_bh() before
removing it entirely.
(Commit created with
git grep -l ptimer_init | xargs sed -i -e 's/ptimer_init/ptimer_init_with_bh/'
and three overlong lines folded by hand.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 78b6eaa6f3ea83d12fa698a7f0ec15a45f802d74
https://github.com/qemu/qemu/commit/78b6eaa6f3ea83d12fa698a7f0ec15a45f802d74
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/core/ptimer.c
M include/hw/ptimer.h
Log Message:
-----------
ptimer: Provide new transaction-based API
Provide the new transaction-based API. If a ptimer is created
using ptimer_init() rather than ptimer_init_with_bh(), then
instead of providing a QEMUBH, it provides a pointer to the
callback function directly, and has opted into the transaction
API. All calls to functions which modify ptimer state:
- ptimer_set_period()
- ptimer_set_freq()
- ptimer_set_limit()
- ptimer_set_count()
- ptimer_run()
- ptimer_stop()
must be between matched calls to ptimer_transaction_begin()
and ptimer_transaction_commit(). When ptimer_transaction_commit()
is called it will evaluate the state of the timer after all the
changes in the transaction, and call the callback if necessary.
In the old API the individual update functions generally would
call ptimer_trigger() immediately, which would schedule the QEMUBH.
In the new API the update functions will instead defer the
"set s->next_event and call ptimer_reload()" work to
ptimer_transaction_commit().
Because ptimer_trigger() can now immediately call into the
device code which may then call other ptimer functions that
update ptimer_state fields, we must be more careful in
ptimer_reload() not to cache fields from ptimer_state across
the ptimer_trigger() call. (This was harmless with the QEMUBH
mechanism as the BH would not be invoked until much later.)
We use assertions to check that:
* the functions modifying ptimer state are not called outside
a transaction block
* ptimer_transaction_begin() and _commit() calls are paired
* the transaction API is not used with a QEMUBH ptimer
There is some slight repetition of code:
* most of the set functions have similar looking "if s->bh
call ptimer_reload, otherwise set s->need_reload" code
* ptimer_init() and ptimer_init_with_bh() have similar code
We deliberately don't try to avoid this repetition, because
it will all be deleted when the QEMUBH version of the API
is removed.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 91b37aea0e3f344aefec4d72faf12cbcac79d64e
https://github.com/qemu/qemu/commit/91b37aea0e3f344aefec4d72faf12cbcac79d64e
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M tests/ptimer-test.c
Log Message:
-----------
tests/ptimer-test: Switch to transaction-based ptimer API
Convert the ptimer test cases to the transaction-based ptimer API,
by changing to ptimer_init(), dropping the now-unused QEMUBH
variables, and surrounding each set of changes to the ptimer
state in ptimer_transaction_begin/commit calls.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 5a65f7b5f4907ca70cb6eae1265e59ccbdfa0937
https://github.com/qemu/qemu/commit/5a65f7b5f4907ca70cb6eae1265e59ccbdfa0937
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/arm_timer.c
Log Message:
-----------
hw/timer/arm_timer.c: Switch to transaction-based ptimer API
Switch the arm_timer.c code away from bottom-half based ptimers
to the new transaction-based ptimer API. This just requires
adding begin/commit calls around the various arms of
arm_timer_write() that modify the ptimer state, and using the
new ptimer_init() function to create the timer.
Fixes: https://bugs.launchpad.net/qemu/+bug/1777777
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: d8052a2e2d39660ba657af83cf079b1fe812c163
https://github.com/qemu/qemu/commit/d8052a2e2d39660ba657af83cf079b1fe812c163
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/musicpal.c
Log Message:
-----------
hw/arm/musicpal.c: Switch to transaction-based ptimer API
Switch the musicpal code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 827c421492cb414f1d388442e2a4deb6e971fc8a
https://github.com/qemu/qemu/commit/827c421492cb414f1d388442e2a4deb6e971fc8a
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/allwinner-a10-pit.c
Log Message:
-----------
hw/timer/allwinner-a10-pit.c: Switch to transaction-based ptimer API
Switch the allwinner-a10-pit code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 581b088035a16432aece13639985235e3689363e
https://github.com/qemu/qemu/commit/581b088035a16432aece13639985235e3689363e
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/arm_mptimer.c
Log Message:
-----------
hw/timer/arm_mptimer.c: Switch to transaction-based ptimer API
Switch the arm_mptimer.c code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: da38e0680f8e5118131fd224d52e97d7db38a48c
https://github.com/qemu/qemu/commit/da38e0680f8e5118131fd224d52e97d7db38a48c
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/cmsdk-apb-dualtimer.c
Log Message:
-----------
hw/timer/cmsdk-apb-dualtimer.c: Switch to transaction-based ptimer API
Switch the cmsdk-apb-dualtimer code away from bottom-half based
ptimers to the new transaction-based ptimer API. This just requires
adding begin/commit calls around the various places that modify the
ptimer state, and using the new ptimer_init() function to create the
timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 19c12fe93ab9c65b56c7dfd467799a63c28d4bbd
https://github.com/qemu/qemu/commit/19c12fe93ab9c65b56c7dfd467799a63c28d4bbd
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/cmsdk-apb-timer.c
Log Message:
-----------
hw/timer/cmsdk-apb-timer.c: Switch to transaction-based ptimer API
Switch the cmsdk-apb-timer code away from bottom-half based ptimers
to the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 30e22c8733e8b2bed7dc77c4f9ebc7a4a4114632
https://github.com/qemu/qemu/commit/30e22c8733e8b2bed7dc77c4f9ebc7a4a4114632
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/digic-timer.c
Log Message:
-----------
hw/timer/digic-timer.c: Switch to transaction-based ptimer API
Switch the digic-timer.c code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 9ede4ec094340cd788e9260f72e64988c5738530
https://github.com/qemu/qemu/commit/9ede4ec094340cd788e9260f72e64988c5738530
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/exynos4210_mct.c
Log Message:
-----------
hw/timer/exynos4210_mct.c: Switch GFRC to transaction-based ptimer API
We want to switch the exynos MCT code away from bottom-half based ptimers to
the new transaction-based ptimer API. The MCT is complicated
and uses multiple different ptimers, so it's clearer to switch
it a piece at a time. Here we change over only the GFRC.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 50f07d76f4920988c9bddeb9854240ac9f761e2e
https://github.com/qemu/qemu/commit/50f07d76f4920988c9bddeb9854240ac9f761e2e
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/exynos4210_mct.c
Log Message:
-----------
hw/timer/exynos4210_mct.c: Switch LFRC to transaction-based ptimer API
Switch the exynos MCT LFRC timers over to the ptimer transaction API.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 6c27ee94f34fb17588dd850fd8f7870d3314338f
https://github.com/qemu/qemu/commit/6c27ee94f34fb17588dd850fd8f7870d3314338f
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/exynos4210_mct.c
Log Message:
-----------
hw/timer/exynos4210_mct.c: Switch ltick to transaction-based ptimer API
Switch the ltick ptimer over to the ptimer transaction API.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: b1b104ed977177ad72573333b592314c5f626d56
https://github.com/qemu/qemu/commit/b1b104ed977177ad72573333b592314c5f626d56
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/exynos4210_pwm.c
Log Message:
-----------
hw/timer/exynos4210_pwm.c: Switch to transaction-based ptimer API
Switch the exynos4210_pwm code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 2dd20308f77d544478b8d335b8929404f5eb2f4b
https://github.com/qemu/qemu/commit/2dd20308f77d544478b8d335b8929404f5eb2f4b
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/exynos4210_rtc.c
Log Message:
-----------
hw/timer/exynos4210_rtc.c: Switch 1Hz ptimer to transaction-based API
Switch the exynos41210_rtc 1Hz ptimer over to the transaction-based
API. (We will switch the other ptimer used by this device in a
separate commit.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 82c7f5faefeefec62e90f2764bc9bda4717007bb
https://github.com/qemu/qemu/commit/82c7f5faefeefec62e90f2764bc9bda4717007bb
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/exynos4210_rtc.c
Log Message:
-----------
hw/timer/exynos4210_rtc.c: Switch main ptimer to transaction-based API
Switch the exynos41210_rtc main ptimer over to the transaction-based
API, completing the transition for this device.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: cc2722ec83ad944505fe9371fc4a94efdf4fe90f
https://github.com/qemu/qemu/commit/cc2722ec83ad944505fe9371fc4a94efdf4fe90f
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/imx_epit.c
Log Message:
-----------
hw/timer/imx_epit.c: Switch to transaction-based ptimer API
Switch the imx_epit.c code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 1b914994ea5e995f36fe751f7ed1d8858a87b032
https://github.com/qemu/qemu/commit/1b914994ea5e995f36fe751f7ed1d8858a87b032
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/imx_gpt.c
Log Message:
-----------
hw/timer/imx_gpt.c: Switch to transaction-based ptimer API
Switch the imx_epit.c code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 00ee4b0f485a96d91beb613ccd43044e354d97df
https://github.com/qemu/qemu/commit/00ee4b0f485a96d91beb613ccd43044e354d97df
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/mss-timer.c
M include/hw/timer/mss-timer.h
Log Message:
-----------
hw/timer/mss-timerc: Switch to transaction-based ptimer API
Switch the mss-timer code away from bottom-half based ptimers to
the new transaction-based ptimer API. This just requires adding
begin/commit calls around the various places that modify the ptimer
state, and using the new ptimer_init() function to create the timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 8c9dbc6236d202bfa8ec64a6661cff8a600f5768
https://github.com/qemu/qemu/commit/8c9dbc6236d202bfa8ec64a6661cff8a600f5768
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/watchdog/cmsdk-apb-watchdog.c
Log Message:
-----------
hw/watchdog/cmsdk-apb-watchdog.c: Switch to transaction-based ptimer API
Switch the cmsdk-apb-watchdog code away from bottom-half based
ptimers to the new transaction-based ptimer API. This just requires
adding begin/commit calls around the various places that modify the
ptimer state, and using the new ptimer_init() function to create the
timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 88e4bd672e8f25f932ec3db88684406b0cc71a00
https://github.com/qemu/qemu/commit/88e4bd672e8f25f932ec3db88684406b0cc71a00
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/net/lan9118.c
Log Message:
-----------
hw/net/lan9118.c: Switch to transaction-based ptimer API
Switch the cmsdk-apb-watchdog code away from bottom-half based
ptimers to the new transaction-based ptimer API. This just requires
adding begin/commit calls around the various places that modify the
ptimer state, and using the new ptimer_init() function to create the
timer.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 1b003821d4b4898ca515619579dbcc8de7702b10
https://github.com/qemu/qemu/commit/1b003821d4b4898ca515619579dbcc8de7702b10
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Capture errno in softmmu version of set_swi_errno()
The set_swi_errno() function is called to capture the errno
from a host system call, so that we can return -1 from the
semihosting function and later allow the guest to get a more
specific error code with the SYS_ERRNO function. It comes in
two versions, one for user-only and one for softmmu. We forgot
to capture the errno in the softmmu version; fix the error.
(Semihosting calls directed to gdb are unaffected because
they go through a different code path that captures the
error return from the gdbstub call in arm_semi_cb() or
arm_semi_flen_cb().)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: f7d38cf2d0b35f707ec7a19f71030afbd8fd1491
https://github.com/qemu/qemu/commit/f7d38cf2d0b35f707ec7a19f71030afbd8fd1491
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Always set some kind of errno for failed calls
If we fail a semihosting call we should always set the
semihosting errno to something; we were failing to do
this for some of the "check inputs for sanity" cases.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: f8ad2306d157a1db494dc0747f9f9afbae72cbda
https://github.com/qemu/qemu/commit/f8ad2306d157a1db494dc0747f9f9afbae72cbda
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Correct comment about gdb syscall races
In arm_gdb_syscall() we have a comment suggesting a race
because the syscall completion callback might not happen
before the gdb_do_syscallv() call returns. The comment is
correct that the callback may not happen but incorrect about
the effects. Correct it and note the important caveat that
callers must never do any work of any kind after return from
arm_gdb_syscall() that depends on its return value.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 35e9a0a8ce4be12a86e5cedd1268ff22eeacdc9e
https://github.com/qemu/qemu/commit/35e9a0a8ce4be12a86e5cedd1268ff22eeacdc9e
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Make semihosting code hand out its own file descriptors
Currently the Arm semihosting code returns the guest file descriptors
(handles) which are simply the fd values from the host OS or the
remote gdbstub. Part of the semihosting 2.0 specification requires
that we implement special handling of opening a ":semihosting-features"
filename. Guest fds which result from opening the special file
won't correspond to host fds, so to ensure that we don't end up
with duplicate fds we need to have QEMU code control the allocation
of the fd values we give the guest.
Add in an abstraction layer which lets us allocate new guest FD
values, and translate from a guest FD value back to the host one.
This also fixes an odd hole where a semihosting guest could
use the semihosting API to read, write or close file descriptors
that it had never allocated but which were being used by QEMU itself.
(This isn't a security hole, because enabling semihosting permits
the guest to do arbitrary file access to the whole host filesystem,
and so should only be done if the guest is completely trusted.)
Currently the only kind of guest fd is one which maps to a
host fd, but in a following commit we will add one which maps
to the :semihosting-features magic data.
If the guest is migrated with an open semihosting file descriptor
then subsequent attempts to use the fd will all fail; this is
not a change from the previous situation (where the host fd
being used on the source end would not be re-opened on the
destination end).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 6ed6845532ef023ab9953e22f3aada6aa59657b9
https://github.com/qemu/qemu/commit/6ed6845532ef023ab9953e22f3aada6aa59657b9
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Restrict use of TaskState*
The semihosting code needs accuss to the linux-user only
TaskState pointer so it can set the semihosting errno per-thread
for linux-user mode. At the moment we do this by having some
ifdefs so that we define a 'ts' local in do_arm_semihosting()
which is either a real TaskState * or just a CPUARMState *,
depending on which mode we're compiling for.
This is awkward if we want to refactor do_arm_semihosting()
into other functions which might need to be passed the TaskState.
Restrict usage of the TaskState local by:
* making set_swi_errno() always take the CPUARMState pointer
and (for the linux-user version) get TaskState from that
* creating a new get_swi_errno() which reads the errno
* having the two semihosting calls which need the TaskState
for other purposes (SYS_GET_CMDLINE and SYS_HEAPINFO)
define a variable with scope restricted to just that code
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 939f5b4331b159b51c85cae1b8f0c9d82aa0dffd
https://github.com/qemu/qemu/commit/939f5b4331b159b51c85cae1b8f0c9d82aa0dffd
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Use set_swi_errno() in gdbstub callback functions
When we are routing semihosting operations through the gdbstub, the
work of sorting out the return value and setting errno if necessary
is done by callback functions which are invoked by the gdbstub code.
Clean up some ifdeffery in those functions by having them call
set_swi_errno() to set the semihosting errno.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 263eb621de9dc5295c64879edf46dafe928c8b72
https://github.com/qemu/qemu/commit/263eb621de9dc5295c64879edf46dafe928c8b72
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Factor out implementation of SYS_CLOSE
Currently for the semihosting calls which take a file descriptor
(SYS_CLOSE, SYS_WRITE, SYS_READ, SYS_ISTTY, SYS_SEEK, SYS_FLEN)
we have effectively two implementations, one for real host files
and one for when we indirect via the gdbstub. We want to add a
third one to deal with the magic :semihosting-features file.
Instead of having a three-way if statement in each of these
cases, factor out the implementation of the calls to separate
functions which we dispatch to via function pointers selected
via the GuestFDType for the guest fd.
In this commit, we set up the framework for the dispatch,
and convert the SYS_CLOSE call to use it.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 52c8a163c165f6989238638c842895dbd767fec9
https://github.com/qemu/qemu/commit/52c8a163c165f6989238638c842895dbd767fec9
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Factor out implementation of SYS_WRITE
Factor out the implementation of SYS_WRITE via the
new function tables.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 2c3a09a6208a776e036f83edbc889ead357836ab
https://github.com/qemu/qemu/commit/2c3a09a6208a776e036f83edbc889ead357836ab
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Factor out implementation of SYS_READ
Factor out the implementation of SYS_READ via the
new function tables.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 0213fa452f5076c256fa2b23eefcd79caea347f1
https://github.com/qemu/qemu/commit/0213fa452f5076c256fa2b23eefcd79caea347f1
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Factor out implementation of SYS_ISTTY
Factor out the implementation of SYS_ISTTY via the new function
tables.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 45e88ffc7633d0e8fefaf72e5ceab37a4e35a2d8
https://github.com/qemu/qemu/commit/45e88ffc7633d0e8fefaf72e5ceab37a4e35a2d8
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Factor out implementation of SYS_SEEK
Factor out the implementation of SYS_SEEK via the new function
tables.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 1631a7be3a22859e0b490c631a0c969d6b8b6230
https://github.com/qemu/qemu/commit/1631a7be3a22859e0b490c631a0c969d6b8b6230
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Factor out implementation of SYS_FLEN
Factor out the implementation of SYS_FLEN via the new
function tables.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: c46a653c3a2f96c55a47241ba9c67add0e7a3b22
https://github.com/qemu/qemu/commit/c46a653c3a2f96c55a47241ba9c67add0e7a3b22
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Implement support for semihosting feature detection
Version 2.0 of the semihosting specification added support for
allowing a guest to detect whether the implementation supported
particular features. This works by the guest opening a magic
file ":semihosting-features", which contains a fixed set of
data with some magic numbers followed by a sequence of bytes
with feature flags. The file is expected to behave sensibly
for the various semihosting calls which operate on files
(SYS_FLEN, SYS_SEEK, etc).
Implement this as another kind of guest FD using our function
table dispatch mechanism. Initially we report no extended
features, so we have just one feature flag byte which is zero.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Commit: 22a43bb9abf946a9e405e740cfd0ba887ccd4823
https://github.com/qemu/qemu/commit/22a43bb9abf946a9e405e740cfd0ba887ccd4823
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension
SH_EXT_EXIT_EXTENDED is a v2.0 semihosting extension: it
indicates that the implementation supports the SYS_EXIT_EXTENDED
function. This function allows both A64 and A32/T32 guests to
exit with a specified exit status, unlike the older SYS_EXIT
function which only allowed this for A64 guests. Implement
this extension.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Commit: 6ee18643770b360da0c8ee44aa07708caa516fa9
https://github.com/qemu/qemu/commit/6ee18643770b360da0c8ee44aa07708caa516fa9
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M target/arm/arm-semi.c
Log Message:
-----------
target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension
SH_EXT_STDOUT_STDERR is a v2.0 semihosting extension: the guest
can open ":tt" with a file mode requesting append access in
order to open stderr, in addition to the existing "open for
read for stdin or write for stdout". Implement this and
report it via the :semihosting-features data.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Commit: 1ff68783f6e94b3c1ab909f92911a04d7183241c
https://github.com/qemu/qemu/commit/1ff68783f6e94b3c1ab909f92911a04d7183241c
Author: Amithash Prasad <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/watchdog/wdt_aspeed.c
Log Message:
-----------
aspeed/wdt: Check correct register for clock source
When WDT_RESTART is written, the data is not the contents
of the WDT_CTRL register. Hence ensure we are looking at
WDT_CTRL to check if bit WDT_CTRL_1MHZ_CLK is set or not.
Signed-off-by: Amithash Prasad <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: improved Suject prefix ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2bea128c3d0b07d9b33facd24d1703438defa387
https://github.com/qemu/qemu/commit/2bea128c3d0b07d9b33facd24d1703438defa387
Author: Eddie James <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_soc.c
M hw/sd/Makefile.objs
A hw/sd/aspeed_sdhci.c
M include/hw/arm/aspeed_soc.h
A include/hw/sd/aspeed_sdhci.h
Log Message:
-----------
hw/sd/aspeed_sdhci: New device
The Aspeed SOCs have two SD/MMC controllers. Add a device that
encapsulates both of these controllers and models the Aspeed-specific
registers and behavior.
Tested by reading from mmcblk0 in Linux:
qemu-system-arm -machine romulus-bmc -nographic \
-drive file=flash-romulus,format=raw,if=mtd \
-device sd-card,drive=sd0 -drive file=_tmp/kernel,format=raw,if=sd,id=sd0
Signed-off-by: Eddie James <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: - changed the controller MMIO window size to 0x1000
- moved the MMIO mapping of the SDHCI slots at the SoC level
- merged code to add SD drives on the SD buses at the machine level ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: e09cf36321f69a9633e2171cbe45c7ce603fbcbf
https://github.com/qemu/qemu/commit/e09cf36321f69a9633e2171cbe45c7ce603fbcbf
Author: Joel Stanley <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/misc/aspeed_scu.c
M include/hw/misc/aspeed_scu.h
Log Message:
-----------
hw: aspeed_scu: Add AST2600 support
The SCU controller on the AST2600 SoC has extra registers. Increase
the number of regs of the model and introduce a new field in the class
to customize the MemoryRegion operations depending on the SoC model.
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: - improved commit log
- changed vmstate version
- reworked model integration into new object class
- included AST2600_HPLL_PARAM value ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 72d96f8e2288e4bc7b31011c0c3f00448e2cef19
https://github.com/qemu/qemu/commit/72d96f8e2288e4bc7b31011c0c3f00448e2cef19
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/aspeed_soc.c
M hw/timer/aspeed_timer.c
M include/hw/timer/aspeed_timer.h
Log Message:
-----------
aspeed/timer: Introduce an object class per SoC
The most important changes will be on the register range 0x34 - 0x3C
memops. Introduce class read/write operations to handle the
differences between SoCs.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d85c87c1d1bf4353a4cb2c19988f81b9c667f7c6
https://github.com/qemu/qemu/commit/d85c87c1d1bf4353a4cb2c19988f81b9c667f7c6
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/aspeed_timer.c
M include/hw/timer/aspeed_timer.h
Log Message:
-----------
aspeed/timer: Add support for control register 3
The AST2500 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.
This models the behaviour expected by the AST2500 while maintaining
the same behaviour for the AST2400.
The vmstate version is not increased yet because the structure is
modified again in the following patches.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: c20375dd8678eae2462a986938e6d119cb5abefa
https://github.com/qemu/qemu/commit/c20375dd8678eae2462a986938e6d119cb5abefa
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/aspeed_timer.c
M include/hw/timer/aspeed_timer.h
Log Message:
-----------
aspeed/timer: Add AST2600 support
The AST2600 timer has a third control register that is used to
implement a set-to-clear feature for the main control register.
On the AST2600, it is not configurable via 0x38 (control register 3)
as it is on the AST2500.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: fadefada4d07a3a77c4171244cded0e9af81331c
https://github.com/qemu/qemu/commit/fadefada4d07a3a77c4171244cded0e9af81331c
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/timer/aspeed_timer.c
M include/hw/timer/aspeed_timer.h
Log Message:
-----------
aspeed/timer: Add support for IRQ status register on the AST2600
The AST2600 timer replaces control register 2 with a interrupt status
register. It is set by hardware when an IRQ occurs and cleared by
software.
Modify the vmstate version to take into account the new fields.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8e00d1a97d1d0b416527debb9a0759ab8c49ec51
https://github.com/qemu/qemu/commit/8e00d1a97d1d0b416527debb9a0759ab8c49ec51
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/aspeed_soc.c
M hw/misc/aspeed_sdmc.c
M include/hw/misc/aspeed_sdmc.h
Log Message:
-----------
aspeed/sdmc: Introduce an object class per SoC
Use class handlers and class constants to differentiate the
characteristics of the memory controller and remove the 'silicon_rev'
property.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 1550d7267984b19796089f767832c30da80494ec
https://github.com/qemu/qemu/commit/1550d7267984b19796089f767832c30da80494ec
Author: Joel Stanley <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/misc/aspeed_scu.c
M hw/misc/aspeed_sdmc.c
M include/hw/misc/aspeed_sdmc.h
Log Message:
-----------
aspeed/sdmc: Add AST2600 support
The AST2600 SDMC controller is slightly different from its predecessor
(DRAM training). Max memory is now 2G on the AST2600.
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: - improved commit log
- reworked model integration into new object class ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 6112bd6d9b8e03c1c454c4785a56402573ccb16e
https://github.com/qemu/qemu/commit/6112bd6d9b8e03c1c454c4785a56402573ccb16e
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/aspeed_soc.c
M hw/watchdog/wdt_aspeed.c
M include/hw/watchdog/wdt_aspeed.h
Log Message:
-----------
watchdog/aspeed: Introduce an object class per SoC
It cleanups the current models for the Aspeed AST2400 and AST2500 SoCs
and prepares ground for future SoCs.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 6b2b2a703cad4c2138b848dcdcc65634c2823c08
https://github.com/qemu/qemu/commit/6b2b2a703cad4c2138b848dcdcc65634c2823c08
Author: Joel Stanley <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/watchdog/wdt_aspeed.c
M include/hw/arm/aspeed_soc.h
M include/hw/watchdog/wdt_aspeed.h
Log Message:
-----------
hw: wdt_aspeed: Add AST2600 support
The AST2600 has four watchdogs, and they each have a 0x40 of registers.
When running as part of an ast2600 system we must check a different
offset for the system reset control register in the SCU.
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: - reworked model integration into new object class ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: d0e250400844323a6edf783b0d8ef7545e34105f
https://github.com/qemu/qemu/commit/d0e250400844323a6edf783b0d8ef7545e34105f
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: Introduce segment operations
AST2600 will use a different encoding for the addresses defined in the
Segment Register.
Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: bcaa8ddd081cab4e1d1d4e3e83a2bf9a3f56eb2b
https://github.com/qemu/qemu/commit/bcaa8ddd081cab4e1d1d4e3e83a2bf9a3f56eb2b
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: Add AST2600 support
The AST2600 SoC SMC controller is a SPI only controller now and has a
few extensions which we will need to take into account when SW
requires it. This is enough to support u-boot and Linux.
Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 36d737ee82b2972167e97901c5271ba3f904ba71
https://github.com/qemu/qemu/commit/36d737ee82b2972167e97901c5271ba3f904ba71
Author: Rashmica Gupta <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/gpio/aspeed_gpio.c
Log Message:
-----------
hw/gpio: Add in AST2600 specific implementation
The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an
addtional two sets of 1.8V gpios.
Signed-off-by: Rashmica Gupta <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f7da1aa8fee9d0a4eb013ff8c173ead5a26e930e
https://github.com/qemu/qemu/commit/f7da1aa8fee9d0a4eb013ff8c173ead5a26e930e
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/aspeed_soc.c
M hw/i2c/aspeed_i2c.c
M include/hw/i2c/aspeed_i2c.h
Log Message:
-----------
aspeed/i2c: Introduce an object class per SoC
It prepares ground for register differences between SoCs.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 51dd49236ba4bc20575b17abab26133957e38e91
https://github.com/qemu/qemu/commit/51dd49236ba4bc20575b17abab26133957e38e91
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/i2c/aspeed_i2c.c
M include/hw/i2c/aspeed_i2c.h
Log Message:
-----------
aspeed/i2c: Add AST2600 support
The I2C controller of the AST2400 and AST2500 SoCs have one IRQ shared
by all I2C busses. The AST2600 SoC I2C controller has one IRQ per bus
and 16 busses.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 54ecafb7f98bddd75af0573e5ff6bbdf93de4da9
https://github.com/qemu/qemu/commit/54ecafb7f98bddd75af0573e5ff6bbdf93de4da9
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: Introduce an object class per SoC
It prepares ground for the AST2600.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f25c0ae1079dc0b9de02676eb3e3949a09df9f41
https://github.com/qemu/qemu/commit/f25c0ae1079dc0b9de02676eb3e3949a09df9f41
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/Makefile.objs
A hw/arm/aspeed_ast2600.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed/soc: Add AST2600 support
Initial definitions for a simple machine using an AST2600 SoC (Cortex
CPU).
The Cortex CPU and its interrupt controller are too complex to handle
in the common Aspeed SoC framework. We introduce a new Aspeed SoC
class with instance_init and realize handlers to handle the differences
with the AST2400 and the AST2500 SoCs. This will add extra work to
keep in sync both models with future extensions but it makes the code
clearer.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 519370bc63ea885ee8e69eb5dc3c64799206e5b2
https://github.com/qemu/qemu/commit/519370bc63ea885ee8e69eb5dc3c64799206e5b2
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Add support for w25q512jv
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d300db02774b2225cd8a527ee6212e093e94fdce
https://github.com/qemu/qemu/commit/d300db02774b2225cd8a527ee6212e093e94fdce
Author: Joel Stanley <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: Parameterise number of MACs
To support the ast2600's four MACs allow SoCs to specify the number
they have, and create that many.
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: - included a check on sc->macs_num when realizing the macs
- included interrupt definitions for the AST2600 ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 289251b033979234ed735a7b996a187880ed090e
https://github.com/qemu/qemu/commit/289251b033979234ed735a7b996a187880ed090e
Author: Cédric Le Goater <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/net/ftgmac100.c
M include/hw/arm/aspeed_soc.h
M include/hw/net/ftgmac100.h
Log Message:
-----------
aspeed: add support for the Aspeed MII controller of the AST2600
The AST2600 SoC has an extra controller to set the PHY registers.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 514bcf6fddff875f100f5cddc649c1e8130d4142
https://github.com/qemu/qemu/commit/514bcf6fddff875f100f5cddc649c1e8130d4142
Author: Joel Stanley <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed/soc: Add ASPEED Video stub
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2aee410712b47d461749deaeefddfb786a751157
https://github.com/qemu/qemu/commit/2aee410712b47d461749deaeefddfb786a751157
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Use the IEC binary prefix definitions
IEC binary prefixes ease code review: the unit is explicit.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Cleber Rosa <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e1ecf8c8026fc1b1a742160e69c0ab3087bc2841
https://github.com/qemu/qemu/commit/e1ecf8c8026fc1b1a742160e69c0ab3087bc2841
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/char/bcm2835_aux.c
M hw/dma/bcm2835_dma.c
M hw/intc/bcm2836_control.c
M hw/misc/bcm2835_mbox.c
M hw/misc/bcm2835_property.c
Log Message:
-----------
hw/arm/bcm2835_peripherals: Improve logging
Various logging improvements as once:
- Use 0x prefix for hex numbers
- Display value written during write accesses
- Move some logs from GUEST_ERROR to UNIMP
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Cleber Rosa <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e55a8b37904ad8aa4ec4206854c780259fddc15c
https://github.com/qemu/qemu/commit/e55a8b37904ad8aa4ec4206854c780259fddc15c
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/display/bcm2835_fb.c
M hw/dma/bcm2835_dma.c
M hw/misc/bcm2835_mbox.c
M hw/misc/bcm2835_property.c
Log Message:
-----------
hw/arm/bcm2835_peripherals: Name various address spaces
Various address spaces from the BCM2835 are reported as
'anonymous' in memory tree:
(qemu) info mtree
address-space: anonymous
0000000000000000-000000000000008f (prio 0, i/o): bcm2835-mbox
0000000000000010-000000000000001f (prio 0, i/o): bcm2835-fb
0000000000000080-000000000000008f (prio 0, i/o): bcm2835-property
address-space: anonymous
0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu
0000000000000000-000000003fffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
0000000040000000-000000007fffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
000000007e000000-000000007effffff (prio 1, i/o): alias
bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff
0000000080000000-00000000bfffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
00000000c0000000-00000000ffffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
[...]
Since the address_space_init() function takes a 'name' argument,
set it to correctly describe each address space:
(qemu) info mtree
address-space: bcm2835-mbox-memory
0000000000000000-000000000000008f (prio 0, i/o): bcm2835-mbox
0000000000000010-000000000000001f (prio 0, i/o): bcm2835-fb
0000000000000080-000000000000008f (prio 0, i/o): bcm2835-property
address-space: bcm2835-fb-memory
0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu
0000000000000000-000000003fffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
0000000040000000-000000007fffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
000000007e000000-000000007effffff (prio 1, i/o): alias
bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff
0000000080000000-00000000bfffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
00000000c0000000-00000000ffffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
address-space: bcm2835-property-memory
0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu
0000000000000000-000000003fffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
0000000040000000-000000007fffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
000000007e000000-000000007effffff (prio 1, i/o): alias
bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff
0000000080000000-00000000bfffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
00000000c0000000-00000000ffffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
address-space: bcm2835-dma-memory
0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu
0000000000000000-000000003fffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
0000000040000000-000000007fffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
000000007e000000-000000007effffff (prio 1, i/o): alias
bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff
0000000080000000-00000000bfffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
00000000c0000000-00000000ffffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Cleber Rosa <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5cd436f95066be3eb87e8767fb1a95ebdd4a9dc8
https://github.com/qemu/qemu/commit/5cd436f95066be3eb87e8767fb1a95ebdd4a9dc8
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/bcm2835_peripherals.c
M hw/arm/bcm2836.c
M include/hw/arm/raspi_platform.h
Log Message:
-----------
hw/arm/bcm2835: Rename some definitions
The UART1 is part of the AUX peripheral,
the PCM_CLOCK (yet unimplemented) is part of the CPRMAN.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 00cbd5bd74b1d9db3f39c45aea8eebeedb641051
https://github.com/qemu/qemu/commit/00cbd5bd74b1d9db3f39c45aea8eebeedb641051
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/bcm2835_peripherals.c
M include/hw/arm/bcm2835_peripherals.h
M include/hw/arm/raspi_platform.h
Log Message:
-----------
hw/arm/bcm2835: Add various unimplemented peripherals
Base addresses and sizes taken from the "BCM2835 ARM Peripherals"
datasheet from February 06 2012:
https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 19845504da1bdee4be7d0fba33da5be9efa4c11b
https://github.com/qemu/qemu/commit/19845504da1bdee4be7d0fba33da5be9efa4c11b
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/misc/bcm2835_mbox.c
M hw/misc/bcm2835_property.c
M hw/misc/trace-events
Log Message:
-----------
hw/misc/bcm2835_mbox: Add trace events
Add trace events for read/write accesses and IRQ.
Properties are structures used for the ARM particular MBOX.
Since one call in bcm2835_property.c concerns the mbox block,
name this trace event in the same bcm2835_mbox* namespace.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 69b81893bc28feb678188fbcdce52eff1609bdad
https://github.com/qemu/qemu/commit/69b81893bc28feb678188fbcdce52eff1609bdad
Author: Peter Maydell <address@hidden>
Date: 2019-10-15 (Tue, 15 Oct 2019)
Changed paths:
M hw/arm/Makefile.objs
M hw/arm/aspeed.c
A hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M hw/arm/bcm2835_peripherals.c
M hw/arm/bcm2836.c
M hw/arm/musicpal.c
M hw/arm/raspi.c
M hw/block/m25p80.c
M hw/char/bcm2835_aux.c
M hw/core/ptimer.c
M hw/display/bcm2835_fb.c
M hw/dma/bcm2835_dma.c
M hw/dma/xilinx_axidma.c
M hw/gpio/aspeed_gpio.c
M hw/i2c/aspeed_i2c.c
M hw/intc/arm_gic_kvm.c
M hw/intc/bcm2836_control.c
M hw/m68k/mcf5206.c
M hw/m68k/mcf5208.c
M hw/misc/aspeed_scu.c
M hw/misc/aspeed_sdmc.c
M hw/misc/bcm2835_mbox.c
M hw/misc/bcm2835_property.c
M hw/misc/trace-events
M hw/net/fsl_etsec/etsec.c
M hw/net/ftgmac100.c
M hw/net/lan9118.c
M hw/sd/Makefile.objs
A hw/sd/aspeed_sdhci.c
M hw/ssi/aspeed_smc.c
M hw/timer/allwinner-a10-pit.c
M hw/timer/altera_timer.c
M hw/timer/arm_mptimer.c
M hw/timer/arm_timer.c
M hw/timer/aspeed_timer.c
M hw/timer/cmsdk-apb-dualtimer.c
M hw/timer/cmsdk-apb-timer.c
M hw/timer/digic-timer.c
M hw/timer/etraxfs_timer.c
M hw/timer/exynos4210_mct.c
M hw/timer/exynos4210_pwm.c
M hw/timer/exynos4210_rtc.c
M hw/timer/grlib_gptimer.c
M hw/timer/imx_epit.c
M hw/timer/imx_gpt.c
M hw/timer/lm32_timer.c
M hw/timer/milkymist-sysctl.c
M hw/timer/mss-timer.c
M hw/timer/puv3_ost.c
M hw/timer/sh_timer.c
M hw/timer/slavio_timer.c
M hw/timer/xilinx_timer.c
M hw/watchdog/cmsdk-apb-watchdog.c
M hw/watchdog/wdt_aspeed.c
M include/hw/arm/aspeed_soc.h
M include/hw/arm/bcm2835_peripherals.h
M include/hw/arm/raspi_platform.h
M include/hw/i2c/aspeed_i2c.h
M include/hw/misc/aspeed_scu.h
M include/hw/misc/aspeed_sdmc.h
M include/hw/net/ftgmac100.h
M include/hw/ptimer.h
A include/hw/sd/aspeed_sdhci.h
M include/hw/ssi/aspeed_smc.h
M include/hw/timer/aspeed_timer.h
M include/hw/timer/mss-timer.h
M include/hw/watchdog/wdt_aspeed.h
M include/standard-headers/asm-x86/bootparam.h
M include/standard-headers/asm-x86/kvm_para.h
M include/standard-headers/linux/ethtool.h
M include/standard-headers/linux/pci_regs.h
A include/standard-headers/linux/virtio_fs.h
M include/standard-headers/linux/virtio_ids.h
A include/standard-headers/linux/virtio_iommu.h
M include/standard-headers/linux/virtio_pmem.h
M linux-headers/asm-arm/kvm.h
M linux-headers/asm-arm/unistd-common.h
M linux-headers/asm-arm64/kvm.h
M linux-headers/asm-generic/mman-common.h
M linux-headers/asm-generic/mman.h
M linux-headers/asm-generic/unistd.h
M linux-headers/asm-mips/mman.h
M linux-headers/asm-mips/unistd_n32.h
M linux-headers/asm-mips/unistd_n64.h
M linux-headers/asm-mips/unistd_o32.h
M linux-headers/asm-powerpc/mman.h
M linux-headers/asm-powerpc/unistd_32.h
M linux-headers/asm-powerpc/unistd_64.h
M linux-headers/asm-s390/kvm.h
M linux-headers/asm-s390/unistd_32.h
M linux-headers/asm-s390/unistd_64.h
M linux-headers/asm-x86/kvm.h
M linux-headers/asm-x86/unistd.h
M linux-headers/asm-x86/unistd_32.h
M linux-headers/asm-x86/unistd_64.h
M linux-headers/asm-x86/unistd_x32.h
M linux-headers/linux/kvm.h
M linux-headers/linux/psp-sev.h
M linux-headers/linux/vfio.h
M target/arm/arm-semi.c
M target/arm/cpu.c
M target/arm/kvm.c
M target/arm/kvm_arm.h
M tests/ptimer-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191015'
into staging
target-arm queue:
* Add Aspeed AST2600 SoC support (but no new board model yet)
* aspeed/wdt: Check correct register for clock source
* bcm2835: code cleanups, better logging, trace events
* implement v2.0 of the Arm semihosting specification
* provide new 'transaction-based' ptimer API and use it
for the Arm devices that use ptimers
* ARM: KVM: support more than 256 CPUs
# gpg: Signature made Tue 15 Oct 2019 18:09:42 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20191015: (67 commits)
hw/misc/bcm2835_mbox: Add trace events
hw/arm/bcm2835: Add various unimplemented peripherals
hw/arm/bcm2835: Rename some definitions
hw/arm/bcm2835_peripherals: Name various address spaces
hw/arm/bcm2835_peripherals: Improve logging
hw/arm/raspi: Use the IEC binary prefix definitions
aspeed/soc: Add ASPEED Video stub
aspeed: add support for the Aspeed MII controller of the AST2600
aspeed: Parameterise number of MACs
m25p80: Add support for w25q512jv
aspeed/soc: Add AST2600 support
aspeed: Introduce an object class per SoC
aspeed/i2c: Add AST2600 support
aspeed/i2c: Introduce an object class per SoC
hw/gpio: Add in AST2600 specific implementation
aspeed/smc: Add AST2600 support
aspeed/smc: Introduce segment operations
hw: wdt_aspeed: Add AST2600 support
watchdog/aspeed: Introduce an object class per SoC
aspeed/sdmc: Add AST2600 support
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/3af78db68176...69b81893bc28
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