[Qemu-commits] [qemu/qemu] d56974: target/arm: fix CBAR register for AArch64 CPUs

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d56974afe980b2bb8d60b17729483d80a7692400
      
https://github.com/qemu/qemu/commit/d56974afe980b2bb8d60b17729483d80a7692400
  Author: Luc Michel <address@hidden>
  Date:   2019-09-27 (Fri, 27 Sep 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: fix CBAR register for AArch64 CPUs

For AArch64 CPUs with a CBAR register, we have two views for it:
  - in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the
    full 64 bits CBAR value
  - in AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2=0)
    returns a 32 bits view such that:
      CBAR = CBAR_EL1[31:18] 0..0 CBAR_EL1[43:32]

This commit fixes the current implementation where:
  - CBAR_EL1 was returning the 32 bits view instead of the full 64 bits
    value,
  - CBAR was returning a truncated 32 bits version of the full 64 bits
    one, instead of the 32 bits view
  - CBAR was declared as cp15, opc1=4, CRn=15, CRm=0, opc2=0, which is
    the CBAR register found in the ARMv7 Cortex-Ax CPUs, but not in
    ARMv8 CPUs.

Signed-off-by: Luc Michel <address@hidden>
Message-id: address@hidden
[PMM: Added a comment about the two different kinds of CBAR]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 72ab7f9e1d811256ceca7c1d9d79f5ff72a4e0c3
      
https://github.com/qemu/qemu/commit/72ab7f9e1d811256ceca7c1d9d79f5ff72a4e0c3
  Author: Alex Bennée <address@hidden>
  Date:   2019-09-27 (Fri, 27 Sep 2019)

  Changed paths:
    M tests/tcg/Makefile.target
    M tests/tcg/aarch64/Makefile.target
    M tests/tcg/arm/Makefile.target

  Log Message:
  -----------
  tests/tcg: clean-up some comments after the de-tangling

These were missed in the recent de-tangling so have been updated to be
more actuate. I've also built up ARM_TESTS in a manner similar to
AARCH64_TESTS for better consistency.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 376214e4f499f82900e699c225f18f045f8a3c20
      
https://github.com/qemu/qemu/commit/376214e4f499f82900e699c225f18f045f8a3c20
  Author: Alex Bennée <address@hidden>
  Date:   2019-09-27 (Fri, 27 Sep 2019)

  Changed paths:
    M target/arm/m_helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: handle M-profile semihosting at translate time

We do this for other semihosting calls so we might as well do it for
M-profile as well.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5651697f1f405a023378cbd35e3528788fed2166
      
https://github.com/qemu/qemu/commit/5651697f1f405a023378cbd35e3528788fed2166
  Author: Alex Bennée <address@hidden>
  Date:   2019-09-27 (Fri, 27 Sep 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: handle A-profile semihosting at translate time

As for the other semihosting calls we can resolve this at translate
time.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ed6e6ba9c4c0539e4f9ef534bc88d487262a9063
      
https://github.com/qemu/qemu/commit/ed6e6ba9c4c0539e4f9ef534bc88d487262a9063
  Author: Alex Bennée <address@hidden>
  Date:   2019-09-27 (Fri, 27 Sep 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: remove run time semihosting checks

Now we do all our checking and use a common EXCP_SEMIHOST for
semihosting operations we can make helper code a lot simpler.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e267255957fc82db47f96da1ff56409093b824e4
      
https://github.com/qemu/qemu/commit/e267255957fc82db47f96da1ff56409093b824e4
  Author: Alex Bennée <address@hidden>
  Date:   2019-09-27 (Fri, 27 Sep 2019)

  Changed paths:
    M linux-user/arm/cpu_loop.c
    M linux-user/arm/target_syscall.h

  Log Message:
  -----------
  target/arm: remove run-time semihosting checks for linux-user

Now we do all our checking at translate time we can make cpu_loop a
little bit simpler. We also introduce a simple linux-user semihosting
test case to defend the functionality. The out-of-tree softmmu based
semihosting tests are still more comprehensive.

Signed-off-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 83704ceff1b81b750f50464643084aa7cc5608fb
      
https://github.com/qemu/qemu/commit/83704ceff1b81b750f50464643084aa7cc5608fb
  Author: Alex Bennée <address@hidden>
  Date:   2019-09-27 (Fri, 27 Sep 2019)

  Changed paths:
    M tests/tcg/aarch64/Makefile.target
    M tests/tcg/arm/Makefile.target
    A tests/tcg/arm/semihosting.c

  Log Message:
  -----------
  tests/tcg: add linux-user semihosting smoke test for ARM

We already use semihosting for the system stuff so this is a simple
smoke test to ensure we are working OK on linux-user.

Signed-off-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ece628fcf69cbbd4b3efb6fbd203af07609467a2
      
https://github.com/qemu/qemu/commit/ece628fcf69cbbd4b3efb6fbd203af07609467a2
  Author: Peter Maydell <address@hidden>
  Date:   2019-09-27 (Fri, 27 Sep 2019)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots

If we're booting a Linux kernel directly into Non-Secure
state on a CPU which has Secure state, then make sure we
set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed
to access the FPU. Otherwise an AArch32 kernel will UNDEF as
soon as it tries to use the FPU.

It used to not matter that we didn't do this until commit
fc1120a7f5f2d4b6, where we implemented actually honouring
these NSACR bits.

The problem only exists for CPUs where EL3 is AArch32; the
equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to
not trap, 1 to trap", so the reset value of the register
permits NS access, unlike NSACR.

Fixes: fc1120a7f5
Fixes: https://bugs.launchpad.net/qemu/+bug/1844597
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: e4e34855e658b78ecac50a651cc847662ff02cfd
      
https://github.com/qemu/qemu/commit/e4e34855e658b78ecac50a651cc847662ff02cfd
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-09-27 (Fri, 27 Sep 2019)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: Use the IEC binary prefix definitions

IEC binary prefixes ease code review: the unit is explicit.

Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Stefano Garzarella <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 786d36ad416c6c199b18b78cc31eddfb784fe15d
      
https://github.com/qemu/qemu/commit/786d36ad416c6c199b18b78cc31eddfb784fe15d
  Author: Peter Maydell <address@hidden>
  Date:   2019-09-30 (Mon, 30 Sep 2019)

  Changed paths:
    M hw/arm/boot.c
    M linux-user/arm/cpu_loop.c
    M linux-user/arm/target_syscall.h
    M target/arm/helper.c
    M target/arm/m_helper.c
    M target/arm/translate.c
    M tests/tcg/aarch64/Makefile.target
    M tests/tcg/arm/Makefile.target
    A tests/tcg/arm/semihosting.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190927' 
into staging

target-arm queue:
 * Fix the CBAR register implementation for Cortex-A53,
   Cortex-A57, Cortex-A72
 * Fix direct booting of Linux kernels on emulated CPUs
   which have an AArch32 EL3 (incorrect NSACR settings
   meant they could not access the FPU)
 * semihosting cleanup: do more work at translate time
   and less work at runtime

# gpg: Signature made Fri 27 Sep 2019 15:32:43 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190927:
  hw/arm/boot: Use the IEC binary prefix definitions
  hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots
  tests/tcg: add linux-user semihosting smoke test for ARM
  target/arm: remove run-time semihosting checks for linux-user
  target/arm: remove run time semihosting checks
  target/arm: handle A-profile semihosting at translate time
  target/arm: handle M-profile semihosting at translate time
  tests/tcg: clean-up some comments after the de-tangling
  target/arm: fix CBAR register for AArch64 CPUs

Signed-off-by: Peter Maydell <address@hidden>

# Conflicts:
#       tests/tcg/arm/Makefile.target


Compare: https://github.com/qemu/qemu/compare/1e396381939b...786d36ad416c