[Qemu-commits] [qemu/qemu] 0f8d44: riscv: sifive

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[Qemu-commits] [qemu/qemu] 0f8d44: riscv: sifive_u: Add support for load

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 0f8d44: riscv: sifive_u: Add support for loading initrd
Date:	Thu, 19 Sep 2019 05:26:50 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0f8d4462498afd2f071cb5c837750b703a48ba18
      
https://github.com/qemu/qemu/commit/0f8d4462498afd2f071cb5c837750b703a48ba18
  Author: Guenter Roeck <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sifive_u: Add support for loading initrd

Add support for loading initrd with "-initrd <filename>"
to the sifive_u machine. This lets us boot into Linux without
disk drive.

Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 44e6dcd30a10e5b5d70cbf1bc248b146eabcec03
      
https://github.com/qemu/qemu/commit/44e6dcd30a10e5b5d70cbf1bc248b146eabcec03
  Author: Guenter Roeck <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sivive_u: Add dummy serial clock and aliases entry for uart

The riscv uart needs valid clocks. This requires a refereence
to the clock node. Since the SOC clock is not emulated by qemu,
add a reference to a fixed clock instead. The clock-frequency
entry in the uart node does not seem to be necessary, so drop it.

In addition to a reference to the clock, the driver also needs
an aliases entry for the serial node. Add it as well.

Without this patch, the serial driver fails to instantiate with
the following error message.

sifive-serial 10013000.uart: unable to find controller clock
sifive-serial: probe of 10013000.uart failed with error -2

when trying to boot Linux.

Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 04ece4f8205b19b31c4c6ebc481c9653c7fadd39
      
https://github.com/qemu/qemu/commit/04ece4f8205b19b31c4c6ebc481c9653c7fadd39
  Author: Guenter Roeck <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sifive_u: Fix clock-names property for ethernet node

The correct property name is clock-names, not clocks-names.

Without this patch, the Ethernet driver fails to instantiate with
the following error.

macb 100900fc.ethernet: failed to get macb_clk (-2)
macb: probe of 100900fc.ethernet failed with error -2

Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 0b84b6629d444ac31de33fb3125cb3e19740d766
      
https://github.com/qemu/qemu/commit/0b84b6629d444ac31de33fb3125cb3e19740d766
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M target/riscv/Makefile.objs
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv/pmp: Restrict priviledged PMP to system-mode emulation

The RISC-V Physical Memory Protection is restricted to privileged
modes. Restrict its compilation to QEMU system builds.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 6591efb54966cb08bfd7398261caa2fc2184efeb
      
https://github.com/qemu/qemu/commit/6591efb54966cb08bfd7398261caa2fc2184efeb
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M target/riscv/pmp.c
    M target/riscv/trace-events

  Log Message:
  -----------
  target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events

Use the always-compiled trace events, remove the now unused
RISCV_DEBUG_PMP definition.

Note pmpaddr_csr_read() could previously do out-of-bound accesses
passing addr_index >= MAX_RISCV_PMPS.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: f14d65e8992499a179ecdf1901137ce496a0a607
      
https://github.com/qemu/qemu/commit/f14d65e8992499a179ecdf1901137ce496a0a607
  Author: Alistair Francis <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_plic.c
    M include/hw/riscv/sifive_plic.h

  Log Message:
  -----------
  riscv: plic: Remove unused interrupt functions

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: b345b48078d79ebe154a50f75e66999605abcc70
      
https://github.com/qemu/qemu/commit/b345b48078d79ebe154a50f75e66999605abcc70
  Author: Alistair Francis <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Create function to test if FP is enabled

Let's create a function that tests if floating point support is
enabled. We can then protect all floating point operations based on if
they are enabled.

This patch so far doesn't change anything, it's just preparing for the
Hypervisor support for floating point operations.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Christophe de Dinechin <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 7f8dcfeb87810ce6063d351c14d01c22c3901f04
      
https://github.com/qemu/qemu/commit/7f8dcfeb87810ce6063d351c14d01c22c3901f04
  Author: Alistair Francis <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Update the Hypervisor CSRs to v0.4

Update the Hypervisor CSR addresses to match the v0.4 spec.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ddf781322820b6ea174fbe43ddc6a95e8cac8051
      
https://github.com/qemu/qemu/commit/ddf781322820b6ea174fbe43ddc6a95e8cac8051
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  riscv: rv32: Root page table address can be larger than 32-bit

For RV32, the root page table's PPN has 22 bits hence its address
bits could be larger than the maximum bits that target_ulong is
able to represent. Use hwaddr instead.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 751f8f41331951077f3fc17dd245c23b5a18b595
      
https://github.com/qemu/qemu/commit/751f8f41331951077f3fc17dd245c23b5a18b595
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/boot.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  riscv: Add a helper routine for finding firmware

This adds a helper routine for finding firmware. It is currently
used only for "-bios default" case.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 49dd180e4f3e0af8ab8a54fec5058b6cd89e5942
      
https://github.com/qemu/qemu/commit/49dd180e4f3e0af8ab8a54fec5058b6cd89e5942
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  riscv: Resolve full path of the given bios image

At present when "-bios image" is supplied, we just use the straight
path without searching for the configured data directories. Like
"-bios default", we add the same logic so that "-L" actually works.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: df42fdd6cc0df027d6f52b9abbd9cddac8f7c453
      
https://github.com/qemu/qemu/commit/df42fdd6cc0df027d6f52b9abbd9cddac8f7c453
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hmp-commands-info.hx
    M target/riscv/Makefile.objs
    A target/riscv/monitor.c

  Log Message:
  -----------
  riscv: hmp: Add a command to show virtual memory mappings

This adds 'info mem' command for RISC-V, to show virtual memory
mappings that aids debugging.

Rather than showing every valid PTE, the command compacts the
output by merging all contiguous physical address mappings into
one block and only shows the merged block mapping details.

Signed-off-by: Bin Meng <address@hidden>
Acked-by: Dr. David Alan Gilbert <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 9a2551ed6f946e96cd54ea3f3499d785a1f27c3d
      
https://github.com/qemu/qemu/commit/9a2551ed6f946e96cd54ea3f3499d785a1f27c3d
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_test.c
    M include/hw/riscv/sifive_test.h

  Log Message:
  -----------
  riscv: sifive_test: Add reset functionality

This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 1faa8f0138cf8d65b8fa59a3fd325e448a444bc4
      
https://github.com/qemu/qemu/commit/1faa8f0138cf8d65b8fa59a3fd325e448a444bc4
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_prci.c
    M hw/riscv/sifive_test.c

  Log Message:
  -----------
  riscv: hw: Remove duplicated "hw/hw.h" inclusion

Commit a27bd6c779ba ("Include hw/qdev-properties.h less") wrongly
added "hw/hw.h" to sifive_prci.c and sifive_test.c.

Another inclusion of "hw/hw.h" was later added via
commit 650d103d3ea9 ("Include hw/hw.h exactly where needed"), that
resulted in duplicated inclusion of "hw/hw.h".

Fixes: a27bd6c779ba ("Include hw/qdev-properties.h less")
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 24e398d06b42e3340be2c7ab54856802b82a1788
      
https://github.com/qemu/qemu/commit/24e398d06b42e3340be2c7ab54856802b82a1788
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  riscv: hw: Remove superfluous "linux, phandle" property

"linux,phandle" property is optional. Remove all instances in the
sifive_u, virt and spike machine device trees.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 04e7edd108308b03f8066f4385fd317aa620ea70
      
https://github.com/qemu/qemu/commit/04e7edd108308b03f8066f4385fd317aa620ea70
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell

Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: b179685b6a8c3738161d562985a5aa3ad0a65839
      
https://github.com/qemu/qemu/commit/b179685b6a8c3738161d562985a5aa3ad0a65839
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  riscv: hw: Remove not needed PLIC properties in device tree

This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 9f79638ec55411d5d120a15bd2181cc862e4fba1
      
https://github.com/qemu/qemu/commit/9f79638ec55411d5d120a15bd2181cc862e4fba1
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  riscv: hw: Change create_fdt() to return void

There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a2360c854fb56f9506d81be8b86ba577c0dbefc3
      
https://github.com/qemu/qemu/commit/a2360c854fb56f9506d81be8b86ba577c0dbefc3
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_prci.c
    M hw/riscv/sifive_test.c
    M hw/riscv/sifive_uart.c

  Log Message:
  -----------
  riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead

Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 131f0932cf0194355cbcac326c93c2830ebd5148
      
https://github.com/qemu/qemu/commit/131f0932cf0194355cbcac326c93c2830ebd5148
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_prci.c
    M hw/riscv/sifive_test.c
    M hw/riscv/sifive_uart.c

  Log Message:
  -----------
  riscv: hw: Remove the unnecessary include of target/riscv/cpu.h

The inclusion of "target/riscv/cpu.h" is unnecessary in various
sifive model drivers.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 847b6388b1cc263cbd553b07abcc2cf3b75a4656
      
https://github.com/qemu/qemu/commit/847b6388b1cc263cbd553b07abcc2cf3b75a4656
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M pc-bios/opensbi-riscv32-virt-fw_jump.bin
    M pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
    M pc-bios/opensbi-riscv64-virt-fw_jump.bin

  Log Message:
  -----------
  riscv: roms: Remove executable attribute of opensbi images

Like other binary files, the executable attribute of opensbi images
should not be set.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 9baa9f7c9f651dfc7ee8a4abd46c4036f6841f64
      
https://github.com/qemu/qemu/commit/9baa9f7c9f651dfc7ee8a4abd46c4036f6841f64
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sifive_u: Remove the unnecessary include of prci header

sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 56449d20e937e807e4fc35fa3e5a38f7636e7046
      
https://github.com/qemu/qemu/commit/56449d20e937e807e4fc35fa3e5a38f7636e7046
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/Makefile.objs
    M hw/riscv/sifive_e.c
    A hw/riscv/sifive_e_prci.c
    R hw/riscv/sifive_prci.c
    A include/hw/riscv/sifive_e_prci.h
    R include/hw/riscv/sifive_prci.h

  Log Message:
  -----------
  riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}

Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.

Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 1a5938a01fab0a04c322734f683e2348fc9d30b3
      
https://github.com/qemu/qemu/commit/1a5938a01fab0a04c322734f683e2348fc9d30b3
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_e_prci.c

  Log Message:
  -----------
  riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming

For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and
SIFIVE_E_PRCI_HFXOSCCFG_EN should be used.

Signed-off-by: Bin Meng <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: d0730344fd8f27ce5e98efd43efe594ae3a00087
      
https://github.com/qemu/qemu/commit/d0730344fd8f27ce5e98efd43efe594ae3a00087
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_e_prci.c
    M include/hw/riscv/sifive_e_prci.h

  Log Message:
  -----------
  riscv: sifive_e: prci: Update the PRCI register block size

Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 68c9a9b3eb5897bf39e6aa0aa72e5761f3bc9725
      
https://github.com/qemu/qemu/commit/68c9a9b3eb5897bf39e6aa0aa72e5761f3bc9725
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/Kconfig
    M hw/riscv/sifive_e.c

  Log Message:
  -----------
  riscv: sifive_e: Drop sifive_mmio_emulate()

Use create_unimplemented_device() instead.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 20f41c869830fdf0ac9aec8d14b766167f47ce7d
      
https://github.com/qemu/qemu/commit/20f41c869830fdf0ac9aec8d14b766167f47ce7d
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    A include/hw/riscv/sifive_cpu.h
    M include/hw/riscv/sifive_e.h
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv: Add a sifive_cpu.h to include both E and U cpu type defines

Group SiFive E and U cpu type defines into one header file.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 91c985851dd57df3b003e7bd91f1cf544b3a288d
      
https://github.com/qemu/qemu/commit/91c985851dd57df3b003e7bd91f1cf544b3a288d
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/riscv_hart.c

  Log Message:
  -----------
  riscv: hart: Extract hart realize to a separate routine

Currently riscv_harts_realize() creates all harts based on the
same cpu type given in the hart array property. With current
implementation it can only create homogeneous harts. Exact the
hart realize to a separate routine in preparation for supporting
multiple hart arrays.

Note the file header says the RISC-V hart array holds the state
of a heterogeneous array of RISC-V harts, which is not true.
Update the comment to mention homogeneous array of RISC-V harts.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e8c56787cd78f5d26285120f85bf898f5d3693b9
      
https://github.com/qemu/qemu/commit/e8c56787cd78f5d26285120f85bf898f5d3693b9
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/riscv_hart.c
    M include/hw/riscv/riscv_hart.h

  Log Message:
  -----------
  riscv: hart: Add a "hartid-base" property to RISC-V hart array

At present each hart's hartid in a RISC-V hart array is assigned
the same value of its index in the hart array. But for a system
that has multiple hart arrays, this is not the case any more.

Add a new "hartid-base" property so that hartid number can be
assigned based on the property value.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: f3d47d580402d11b73108de807031124c135e370
      
https://github.com/qemu/qemu/commit/f3d47d580402d11b73108de807031124c135e370
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv: sifive_u: Set the minimum number of cpus to 2

It is not useful if we only have one management CPU.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
[Palmer: Set default CPUs to 2]
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ecdfe393b69985eb90ac4921287439dc47ed35b4
      
https://github.com/qemu/qemu/commit/ecdfe393b69985eb90ac4921287439dc47ed35b4
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC

The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
by creating 2 CPU clusters as containers for RISC-V hart arrays to
populate heterogeneous harts.

The cpu nodes in the generated DTS have been updated as well.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ef965ce23956a9e5cde5c9e91081484ec68a4139
      
https://github.com/qemu/qemu/commit/ef965ce23956a9e5cde5c9e91081484ec68a4139
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sifive_u: Update PLIC hart topology configuration string

With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.

Suggested-by: Fabien Chouteau <address@hidden>
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 0d95299468c8f19a306b93bb9b6940ea55945db5
      
https://github.com/qemu/qemu/commit/0d95299468c8f19a306b93bb9b6940ea55945db5
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/Makefile.objs
    A hw/riscv/sifive_u_prci.c
    A include/hw/riscv/sifive_u_prci.h

  Log Message:
  -----------
  riscv: sifive: Implement PRCI model for FU540

This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e1724d09a6dc090063cad9d88d9994b9f55f5716
      
https://github.com/qemu/qemu/commit/e1724d09a6dc090063cad9d88d9994b9f55f5716
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv: sifive_u: Generate hfclk and rtcclk nodes

To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: af14c840418bee1b22e5b1bc403dcc8c69492517
      
https://github.com/qemu/qemu/commit/af14c840418bee1b22e5b1bc403dcc8c69492517
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv: sifive_u: Add PRCI block to the SoC

Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 806c64b7b0e782b7f1414478486c67df718a0f00
      
https://github.com/qemu/qemu/commit/806c64b7b0e782b7f1414478486c67df718a0f00
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u_prci.h

  Log Message:
  -----------
  riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes

Now that we have added a PRCI node, update existing UART and ethernet
nodes to reference PRCI as their clock sources, to keep in sync with
the Linux kernel device tree.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 4b55bc2b5f7ff065da5d2b813ee5153c598d3764
      
https://github.com/qemu/qemu/commit/4b55bc2b5f7ff065da5d2b813ee5153c598d3764
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv: sifive_u: Update UART base addresses and IRQs

This updates the UART base address and IRQs to match the hardware.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 5f7134d3b34955d1e99780b27ea0844ff7f778e2
      
https://github.com/qemu/qemu/commit/5f7134d3b34955d1e99780b27ea0844ff7f778e2
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sifive_u: Change UART node name in device tree

OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
use this information to locate the serial node and probe its driver.
However currently we generate the UART node name as "/soc/uart@...",
causing U-Boot fail to find the serial node in DT.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 6c141fb7dddcb1c8d8f55377c4a867682655e8f8
      
https://github.com/qemu/qemu/commit/6c141fb7dddcb1c8d8f55377c4a867682655e8f8
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
    M roms/Makefile

  Log Message:
  -----------
  riscv: roms: Update default bios for sifive_u machine

With the support of heterogeneous harts and PRCI model, it's now
possible to use the OpenSBI image (PLATFORM=sifive/fu540) built
for the real hardware.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 9fb45c62ae88726eb472656ae90683098473041a
      
https://github.com/qemu/qemu/commit/9fb45c62ae88726eb472656ae90683098473041a
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/Makefile.objs
    A hw/riscv/sifive_u_otp.c
    A include/hw/riscv/sifive_u_otp.h

  Log Message:
  -----------
  riscv: sifive: Implement a model for SiFive FU540 OTP

This implements a simple model for SiFive FU540 OTP (One-Time
Programmable) Memory interface, primarily for reading out the
stored serial number from the first 1 KiB of the 16 KiB OTP
memory reserved by SiFive for internal use.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 5461c4fefed627eac9e1cadfb5754fc985d6df89
      
https://github.com/qemu/qemu/commit/5461c4fefed627eac9e1cadfb5754fc985d6df89
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv: sifive_u: Instantiate OTP memory with a serial number

This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 7b6bb66f02bc81a6bb5d90a4fe08ab9c6841a936
      
https://github.com/qemu/qemu/commit/7b6bb66f02bc81a6bb5d90a4fe08ab9c6841a936
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/Kconfig
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv: sifive_u: Fix broken GEM support

At present the GEM support in sifive_u machine is seriously broken.
The GEM block register base was set to a weird number (0x100900FC),
which for no way could work with the cadence_gem model in QEMU.

Not like other GEM variants, the FU540-specific GEM has a management
block to control 10/100/1000Mbps link speed changes, that is mapped
to 0x100a0000. We can simply map it into MMIO space without special
handling using create_unimplemented_device().

Update the GEM node compatible string to use the official name used
by the upstream Linux kernel, and add the management block reg base
& size to the <reg> property encoding.

Tested with upstream U-Boot and Linux kernel MACB drivers.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 81e94379f75c40b77d577c6bff2d7e23c9904ccf
      
https://github.com/qemu/qemu/commit/81e94379f75c40b77d577c6bff2d7e23c9904ccf
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet

In the past we did not have a model for PRCI, hence two handcrafted
clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the
purpose of supplying hard-coded clock frequencies. But now since we
have added the PRCI support in QEMU, we don't need them any more.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: d372e7486f48f00a7a1e2db56d2795976845f5fc
      
https://github.com/qemu/qemu/commit/d372e7486f48f00a7a1e2db56d2795976845f5fc
  Author: Bin Meng <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sifive_u: Update model and compatible strings in device tree

This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a9f37afab111ddbe394574bed5f69683439d46e6
      
https://github.com/qemu/qemu/commit/a9f37afab111ddbe394574bed5f69683439d46e6
  Author: Atish Patra <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Use both register name and ABI name

Use both the generic register name and ABI name for the general purpose
registers and floating point registers.

Signed-off-by: Atish Patra <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 14115b91ddb106b3e05c74c26a056b253ca666ea
      
https://github.com/qemu/qemu/commit/14115b91ddb106b3e05c74c26a056b253ca666ea
  Author: Alistair Francis <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix mstatus dirty mask

This is meant to mask off the hypervisor bits, but a typo caused it to
mask MPP instead.

Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits")
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: bdce1a5c6d512257f83b6b6831bee2c975643bbd
      
https://github.com/qemu/qemu/commit/bdce1a5c6d512257f83b6b6831bee2c975643bbd
  Author: Alistair Francis <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point

Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb
flags.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: b3e86929189c526d22ef49e18f2f5066535f6deb
      
https://github.com/qemu/qemu/commit/b3e86929189c526d22ef49e18f2f5066535f6deb
  Author: KONRAD Frederic <address@hidden>
  Date:   2019-09-17 (Tue, 17 Sep 2019)

  Changed paths:
    M target/riscv/gdbstub.c

  Log Message:
  -----------
  gdbstub: riscv: fix the fflags registers

While debugging an application with GDB the following might happen:

(gdb) return
Make xxx return now? (y or n) y
Could not fetch register "fflags"; remote failure reply 'E14'

This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr
number (8). It should use the csr_register_map in order to reach the
riscv_cpu_get_fflags callback.

Signed-off-by: KONRAD Frederic <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 7cc0cdcd6a771010ca4a4857c4e4df966bb4e6c2
      
https://github.com/qemu/qemu/commit/7cc0cdcd6a771010ca4a4857c4e4df966bb4e6c2
  Author: Peter Maydell <address@hidden>
  Date:   2019-09-19 (Thu, 19 Sep 2019)

  Changed paths:
    M hmp-commands-info.hx
    M hw/riscv/Kconfig
    M hw/riscv/Makefile.objs
    M hw/riscv/boot.c
    M hw/riscv/riscv_hart.c
    M hw/riscv/sifive_e.c
    A hw/riscv/sifive_e_prci.c
    M hw/riscv/sifive_plic.c
    R hw/riscv/sifive_prci.c
    M hw/riscv/sifive_test.c
    M hw/riscv/sifive_u.c
    A hw/riscv/sifive_u_otp.c
    A hw/riscv/sifive_u_prci.c
    M hw/riscv/sifive_uart.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h
    M include/hw/riscv/riscv_hart.h
    A include/hw/riscv/sifive_cpu.h
    M include/hw/riscv/sifive_e.h
    A include/hw/riscv/sifive_e_prci.h
    M include/hw/riscv/sifive_plic.h
    R include/hw/riscv/sifive_prci.h
    M include/hw/riscv/sifive_test.h
    M include/hw/riscv/sifive_u.h
    A include/hw/riscv/sifive_u_otp.h
    A include/hw/riscv/sifive_u_prci.h
    M pc-bios/opensbi-riscv32-virt-fw_jump.bin
    M pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
    M pc-bios/opensbi-riscv64-virt-fw_jump.bin
    M roms/Makefile
    M target/riscv/Makefile.objs
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/gdbstub.c
    A target/riscv/monitor.c
    M target/riscv/pmp.c
    M target/riscv/trace-events

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/palmer/tags/riscv-for-master-4.2-sf1-v3' into staging

RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3

This contains quite a few patches that I'd like to target for 4.2.
They're mostly emulation fixes for the sifive_u board, which now much
more closely matches the hardware and can therefor run the same fireware
as what gets loaded onto the board.  Additional user-visible
improvements include:

* support for loading initrd files from the command line into Linux, via
  /chosen/linux,initrd-{start,end} device tree nodes.
* The conversion of LOG_TRACE to trace events.
* The addition of clock DT nodes for our uart and ethernet.

This also includes some preliminary work for the H extension patches,
but does not include the H extension patches as I haven't had time to
review them yet.

This passes my OE boot test on 32-bit and 64-bit virt machines, as well
as a 64-bit upstream Linux boot on the sifive_u machine.  It has been
fixed to actually pass "make check" this time.

Changes since v2 (never made it to the list):

* Sets the sifive_u machine default core count to 2 instead of 5.

Changes since v1 <address@hidden>:

* Sets the sifive_u machine default core count to 5 instead of 1, as
  it's impossible to have a single core sifive_u machine.

# gpg: Signature made Tue 17 Sep 2019 16:43:30 BST
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.2-sf1-v3: (48 commits)
  gdbstub: riscv: fix the fflags registers
  target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
  target/riscv: Fix mstatus dirty mask
  target/riscv: Use both register name and ABI name
  riscv: sifive_u: Update model and compatible strings in device tree
  riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
  riscv: sifive_u: Fix broken GEM support
  riscv: sifive_u: Instantiate OTP memory with a serial number
  riscv: sifive: Implement a model for SiFive FU540 OTP
  riscv: roms: Update default bios for sifive_u machine
  riscv: sifive_u: Change UART node name in device tree
  riscv: sifive_u: Update UART base addresses and IRQs
  riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
  riscv: sifive_u: Add PRCI block to the SoC
  riscv: sifive_u: Generate hfclk and rtcclk nodes
  riscv: sifive: Implement PRCI model for FU540
  riscv: sifive_u: Update PLIC hart topology configuration string
  riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
  riscv: sifive_u: Set the minimum number of cpus to 2
  riscv: hart: Add a "hartid-base" property to RISC-V hart array
  ...

Signed-off-by: Peter Maydell <address@hidden>


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