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[Qemu-commits] [qemu/qemu] cdd0f4: target/openrisc: Add DisasContext par

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] cdd0f4: target/openrisc: Add DisasContext parameter to che...
Date: Thu, 05 Sep 2019 02:25:27 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: cdd0f459ae331eb34887d38ea37ac22401e5e064
      
https://github.com/qemu/qemu/commit/cdd0f459ae331eb34887d38ea37ac22401e5e064
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Add DisasContext parameter to check_r0_write

We will need this context in the next patch.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 8bba7619b92a62aff537d295736ca5b871a89d3b
      
https://github.com/qemu/qemu/commit/8bba7619b92a62aff537d295736ca5b871a89d3b
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Replace cpu register array with a function

The writes to cpu_R[0] are now a race across threads, now that we
do code generation in parallel.  Stage the change by introducing
a function to return the temp for R0.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: d29f4368a71c6fe5de3a4424c67d4a3a2e577843
      
https://github.com/qemu/qemu/commit/d29f4368a71c6fe5de3a4424c67d4a3a2e577843
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Cache R0 in DisasContext

Finish the race condition fix from the previous patch.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: b72e3ff65880f2b894a2692e2b0a14424058a919
      
https://github.com/qemu/qemu/commit/b72e3ff65880f2b894a2692e2b0a14424058a919
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/cpu.h
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Make VR and PPC read-only

These SPRs are read-only.  The writes can simply be ignored,
as we already do for other read-only (or missing) registers.
There is no reason to mask the value in env->vr.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: c7efab4fc1fe5092136305a2cae67fca03f4f9c5
      
https://github.com/qemu/qemu/commit/c7efab4fc1fe5092136305a2cae67fca03f4f9c5
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init

These registers are read-only and implementation specific.
Initiailize VR for the first time; take the OR1200 values
from the verilog source.

Note that moving fields within CPUOpenRISCState does not
affect migration.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2
      
https://github.com/qemu/qemu/commit/8bebf7d1349d52355c5b71ca415e6ed86cb2d4d2
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Add VR2 and AVR special processor registers

Update the CPUCFG bits to arch v1.3.
Include support for AVRP for cpu "any".

Signed-off-by: Richard Henderson <address@hidden>


  Commit: 091a35165f206718ecce1f0ddf42563b81086170
      
https://github.com/qemu/qemu/commit/091a35165f206718ecce1f0ddf42563b81086170
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/fpu_helper.c

  Log Message:
  -----------
  target/openrisc: Fix lf.ftoi.s

The specification of this insn is round-to-zero.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: fe636d3722bf266c7b1bd3ca12fa53fb78ceffa0
      
https://github.com/qemu/qemu/commit/fe636d3722bf266c7b1bd3ca12fa53fb78ceffa0
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/cpu.c
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Check CPUCFG_OF32S for float insns

Make sure the OF32S insns are enabled before allowing execution.
Include the missing bit for cpu "any".

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 62f2b0389ff6fc7856b801bb5bee1c2d364d3e6c
      
https://github.com/qemu/qemu/commit/62f2b0389ff6fc7856b801bb5bee1c2d364d3e6c
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M linux-user/openrisc/target_elf.h
    M target/openrisc/cpu.c
    M target/openrisc/disas.c
    M target/openrisc/fpu_helper.c
    M target/openrisc/helper.h
    M target/openrisc/insns.decode
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Add support for ORFPX64A32

This is hardware support for double-precision floating-point using
pairs of 32-bit registers.  Fix latent bugs in the heretofore unused
helper_itofd and helper_ftoid.  Include the bit for cpu "any".
Change the default cpu for linux-user to "any".

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 2b13b4b93dc924a139d7a9350cd13c2c9479d03b
      
https://github.com/qemu/qemu/commit/2b13b4b93dc924a139d7a9350cd13c2c9479d03b
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/disas.c
    M target/openrisc/fpu_helper.c
    M target/openrisc/helper.h
    M target/openrisc/insns.decode
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Implement unordered fp comparisons

These were added to the 1.3 spec.  For OF32S, validate AVR.
But OF64A32 is itself new to 1.3 so no extra check needed.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: a465772eea8fef59bef9a9fe424b1af4866991f5
      
https://github.com/qemu/qemu/commit/a465772eea8fef59bef9a9fe424b1af4866991f5
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/fpu_helper.c
    M target/openrisc/machine.c
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Implement move to/from FPCSR

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 3e0e41ef33a841bdefaaf2fd9224fd791da9d2c6
      
https://github.com/qemu/qemu/commit/3e0e41ef33a841bdefaaf2fd9224fd791da9d2c6
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/disas.c
    M target/openrisc/insns.decode
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Implement l.adrp

This was added to the 1.3 spec.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 9e3bab08d3e3f5808cc35a59af1912bfb6fe96fd
      
https://github.com/qemu/qemu/commit/9e3bab08d3e3f5808cc35a59af1912bfb6fe96fd
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M target/openrisc/cpu.c

  Log Message:
  -----------
  target/openrisc: Update cpu "any" to v1.3

Now that the two updates from v1.3 are implemented,
update the "any" cpu to enable it.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 500efcfcf0fe2e0dae1d25637a13435ce7b6e421
      
https://github.com/qemu/qemu/commit/500efcfcf0fe2e0dae1d25637a13435ce7b6e421
  Author: Peter Maydell <address@hidden>
  Date:   2019-09-05 (Thu, 05 Sep 2019)

  Changed paths:
    M linux-user/openrisc/target_elf.h
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/disas.c
    M target/openrisc/fpu_helper.c
    M target/openrisc/helper.h
    M target/openrisc/insns.decode
    M target/openrisc/machine.c
    M target/openrisc/sys_helper.c
    M target/openrisc/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20190904' into 
staging

Updates for arch v1.3.

# gpg: Signature made Wed 04 Sep 2019 21:30:41 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Richard Henderson <address@hidden>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-or1k-20190904:
  target/openrisc: Update cpu "any" to v1.3
  target/openrisc: Implement l.adrp
  target/openrisc: Implement move to/from FPCSR
  target/openrisc: Implement unordered fp comparisons
  target/openrisc: Add support for ORFPX64A32
  target/openrisc: Check CPUCFG_OF32S for float insns
  target/openrisc: Fix lf.ftoi.s
  target/openrisc: Add VR2 and AVR special processor registers
  target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init
  target/openrisc: Make VR and PPC read-only
  target/openrisc: Cache R0 in DisasContext
  target/openrisc: Replace cpu register array with a function
  target/openrisc: Add DisasContext parameter to check_r0_write

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/a8b5ad8e1fae...500efcfcf0fe
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