[Qemu-commits] [qemu/qemu] 14776a: tcg: TCGMemOp is now accelerator inde

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[Qemu-commits] [qemu/qemu] 14776a: tcg: TCGMemOp is now accelerator inde

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 14776a: tcg: TCGMemOp is now accelerator independent MemOp
Date:	Wed, 04 Sep 2019 09:22:09 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 14776ab5a12972ea439c7fb2203a4c15a09094b4
      
https://github.com/qemu/qemu/commit/14776ab5a12972ea439c7fb2203a4c15a09094b4
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M MAINTAINERS
    M accel/tcg/cputlb.c
    A include/exec/memop.h
    M target/alpha/translate.c
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate-sve.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/hppa/translate.c
    M target/i386/translate.c
    M target/m68k/translate.c
    M target/microblaze/translate.c
    M target/mips/translate.c
    M target/openrisc/translate.c
    M target/ppc/translate.c
    M target/riscv/insn_trans/trans_rva.inc.c
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/s390x/translate.c
    M target/s390x/translate_vx.inc.c
    M target/sparc/translate.c
    M target/tilegx/translate.c
    M target/tricore/translate.c
    M tcg/README
    M tcg/aarch64/tcg-target.inc.c
    M tcg/arm/tcg-target.inc.c
    M tcg/i386/tcg-target.inc.c
    M tcg/mips/tcg-target.inc.c
    M tcg/optimize.c
    M tcg/ppc/tcg-target.inc.c
    M tcg/riscv/tcg-target.inc.c
    M tcg/s390/tcg-target.inc.c
    M tcg/sparc/tcg-target.inc.c
    M tcg/tcg-op.c
    M tcg/tcg-op.h
    M tcg/tcg.c
    M tcg/tcg.h
    M trace/mem-internal.h
    M trace/mem.h

  Log Message:
  -----------
  tcg: TCGMemOp is now accelerator independent MemOp

Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.

Target dependant attributes are conditionalized upon NEED_CPU_H.

Signed-off-by: Tony Nguyen <address@hidden>
Acked-by: David Gibson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Acked-by: Cornelia Huck <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 66b9b24375ac215cdcbdf9e14d665395360abff4
      
https://github.com/qemu/qemu/commit/66b9b24375ac215cdcbdf9e14d665395360abff4
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M include/exec/memop.h

  Log Message:
  -----------
  memory: Introduce size_memop

The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".

Introduce no-op size_memop to aid preparatory conversion of
interfaces.

Once interfaces are converted, size_memop will be implemented to
return a MemOp from size in bytes.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: e501824b3f3b3650e7cb8a509064cac01bc27c82
      
https://github.com/qemu/qemu/commit/e501824b3f3b3650e7cb8a509064cac01bc27c82
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips: Access MemoryRegion with MemOp

The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".

Convert interfaces by using no-op size_memop.

After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".

As size_memop is a no-op, this patch does not change any behaviour.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: bd8b5319be72785c59c418d03ed80c0825c57203
      
https://github.com/qemu/qemu/commit/bd8b5319be72785c59c418d03ed80c0825c57203
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M hw/s390x/s390-pci-inst.c

  Log Message:
  -----------
  hw/s390x: Access MemoryRegion with MemOp

The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".

Convert interfaces by using no-op size_memop.

After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".

As size_memop is a no-op, this patch does not change any behaviour.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Cornelia Huck <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 40f74205da313a36ff4e8b0668be3a8aa104a896
      
https://github.com/qemu/qemu/commit/40f74205da313a36ff4e8b0668be3a8aa104a896
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  hw/intc/armv7m_nic: Access MemoryRegion with MemOp

The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".

Convert interfaces by using no-op size_memop.

After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".

As size_memop is a no-op, this patch does not change any behaviour.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 062c08d1fb52e7751f2afd8141de23d1a488d5fa
      
https://github.com/qemu/qemu/commit/062c08d1fb52e7751f2afd8141de23d1a488d5fa
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M hw/virtio/virtio-pci.c

  Log Message:
  -----------
  hw/virtio: Access MemoryRegion with MemOp

The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".

Convert interfaces by using no-op size_memop.

After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".

As size_memop is a no-op, this patch does not change any behaviour.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Cornelia Huck <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 475fbf0a3c006b4aa96f423666e285d295e51e38
      
https://github.com/qemu/qemu/commit/475fbf0a3c006b4aa96f423666e285d295e51e38
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M hw/vfio/pci-quirks.c

  Log Message:
  -----------
  hw/vfio: Access MemoryRegion with MemOp

The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".

Convert interfaces by using no-op size_memop.

After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".

As size_memop is a no-op, this patch does not change any behaviour.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Cornelia Huck <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 3d9e7c3e7bf11962e1100d077e46f93f780b7310
      
https://github.com/qemu/qemu/commit/3d9e7c3e7bf11962e1100d077e46f93f780b7310
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M exec.c
    M memory_ldst.inc.c

  Log Message:
  -----------
  exec: Access MemoryRegion with MemOp

The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".

Convert interfaces by using no-op size_memop.

After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".

As size_memop is a no-op, this patch does not change any behaviour.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 4cbb198eefef41bbca703605c78875fd4fec6ef6
      
https://github.com/qemu/qemu/commit/4cbb198eefef41bbca703605c78875fd4fec6ef6
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  cputlb: Access MemoryRegion with MemOp

The memory_region_dispatch_{read|write} operand "unsigned size" is
being converted into a "MemOp op".

Convert interfaces by using no-op size_memop.

After all interfaces are converted, size_memop will be implemented
and the memory_region_dispatch_{read|write} operand "unsigned size"
will be converted into a "MemOp op".

As size_memop is a no-op, this patch does not change any behaviour.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: e67c904668d82ca4416cd91d37d9f5abcceef747
      
https://github.com/qemu/qemu/commit/e67c904668d82ca4416cd91d37d9f5abcceef747
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M include/exec/memop.h
    M include/exec/memory.h
    M memory.c

  Log Message:
  -----------
  memory: Access MemoryRegion with MemOp

Convert memory_region_dispatch_{read|write} operand "unsigned size"
into a "MemOp op".

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: c1adc2273327fef986efd2aa26414981e3144309
      
https://github.com/qemu/qemu/commit/c1adc2273327fef986efd2aa26414981e3144309
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M hw/s390x/s390-pci-inst.c

  Log Message:
  -----------
  hw/s390x: Hard code size with MO_{8|16|32|64}

Temporarily no-op size_memop was introduced to aid the conversion of
memory_region_dispatch_{read|write} operand "unsigned size" into
"MemOp op".

Now size_memop is implemented, again hard coded size but with
MO_{8|16|32|64}. This is more expressive and avoids size_memop calls.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Cornelia Huck <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 4574664677116dedb29b12150137f3888374a857
      
https://github.com/qemu/qemu/commit/4574664677116dedb29b12150137f3888374a857
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips: Hard code size with MO_{8|16|32|64}

Temporarily no-op size_memop was introduced to aid the conversion of
memory_region_dispatch_{read|write} operand "unsigned size" into
"MemOp op".

Now size_memop is implemented, again hard coded size but with
MO_{8|16|32|64}. This is more expressive and avoids size_memop calls.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 07f0834f264a79d6225202bd35ca37f74afb8df1
      
https://github.com/qemu/qemu/commit/07f0834f264a79d6225202bd35ca37f74afb8df1
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M memory_ldst.inc.c

  Log Message:
  -----------
  exec: Hard code size with MO_{8|16|32|64}

Temporarily no-op size_memop was introduced to aid the conversion of
memory_region_dispatch_{read|write} operand "unsigned size" into
"MemOp op".

Now size_memop is implemented, again hard coded size but with
MO_{8|16|32|64}. This is more expressive and avoids size_memop calls.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: d5d680cacc66ef7e3c02c81dc8f3a34eabce6dfe
      
https://github.com/qemu/qemu/commit/d5d680cacc66ef7e3c02c81dc8f3a34eabce6dfe
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c
    M exec.c
    M hw/intc/armv7m_nvic.c
    M hw/s390x/s390-pci-inst.c
    M hw/vfio/pci-quirks.c
    M hw/virtio/virtio-pci.c
    M include/exec/memory.h
    M memory.c
    M memory_ldst.inc.c

  Log Message:
  -----------
  memory: Access MemoryRegion with endianness

Preparation for collapsing the two byte swaps adjust_endianness and
handle_bswap into the former.

Call memory_region_dispatch_{read|write} with endianness encoded into
the "MemOp op" operand.

This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endianness.

Once it does handle endianness, callers with byte swaps can collapse
them into adjust_endianness.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Tony Nguyen <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: be5c4787e9a6eed12fd765d9e890f7cc6cd63220
      
https://github.com/qemu/qemu/commit/be5c4787e9a6eed12fd765d9e890f7cc6cd63220
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c
    M include/exec/memop.h

  Log Message:
  -----------
  cputlb: Replace size and endian operands for MemOp

Preparation for collapsing the two byte swaps adjust_endianness and
handle_bswap into the former.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 9bf825bf3df4ebae3af51566c8088e3f1249a910
      
https://github.com/qemu/qemu/commit/9bf825bf3df4ebae3af51566c8088e3f1249a910
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c
    M exec.c
    M hw/virtio/virtio-pci.c
    M memory.c
    M memory_ldst.inc.c

  Log Message:
  -----------
  memory: Single byte swap along the I/O path

Now that MemOp has been pushed down into the memory API, and
callers are encoding endianness, we can collapse byte swaps
along the I/O path into the accelerator and target independent
adjust_endianness.

Collapsing byte swaps along the I/O path enables additional endian
inversion logic, e.g. SPARC64 Invert Endian TTE bit, with redundant
byte swaps cancelling out.

Reviewed-by: Richard Henderson <address@hidden>
Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Tony Nguyen <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: a26fc6f5152b47f1d7ed928f9c9d462d01ff1624
      
https://github.com/qemu/qemu/commit/a26fc6f5152b47f1d7ed928f9c9d462d01ff1624
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c
    M include/exec/memattrs.h

  Log Message:
  -----------
  cputlb: Byte swap memory transaction attribute

Notice new attribute, byte swap, and force the transaction through the
memory slow path.

Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.

Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 9bed46e67e2ee54bc596ba58063ee71a5ca40923
      
https://github.com/qemu/qemu/commit/9bed46e67e2ee54bc596ba58063ee71a5ca40923
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M target/sparc/mmu_helper.c

  Log Message:
  -----------
  target/sparc: Add TLB entry with attributes

Append MemTxAttrs to interfaces so we can pass along up coming Invert
Endian TTE bit on SPARC64.

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: ccdb4c5535f41ee4da2ef158f58fca0327e50dab
      
https://github.com/qemu/qemu/commit/ccdb4c5535f41ee4da2ef158f58fca0327e50dab
  Author: Tony Nguyen <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M target/sparc/cpu.h
    M target/sparc/mmu_helper.c

  Log Message:
  -----------
  target/sparc: sun4u Invert Endian TTE bit

This bit configures endianness of PCI MMIO devices. It is used by
Solaris and OpenBSD sunhme drivers.

Tested working on OpenBSD.

Unfortunately Solaris 10 had a unrelated keyboard issue blocking
testing... another inch towards Solaris 10 on SPARC64 =)

Signed-off-by: Tony Nguyen <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Mark Cave-Ayland <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 74841f044e96644d8ed8a388fe505df5ab843d0a
      
https://github.com/qemu/qemu/commit/74841f044e96644d8ed8a388fe505df5ab843d0a
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M exec.c
    M include/hw/core/cpu.h

  Log Message:
  -----------
  exec: Move user-only watchpoint stubs inline

Let the user-only watchpoint stubs resolve to empty inline functions.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 0026348b48fe532279e8c12b100c16c1aa991373
      
https://github.com/qemu/qemu/commit/0026348b48fe532279e8c12b100c16c1aa991373
  Author: David Hildenbrand <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M exec.c
    M include/hw/core/cpu.h

  Log Message:
  -----------
  exec: Factor out core logic of check_watchpoint()

We want to perform the same checks in probe_write() to trigger a cpu
exit before doing any modifications. We'll have to pass a PC.

Signed-off-by: David Hildenbrand <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
[rth: Use vaddr for len, like other watchpoint functions;
Move user-only stub to static inline.]
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 30d7e098d5c38644359820317fcf72e3e129ec53
      
https://github.com/qemu/qemu/commit/30d7e098d5c38644359820317fcf72e3e129ec53
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c
    M include/exec/cpu-all.h

  Log Message:
  -----------
  cputlb: Fold TLB_RECHECK into TLB_INVALID_MASK

We had two different mechanisms to force a recheck of the tlb.

Before TLB_RECHECK was introduced, we had a PAGE_WRITE_INV bit
that would immediate set TLB_INVALID_MASK, which automatically
means that a second check of the tlb entry fails.

We can use the same mechanism to handle small pages.
Conserve TLB_* bits by removing TLB_RECHECK.

Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 56ad8b007dde7a61e02582e1f2d5c57fc0165a6b
      
https://github.com/qemu/qemu/commit/56ad8b007dde7a61e02582e1f2d5c57fc0165a6b
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M exec.c
    M include/hw/core/cpu.h

  Log Message:
  -----------
  exec: Factor out cpu_watchpoint_address_matches

We want to move the check for watchpoints from
memory_region_section_get_iotlb to tlb_set_page_with_attrs.
Isolate the loop over watchpoints to an exported function.

Rename the existing cpu_watchpoint_address_matches to
watchpoint_address_matches, since it doesn't actually
have a cpu argument.

Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 8f7cd2ad4acd01242d00807e231097b3de9f0930
      
https://github.com/qemu/qemu/commit/8f7cd2ad4acd01242d00807e231097b3de9f0930
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  cputlb: Fix size operand for tlb_fill on unaligned store

We are currently passing the size of the full write to
the tlb_fill for the second page.  Instead pass the real
size of the write to that page.

This argument is unused within all tlb_fill, except to be
logged via tracing, so in practice this makes no difference.

But in a moment we'll need the value of size2 for watchpoints,
and if we've computed the value we might as well use it.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 5787585d0406cfd54dda0c71ea1a603347ce6e71
      
https://github.com/qemu/qemu/commit/5787585d0406cfd54dda0c71ea1a603347ce6e71
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  cputlb: Remove double-alignment in store_helper

We have already aligned page2 to the start of the next page.
There is no reason to do that a second time.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 50b107c5d617eaf93301cef20221312e7a986701
      
https://github.com/qemu/qemu/commit/50b107c5d617eaf93301cef20221312e7a986701
  Author: Richard Henderson <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c
    M exec.c
    M include/exec/cpu-all.h

  Log Message:
  -----------
  cputlb: Handle watchpoints via TLB_WATCHPOINT

The raising of exceptions from check_watchpoint, buried inside
of the I/O subsystem, is fundamentally broken.  We do not have
the helper return address with which we can unwind guest state.

Replace PHYS_SECTION_WATCH and io_mem_watch with TLB_WATCHPOINT.
Move the call to cpu_check_watchpoint into the cputlb helpers
where we do have the helper return address.

This allows watchpoints on RAM to bypass the full i/o access path.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 03a981893c99faba84bb373976796ad7dce0aecc
      
https://github.com/qemu/qemu/commit/03a981893c99faba84bb373976796ad7dce0aecc
  Author: David Hildenbrand <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  tcg: Check for watchpoints in probe_write()

Let size > 0 indicate a promise to write to those bytes.
Check for write watchpoints in the probed range.

Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
[rth: Recompute index after tlb_fill; check TLB_WATCHPOINT.]
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 9e5bef4920b85f30e6f1588b742abb10bc840c93
      
https://github.com/qemu/qemu/commit/9e5bef4920b85f30e6f1588b742abb10bc840c93
  Author: David Hildenbrand <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M target/s390x/mem_helper.c

  Log Message:
  -----------
  s390x/tcg: Use guest_addr_valid() instead of h2g_valid() in 
probe_write_access()

If I'm not completely wrong, we are dealing with guest addresses here
and not with host addresses. Use the right check.

Fixes: c5a7392cfb96 ("s390x/tcg: Provide probe_write_access helper")
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Reviewed-by: Cornelia Huck <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 46750128631eaace54b69ddd8b63683edd4606cc
      
https://github.com/qemu/qemu/commit/46750128631eaace54b69ddd8b63683edd4606cc
  Author: David Hildenbrand <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M target/s390x/mem_helper.c

  Log Message:
  -----------
  s390x/tcg: Fix length calculation in probe_write_access()

Hm... how did that "-" slip in (-TAGRET_PAGE_SIZE would be correct). This
currently makes us exceed one page in a single probe_write() call,
essentially leaving some memory unchecked.

Fixes: c5a7392cfb96 ("s390x/tcg: Provide probe_write_access helper")
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Reviewed-by: Cornelia Huck <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 59e96ac6cb13951dd09afc70622858089abf3384
      
https://github.com/qemu/qemu/commit/59e96ac6cb13951dd09afc70622858089abf3384
  Author: David Hildenbrand <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/user-exec.c
    M include/exec/exec-all.h
    M target/s390x/mem_helper.c

  Log Message:
  -----------
  tcg: Factor out CONFIG_USER_ONLY probe_write() from s390x code

Factor it out into common code. Similar to the !CONFIG_USER_ONLY variant,
let's not allow to cross page boundaries.

Signed-off-by: David Hildenbrand <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
[rth: Move cpu & cc variables inside if block.]
Signed-off-by: Richard Henderson <address@hidden>


  Commit: ca86cf328ce216bb304bbf09a43614613f945d86
      
https://github.com/qemu/qemu/commit/ca86cf328ce216bb304bbf09a43614613f945d86
  Author: David Hildenbrand <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c

  Log Message:
  -----------
  tcg: Enforce single page access in probe_write()

Let's enforce the interface restriction.

Signed-off-by: David Hildenbrand <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 3a9576ec98cf87ac29e6e3aa885d6c782f918f73
      
https://github.com/qemu/qemu/commit/3a9576ec98cf87ac29e6e3aa885d6c782f918f73
  Author: David Hildenbrand <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M target/mips/op_helper.c

  Log Message:
  -----------
  mips/tcg: Call probe_write() for CONFIG_USER_ONLY as well

Let's call it also for CONFIG_USER_ONLY. While at it, add a FIXME and get
rid of one local variable.

MIPS code probably needs a bigger refactoring in regards of
ensure_writable_pages(), similar to s390x, so for example, watchpoints
can be handled reliably later. The actually accessed addresses should
be probed only, not full pages.

Signed-off-by: David Hildenbrand <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 200aa7a527dd2af04a0cf524a44596e89db6d4d6
      
https://github.com/qemu/qemu/commit/200aa7a527dd2af04a0cf524a44596e89db6d4d6
  Author: David Hildenbrand <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M target/hppa/op_helper.c

  Log Message:
  -----------
  hppa/tcg: Call probe_write() also for CONFIG_USER_ONLY

We now have a variant for CONFIG_USER_ONLY as well.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 9cd9cdaefc2be7a7e26684734bd334b717c50e5a
      
https://github.com/qemu/qemu/commit/9cd9cdaefc2be7a7e26684734bd334b717c50e5a
  Author: David Hildenbrand <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M target/s390x/mem_helper.c

  Log Message:
  -----------
  s390x/tcg: Pass a size to probe_write() in do_csst()

... and also call it for CONFIG_USER_ONLY. This function probably will
also need some refactoring in regards to probing, however, we'll have to
come back to that later, once cleaning up the other mem helpers.

The alignment check always makes sure that the write access falls into a
single page.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: fef39ccd567032d3ad520ed80f3576068e6eb2e3
      
https://github.com/qemu/qemu/commit/fef39ccd567032d3ad520ed80f3576068e6eb2e3
  Author: David Hildenbrand <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c
    M include/exec/exec-all.h

  Log Message:
  -----------
  tcg: Make probe_write() return a pointer to the host page

... similar to tlb_vaddr_to_host(); however, allow access to the host
page except when TLB_NOTDIRTY or TLB_MMIO is set.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: c25c283df0f08582df29f1d5d7be1516b851532d
      
https://github.com/qemu/qemu/commit/c25c283df0f08582df29f1d5d7be1516b851532d
  Author: David Hildenbrand <address@hidden>
  Date:   2019-09-03 (Tue, 03 Sep 2019)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c
    M include/exec/exec-all.h

  Log Message:
  -----------
  tcg: Factor out probe_write() logic into probe_access()

Let's also allow to probe other access types.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 9de65783e188b6cc3816847e03602864921bf504
      
https://github.com/qemu/qemu/commit/9de65783e188b6cc3816847e03602864921bf504
  Author: Peter Maydell <address@hidden>
  Date:   2019-09-04 (Wed, 04 Sep 2019)

  Changed paths:
    M MAINTAINERS
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c
    M exec.c
    M hw/intc/armv7m_nvic.c
    M hw/s390x/s390-pci-inst.c
    M hw/vfio/pci-quirks.c
    M hw/virtio/virtio-pci.c
    M include/exec/cpu-all.h
    M include/exec/exec-all.h
    M include/exec/memattrs.h
    A include/exec/memop.h
    M include/exec/memory.h
    M include/hw/core/cpu.h
    M memory.c
    M memory_ldst.inc.c
    M target/alpha/translate.c
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate-sve.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/hppa/op_helper.c
    M target/hppa/translate.c
    M target/i386/translate.c
    M target/m68k/translate.c
    M target/microblaze/translate.c
    M target/mips/op_helper.c
    M target/mips/translate.c
    M target/openrisc/translate.c
    M target/ppc/translate.c
    M target/riscv/insn_trans/trans_rva.inc.c
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/s390x/mem_helper.c
    M target/s390x/translate.c
    M target/s390x/translate_vx.inc.c
    M target/sparc/cpu.h
    M target/sparc/mmu_helper.c
    M target/sparc/translate.c
    M target/tilegx/translate.c
    M target/tricore/translate.c
    M tcg/README
    M tcg/aarch64/tcg-target.inc.c
    M tcg/arm/tcg-target.inc.c
    M tcg/i386/tcg-target.inc.c
    M tcg/mips/tcg-target.inc.c
    M tcg/optimize.c
    M tcg/ppc/tcg-target.inc.c
    M tcg/riscv/tcg-target.inc.c
    M tcg/s390/tcg-target.inc.c
    M tcg/sparc/tcg-target.inc.c
    M tcg/tcg-op.c
    M tcg/tcg-op.h
    M tcg/tcg.c
    M tcg/tcg.h
    M trace/mem-internal.h
    M trace/mem.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190903' into staging

Allow page table bit to swap endianness.
Reorganize watchpoints out of i/o path.
Return host address from probe_write / probe_access.

# gpg: Signature made Tue 03 Sep 2019 16:47:50 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Richard Henderson <address@hidden>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20190903: (36 commits)
  tcg: Factor out probe_write() logic into probe_access()
  tcg: Make probe_write() return a pointer to the host page
  s390x/tcg: Pass a size to probe_write() in do_csst()
  hppa/tcg: Call probe_write() also for CONFIG_USER_ONLY
  mips/tcg: Call probe_write() for CONFIG_USER_ONLY as well
  tcg: Enforce single page access in probe_write()
  tcg: Factor out CONFIG_USER_ONLY probe_write() from s390x code
  s390x/tcg: Fix length calculation in probe_write_access()
  s390x/tcg: Use guest_addr_valid() instead of h2g_valid() in 
probe_write_access()
  tcg: Check for watchpoints in probe_write()
  cputlb: Handle watchpoints via TLB_WATCHPOINT
  cputlb: Remove double-alignment in store_helper
  cputlb: Fix size operand for tlb_fill on unaligned store
  exec: Factor out cpu_watchpoint_address_matches
  cputlb: Fold TLB_RECHECK into TLB_INVALID_MASK
  exec: Factor out core logic of check_watchpoint()
  exec: Move user-only watchpoint stubs inline
  target/sparc: sun4u Invert Endian TTE bit
  target/sparc: Add TLB entry with attributes
  cputlb: Byte swap memory transaction attribute
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/da9e0c272147...9de65783e188
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