[Qemu-commits] [qemu/qemu] 2bd5f4: target/arm: generate a custom MIDR for -cpu max

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 2bd5f41c00686a1f847a60824d0375f3df2c26bf
      
https://github.com/qemu/qemu/commit/2bd5f41c00686a1f847a60824d0375f3df2c26bf
  Author: Alex Bennée <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: generate a custom MIDR for -cpu max

While most features are now detected by probing the ID_* registers
kernels can (and do) use MIDR_EL1 for working out of they have to
apply errata. This can trip up warnings in the kernel as it tries to
work out if it should apply workarounds to features that don't
actually exist in the reported CPU type.

Avoid this problem by synthesising our own MIDR value.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a6b3ed2348dc06623622fefec6753296d431f155
      
https://github.com/qemu/qemu/commit/a6b3ed2348dc06623622fefec6753296d431f155
  Author: Damien Hedde <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M hw/misc/zynq_slcr.c

  Log Message:
  -----------
  hw/misc/zynq_slcr: use standard register definition

Replace the zynq_slcr registers enum and macros using the
hw/registerfields.h macros.

Signed-off-by: Damien Hedde <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 88e1b59ee30950a66ea28b740914bf603fa9a1ec
      
https://github.com/qemu/qemu/commit/88e1b59ee30950a66ea28b740914bf603fa9a1ec
  Author: Aaron Hill <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M hw/net/imx_fec.c

  Log Message:
  -----------
  Set ENET_BD_BDU in I.MX FEC controller

This commit properly sets the ENET_BD_BDU flag once the emulated FEC controller
has finished processing the last descriptor. This is done for both transmit
and receive descriptors.

This allows the QNX 7.0.0 BSP for the Sabrelite board (which can be
found at http://blackberry.qnx.com/en/developers/bsp) to properly
control the FEC. Without this patch, the BSP ethernet driver will never
re-use FEC descriptors, as the unset ENET_BD_BDU flag will cause
it to believe that the descriptors are still in use by the NIC.

Note that Linux does not appear to use this field at all, and is
unaffected by this patch.

Without this patch, QNX will think that the NIC is still processing its
transaction descriptors, and won't send any more data over the network.

For reference:

On page 1192 of the I.MX 6DQ reference manual revision (Rev. 5, 06/2018),
which can be found at 
https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-6-processors/i.mx-6quad-processors-high-performance-3d-graphics-hd-video-arm-cortex-a9-core:i.MX6Q?&tab=Documentation_Tab&linkline=Application-Note

the 'BDU' field is described as follows for the 'Enhanced transmit
buffer descriptor':

'Last buffer descriptor update done. Indicates that the last BD data has been 
updated by
uDMA. This field is written by the user (=0) and uDMA (=1).'

The same description is used for the receive buffer descriptor.

Signed-off-by: Aaron Hill <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c1d5f50f094ab204accfacc2ee6aafc9601dd5c4
      
https://github.com/qemu/qemu/commit/c1d5f50f094ab204accfacc2ee6aafc9601dd5c4
  Author: Peter Maydell <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Factor out 'generate singlestep exception' function

Factor out code to 'generate a singlestep exception', which is
currently repeated in four places.

To do this we need to also pull the identical copies of the
gen-exception() function out of translate-a64.c and translate.c
into translate.h.

(There is a bug in the code: we're taking the exception to the wrong
target EL.  This will be simpler to fix if there's only one place to
do it.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 8bd587c1066f4456ddfe611b571d9439a947d74c
      
https://github.com/qemu/qemu/commit/8bd587c1066f4456ddfe611b571d9439a947d74c
  Author: Peter Maydell <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Fix routing of singlestep exceptions

When generating an architectural single-step exception we were
routing it to the "default exception level", which is to say
the same exception level we execute at except that EL0 exceptions
go to EL1. This is incorrect because the debug exception level
can be configured by the guest for situations such as single
stepping of EL0 and EL1 code by EL2.

We have to track the target debug exception level in the TB
flags, because it is dependent on CPU state like HCR_EL2.TGE
and MDCR_EL2.TDE. (That we were previously calling the
arm_debug_target_el() function to determine dc->ss_same_el
is itself a bug, though one that would only have manifested
as incorrect syndrome information.) Since we are out of TB
flag bits unless we want to expand into the cs_base field,
we share some bits with the M-profile only HANDLER and
STACKCHECK bits, since only A-profile has this singlestep.

Fixes: https://bugs.launchpad.net/qemu/+bug/1838913
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 331b1ca616cb708db30dab68e3262d286e687f24
      
https://github.com/qemu/qemu/commit/331b1ca616cb708db30dab68e3262d286e687f24
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Pass in pc to thumb_insn_is_16bit

This function is used in two different contexts, and it will be
clearer if the function is given the address to which it applies.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 43722a6d4f0c92f7e7e1e291580039b0f9789df1
      
https://github.com/qemu/qemu/commit/43722a6d4f0c92f7e7e1e291580039b0f9789df1
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Introduce pc_curr

Add a new field to retain the address of the instruction currently
being translated.  The 32-bit uses are all within subroutines used
by a32 and t32.  This will become less obvious when t16 support is
merged with a32+t32, and having a clear definition will help.

Convert aarch64 as well for consistency.  Note that there is one
instance of a pre-assert fprintf that used the wrong value for the
address of the current instruction.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fdbcf6329d0c2984c55d7019419a72bf8e583c36
      
https://github.com/qemu/qemu/commit/fdbcf6329d0c2984c55d7019419a72bf8e583c36
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Introduce read_pc

We currently have 3 different ways of computing the architectural
value of "PC" as seen in the ARM ARM.

The value of s->pc has been incremented past the current insn,
but that is all.  Thus for a32, PC = s->pc + 4; for t32, PC = s->pc;
for t16, PC = s->pc + 2.  These differing computations make it
impossible at present to unify the various code paths.

With the newly introduced s->pc_curr, we can compute the correct
value for all cases, using the formula given in the ARM ARM.

This changes the behaviour for load_reg() and load_reg_var()
when called with reg==15 from a 32-bit Thumb instruction:
previously they would have returned the incorrect value
of pc_curr + 6, and now they will return the architecturally
correct value of PC, which is pc_curr + 4. This will not
affect well-behaved guest software, because all of the places
we call these functions from T32 code are instructions where
using r15 is UNPREDICTABLE. Using the architectural PC value
here is more consistent with the T16 and A32 behaviour.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
[PMM: added commit message note about UNPREDICTABLE T32 cases]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 16e0d8234ef9291747332d2c431e46808a060472
      
https://github.com/qemu/qemu/commit/16e0d8234ef9291747332d2c431e46808a060472
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Introduce add_reg_for_lit

Provide a common routine for the places that require ALIGN(PC, 4)
as the base address as opposed to plain PC.  The two are always
the same for A32, but the difference is meaningful for thumb mode.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4818c3743b0e0095fdcecd24457da9b3443730ab
      
https://github.com/qemu/qemu/commit/4818c3743b0e0095fdcecd24457da9b3443730ab
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Remove redundant s->pc & ~1

The thumb bit has already been removed from s->pc, and is always even.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a04159166b880b505ccadc16f2fe84169806883d
      
https://github.com/qemu/qemu/commit/a04159166b880b505ccadc16f2fe84169806883d
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Replace s->pc with s->base.pc_next

We must update s->base.pc_next when we return from the translate_insn
hook to the main translator loop.  By incrementing s->base.pc_next
immediately after reading the insn word, "pc_next" contains the address
of the next instruction throughout translation.

All remaining uses of s->pc are referencing the address of the next insn,
so this is now a simple global replacement.  Remove the "s->pc" field.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a767fac802f6fa6220330ea6f408dde2fb41db22
      
https://github.com/qemu/qemu/commit/a767fac802f6fa6220330ea6f408dde2fb41db22
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Replace offset with pc in gen_exception_insn

The offset is variable depending on the instruction set, whereas
we have stored values for the current pc and the next pc.  Passing
in the actual value is clearer in intent.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: aee828e7541a5895669ade3a4b6978382b6b094a
      
https://github.com/qemu/qemu/commit/aee828e7541a5895669ade3a4b6978382b6b094a
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Replace offset with pc in gen_exception_internal_insn

The offset is variable depending on the instruction set.
Passing in the actual value is clearer in intent.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 06bcbda3f64d464b6ecac789bce4bd69f199cd68
      
https://github.com/qemu/qemu/commit/06bcbda3f64d464b6ecac789bce4bd69f199cd68
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Remove offset argument to gen_exception_bkpt_insn

Unlike the other more generic gen_exception{,_internal}_insn
interfaces, breakpoints always refer to the current instruction.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3cb36637157088892e9e33ddb1034bffd1251d3b
      
https://github.com/qemu/qemu/commit/3cb36637157088892e9e33ddb1034bffd1251d3b
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Use unallocated_encoding for aarch32

Promote this function from aarch64 to fully general use.
Use it to unify the code sequences for generating illegal
opcode exceptions.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 640581a06d14e2d0d3c3ba79b916de6bc43578b0
      
https://github.com/qemu/qemu/commit/640581a06d14e2d0d3c3ba79b916de6bc43578b0
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/helper.h
    M target/arm/op_helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Remove helper_double_saturate

Replace x = double_saturate(y) with x = add_saturate(y, y).
There is no need for a separate more specialized helper.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b9e758f0b5bc64b5800432c0a436dd1afc98ba33
      
https://github.com/qemu/qemu/commit/b9e758f0b5bc64b5800432c0a436dd1afc98ba33
  Author: Andrew Jones <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/cpu64.c
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  target/arm/cpu64: Ensure kvm really supports aarch64=off

If -cpu <cpu>,aarch64=off is used then KVM must also be used, and it
and the host must support running the vcpu in 32-bit mode. Also, if
-cpu <cpu>,aarch64=on is used, then it doesn't matter if kvm is
enabled or not.

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ae502508f83e06abddab3ac1a11dd822718472e1
      
https://github.com/qemu/qemu/commit/ae502508f83e06abddab3ac1a11dd822718472e1
  Author: Andrew Jones <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/kvm.c
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  target/arm/cpu: Ensure we can use the pmu with kvm

We first convert the pmu property from a static property to one with
its own accessors. Then we use the set accessor to check if the PMU is
supported when using KVM. Indeed a 32-bit KVM host does not support
the PMU, so this check will catch an attempt to use it at property-set
time.

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7b351d98709d3f77d6bb18562e1bf228862b0d57
      
https://github.com/qemu/qemu/commit/7b351d98709d3f77d6bb18562e1bf228862b0d57
  Author: Andrew Jones <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm/helper: zcr: Add build bug next to value range assumption

The current implementation of ZCR_ELx matches the architecture, only
implementing the lower four bits, with the rest RAZ/WI. This puts
a strict limit on ARM_MAX_VQ of 16. Make sure we don't let ARM_MAX_VQ
grow without a corresponding update here.

Suggested-by: Dave Martin <address@hidden>
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 46417784d21c89446763f2047228977bdc267895
      
https://github.com/qemu/qemu/commit/46417784d21c89446763f2047228977bdc267895
  Author: Andrew Jones <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm/cpu: Use div-round-up to determine predicate register array size

Unless we're guaranteed to always increase ARM_MAX_VQ by a multiple of
four, then we should use DIV_ROUND_UP to ensure we get an appropriate
array size.

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4ed9d9f894a7ab19f5b927fe0d833effeabac0ce
      
https://github.com/qemu/qemu/commit/4ed9d9f894a7ab19f5b927fe0d833effeabac0ce
  Author: Andrew Jones <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/kvm64.c

  Log Message:
  -----------
  target/arm/kvm64: Fix error returns

A couple return -EINVAL's forgot their '-'s.

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 30e3537fa5948e6346d23422b8397dee086a434e
      
https://github.com/qemu/qemu/commit/30e3537fa5948e6346d23422b8397dee086a434e
  Author: Andrew Jones <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/kvm64.c

  Log Message:
  -----------
  target/arm/kvm64: Move the get/put of fpsimd registers out

Move the getting/putting of the fpsimd registers out of
kvm_arch_get/put_registers() into their own helper functions
to prepare for alternatively getting/putting SVE registers.

No functional change.

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 191f4bfe8d6cf0c7d5cd7f84cd7076e32e3745dd
      
https://github.com/qemu/qemu/commit/191f4bfe8d6cf0c7d5cd7f84cd7076e32e3745dd
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use tcg_gen_extract_i32 for shifter_out_im

Extract is a compact combination of shift + and.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d1f8755fc93911f5b27246b1da794542d222fa1b
      
https://github.com/qemu/qemu/commit/d1f8755fc93911f5b27246b1da794542d222fa1b
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB

Use deposit as the composit operation to merge the
bits from the two inputs.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 464eaa9571fae5867d9aea7d7209c091c8a50223
      
https://github.com/qemu/qemu/commit/464eaa9571fae5867d9aea7d7209c091c8a50223
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Remove redundant shift tests

The immediate shift generator functions already test for,
and eliminate, the case of a shift by zero.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dd861b3f29be97a9e3cdb9769dcbc0c7d7825185
      
https://github.com/qemu/qemu/commit/dd861b3f29be97a9e3cdb9769dcbc0c7d7825185
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use ror32 instead of open-coding the operation

The helper function is more documentary, and also already
handles the case of rotate by zero.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: adefba76e8bf10dfb342094d2f5debfeedb1a74d
      
https://github.com/qemu/qemu/commit/adefba76e8bf10dfb342094d2f5debfeedb1a74d
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use tcg_gen_rotri_i32 for gen_swap_half

Rotate is the more compact and obvious way to swap 16-bit
elements of a 32-bit word.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5f8cd06ebcf57420be8fea4574de2e074de46709
      
https://github.com/qemu/qemu/commit/5f8cd06ebcf57420be8fea4574de2e074de46709
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR

All of the inputs to these instructions are 32-bits.  Rather than
extend each input to 64-bits and then extract the high 32-bits of
the output, use tcg_gen_muls2_i32 and other 32-bit generator functions.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 664b7e3b97d6376f3329986c465b3782458b0f8b
      
https://github.com/qemu/qemu/commit/664b7e3b97d6376f3329986c465b3782458b0f8b
  Author: Richard Henderson <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word

Separate shift + extract low will result in one extra insn
for hosts like RISC-V, MIPS, and Sparc.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: afd760539308a5524accf964107cdb1d54a059e3
      
https://github.com/qemu/qemu/commit/afd760539308a5524accf964107cdb1d54a059e3
  Author: Peter Maydell <address@hidden>
  Date:   2019-08-16 (Fri, 16 Aug 2019)

  Changed paths:
    M hw/misc/zynq_slcr.c
    M hw/net/imx_fec.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/kvm.c
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h
    M target/arm/op_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190816' 
into staging

target-arm queue:
 * target/arm: generate a custom MIDR for -cpu max
 * hw/misc/zynq_slcr: refactor to use standard register definition
 * Set ENET_BD_BDU in I.MX FEC controller
 * target/arm: Fix routing of singlestep exceptions
 * refactor a32/t32 decoder handling of PC
 * minor optimisations/cleanups of some a32/t32 codegen
 * target/arm/cpu64: Ensure kvm really supports aarch64=off
 * target/arm/cpu: Ensure we can use the pmu with kvm
 * target/arm: Minor cleanups preparatory to KVM SVE support

# gpg: Signature made Fri 16 Aug 2019 14:15:55 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190816: (29 commits)
  target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word
  target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR
  target/arm: Use tcg_gen_rotri_i32 for gen_swap_half
  target/arm: Use ror32 instead of open-coding the operation
  target/arm: Remove redundant shift tests
  target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB
  target/arm: Use tcg_gen_extract_i32 for shifter_out_im
  target/arm/kvm64: Move the get/put of fpsimd registers out
  target/arm/kvm64: Fix error returns
  target/arm/cpu: Use div-round-up to determine predicate register array size
  target/arm/helper: zcr: Add build bug next to value range assumption
  target/arm/cpu: Ensure we can use the pmu with kvm
  target/arm/cpu64: Ensure kvm really supports aarch64=off
  target/arm: Remove helper_double_saturate
  target/arm: Use unallocated_encoding for aarch32
  target/arm: Remove offset argument to gen_exception_bkpt_insn
  target/arm: Replace offset with pc in gen_exception_internal_insn
  target/arm: Replace offset with pc in gen_exception_insn
  target/arm: Replace s->pc with s->base.pc_next
  target/arm: Remove redundant s->pc & ~1
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e018ccb3fbfa...afd760539308